KR102427868B1 - MIPI D-PHY sending circuit and device - Google Patents

Abstract

The present invention provides a MIPI D-PHY sending circuit and device, the MIPI D-PHY sending circuit comprising: an FPGA reconfigurable sending clock circuit; an FPGA reconfigurable DPHY_IO dispatch circuit coupled to the FPGA reconfigurable dispatch clock circuit; data packet recombination circuit; and an FPGA reconfigurable DPHY_IO sending circuit connected to the data packet recombination circuit, wherein a matching design is performed for the MIPI D-PHY sending circuit and the MIPI protocol layer through the FPGA reconfigurable MIPI D-PHY sending circuit, so that the MIPI D -By adjusting the driving capability of the PHY sending circuit, it can effectively reduce the circuit area, improve the circuit resource utilization, improve the sending performance and improve the compatibility, and satisfy the various application requirements of CSI-2 and DSI. may do it

Description

MIPI D-PHY sending circuit and device

The present invention claims the priority of the Chinese application filed on May 29, 2019 with the application number CN201910458822.7, and all contents thereof are incorporated into the text by reference.

FIELD OF THE INVENTION The present invention relates to the field of high-speed serial bus technology, and more particularly to MIPI D-PHY sending circuits and devices.

Mobile Industry Processor Interface (MIPI) DPHY is a standard general-purpose interface for the mobile industry processor interface. As the MIPI D-PHY interface becomes more widely used in the mobile industry, the demand for variety of MIPI D-PHY support modes is also increasing. However, the existing MIPI D-PHY circuits all use ASIC-only circuits, so they cannot be flexibly configured for application modes, and the dedicated MIPI D-PHY circuits cannot meet the needs of different application situations. In addition, since the general-purpose MIPI D-PHY circuit and the protocol (CSI-2/DSI) circuit are independent, both the MIPI D-PHY and MIPI protocol layers have to process the protocol for the circuit. exists

The technical problem to be solved by the present invention is that the existing dedicated MIPI D-PHY circuit cannot satisfy different application situation requirements, and the general-purpose MIPI D-PHY circuit and the protocol (CSI-2 protocol/DSI protocol) circuit are independent. , since both the MIPI D-PHY and the MIPI protocol layer have to process the protocol for the circuit, some functions overlap and there is a problem of wasting resources.

In order to solve the above technical problem, the present invention provides a MIPI D-PHY sending circuit, wherein the MIPI D-PHY sending circuit includes: an FPGA reconfigurable sending clock circuit; and an FPGA reconfigurable DPHY_IO dispatch circuit coupled to the FPGA reconfigurable dispatch clock circuit.

Optionally, the MIPI D-PHY sending circuitry comprises: a data packet recombination circuit; and an FPGA reconfigurable DPHY_IO sending circuit connected to the data packet recombination circuit, wherein the data packet recombination circuit repackages the data to be sent according to a protocol and then sends it to the FPGA reconfigurable DPHY_IO sending circuit.

Optionally, the MIPI D-PHY sending circuit performs data transmission based on a CSI-2 protocol or a DSI protocol.

Optionally, the FPGA reconfigurable dispatch clock circuit comprises a PLL module, the FPGA reconfigurable DPHY_IO dispatch circuit comprises a DPHY_IO clock circuit, wherein the PLL module comprises a clock link clock signal output circuit, a data link clock signal output circuit wherein the DPHY_IO clock circuit each comprises a clock link clock channel coupled to the clock link clock signal output circuit, and a data link clock channel coupled to the data link clock signal output circuit.

Optionally, the clock link clock channel comprises a first frequency division circuit CLKDIV, a first parallel serial conversion module OSERDES, and a first input output buffer IOB, wherein the first frequency division circuit CLKDIV is sent by the first PLL module Receive one clock channel data, perform frequency division on the clock channel data, and then obtain first parallel data, and transmit the first parallel data in parallel to a first parallel serial conversion module OSERDES, and the first parallel serial data The conversion module OSERDES converts the first parallel data into first serial data and transmits it to the first input output buffer IOB.

Optionally, the data link clock channel comprises a second frequency division circuit CLKDIV, a second parallel-to-serial conversion module OSERDES, and a second input output buffer IOB, wherein the second frequency division circuit CLKDIV comprises data sent by the PLL module receiving channel data, performing frequency division on the data channel data, obtaining second parallel data, and transmitting the second parallel data to the second parallel-serial conversion module OSERDES in parallel, and the second parallel-serial conversion The module OSERDES converts the second parallel data into second serial data and transmits it to the second input output buffer IOB.

Optionally, the FPGA reconfigurable DPHY_IO dispatch circuit includes up to four data output channels.

Optionally, the data output channel comprises the DPHY_IO sending circuit and an external analog circuit, the DPHY_IO sending circuit being coupled to the external analog circuit.

Optionally, the DPHY_IO sending circuit comprises an IOL module and a sending circuit coupled to the IOL module, wherein the IOL module receives low-speed data or high-speed data; the sending circuit outputs low-speed data or high-speed data to the external port; The external analog circuit is connected to the external port.

Optionally, the number of the IOL modules is four, and the four IOL modules include two first IOL modules for transmitting low-speed data and two second IOL modules for transmitting high-speed data.

Optionally, the MIPI D-PHY sending circuit further comprises a first resistor, wherein the first IOL module is connected to the external port through the first resistor, wherein the resistance value of the first resistor is 330 ohms .

Optionally, the MIPI D-PHY sending circuit further comprises a second resistor, the second IOL module is connected to the external port through the second resistor, the resistance value of the second resistor is 50 ohms .

Optionally, the level standard of the high-speed data is LVDS.

Optionally, the high-speed data is a current of 2-4 mA.

Optionally, the level standard of the low-speed data is LVCMOS12.

Optionally, the high-speed data is a current of 2-12 mA.

Optionally, the clock link clock channel is a unidirectional channel and the data link clock channel is a unidirectional channel or a bidirectional channel.

Optionally, the MIPI D-PHY sending circuit is for generating a clock in a clock path and a clock in a data path, wherein the clock in the clock path and the clock in the data path are out of phase by a predetermined phase.

In addition, the present invention further provides a device including the above-described MIPI D-PHY sending circuit.

Optionally, the device comprises a smart phone, a tablet PC, a notebook computer, a PDA and an on-board computer.

MIPI D-PHYMIPI D-PHYMIPI D-PHY

1 is a structural schematic diagram of a MIPI D-PHY sending circuit provided by Embodiment 1 of the present invention.
Fig. 2 is a structural schematic diagram of a clock circuit logical layer circuit of the MIPI D-PHY sending circuit provided in Embodiment 1 of the present invention.
3 is a structural schematic diagram of a DPHY_IO sending circuit of the MIPI D-PHY sending circuit provided by Embodiment 1 of the present invention.
4 is a schematic diagram of a work flow of a MIPI D-PHY sending circuit provided by Embodiment 2 of the present invention.

An embodiment of the present invention will be described in detail with reference to the drawings through specific embodiments below so that the object, means and advantages of the present invention are more clear. It should be understood that the specific embodiments described herein are intended to interpret the present invention and not to limit it.

Example 1

Since the existing dedicated MIPI D-PHY circuit cannot meet the different application requirements, and the general-purpose MIPI D-PHY circuit and the protocol (CSI-2/DSI) circuit are independent, both the MIPI D-PHY and MIPI protocol layers are In order to solve the problem of wasting resources due to overlapping of some functions because protocol processing has to be performed on the circuit, a MIPI D-PHY sending circuit is provided.

It should be understood that the present invention uses an FPGA (Field-Programmable Gate Array, Field-Programmable Gate Array) to realize the reconfiguration of the MIPI D-PHY sending circuit, where MIPI is a mobile industrial processor interface, its formal name is Mobile Industry Processor Interface Here, MIPI D-PHY is one physical layer of MIPI, and the protocol layer has two types of CSI and DSI, where CSI is mainly used for image connection, for example, an image sensor.

Referring to FIG. 1, FIG. 1 is a structural schematic diagram of a MIPI D-PHY sending circuit provided by an embodiment of the present invention. The MIPI D-PHY dispatch circuit 100 includes an FPGA reconfigurable dispatch clock circuit 110, an FPGA reconfigurable DPHY_IO dispatch circuit 120 coupled to the FPGA reconfigurable dispatch clock circuit 110, a data packet recombination circuit (prg_tx_hs_pkg) an FPGA reconfigurable DPHY_IO dispatch circuit (120) comprising (130) and an FPGA reconfigurable DPHY_IO dispatch circuit (120) coupled to the data packet recombination circuit (130), the FPGA reconfigurable DPHY_IO dispatch circuit (120) coupled to the FPGA reconfigurable dispatch clock circuit (110) below ) is abbreviated as DPHY_IO clock circuit 121 , and the FPGA reconfigurable DPHY_IO dispatch circuit 120 connected to the data packet recombination circuit 130 is abbreviated as DPHY_IO dispatch circuit 122 .

In this embodiment, the FPGA reconfigurable dispatch clock circuit 110 is a PLL module, the PLL module can generate a necessary clock according to user configuration, it should be explained that there are two types of generated clocks, one of which is a clock The clock of the passage and the other of the clock of the data passage, the two clocks maintain a constant phase relationship to satisfy the building holding time required for the digital circuit. The DPHY_IO clock circuit 121 receives a clock of a clock channel and a clock of a data channel that the PLL module has transmitted through hs_clk and hs_clk_i, respectively, where hs_cl is the driving clock of the clock channel, and hs_clk_i is the driving clock of the data channel. output by the clock channel. The data packet recombination circuit (prg_tx_hs_pkg) 130 repackages the received user data according to the protocol request and sends it to the DPHY_IO sending circuit 122 and output by the data channel.

It should be explained that the data packet recombination circuit 130 processes the received user data, converts it into a format that can be received and processed by the DPHY_IO sending circuit 122 according to the protocol request, and then repackages it and sends it.

In this embodiment, matching is performed with the MIPI D-PHY sending circuit 100 and the CSI-2 protocol/DSI protocol, that is, the MIPI D-PHY sending circuit 100 is based on the CSI-2 protocol or the DSI protocol. Thus, data transmission can proceed. Specifically, it is up to the user to decide which protocol to select, and this method can effectively reduce the circuit area and improve the resource usage rate of the circuit.

In this embodiment, the MIPI D-PHY sending circuit uses a pair of source synchronization clocks and 1 to 4 pairs of clock data lines to carry out data transmission, it should be explained that the clock channel is unidirectional and the data channel is unidirectional or in both directions.

In this embodiment, please refer to FIG. 2 for the transmission of the clock signal. The PLL module includes a clock signal input terminal (clk_in) 111, a first clock signal output terminal (clkout0) 112, a second clock signal output terminal (clkout1) 113, a clock link clock signal output circuit 114, and a data link clock a signal output circuit (115), the DPHY_IO clock circuit comprising a clock link clock channel (1211) coupled to a clock link clock signal output circuit (114), and a data link coupled to a data link clock signal output circuit (115), respectively a clock channel 1212, the clock link clock channel comprising a frequency division circuit (CLKDIV) 1211a, a parallel serial conversion module (OSERDES) 1211b, an input output buffer (IOB) 1211c, and a data link The clock channel includes a frequency division circuit (CLKDIV) 1212a, a parallel-to-serial conversion module (OSERDES) 1212b, and an input output buffer (IOB) 1212c.

Specifically, the clock signal input terminal (clk_in) 111 of the PLL module receives a user-configured clock signal, the clock signal includes a clock signal of a clock path and a clock signal of a data path, and the clock signal of the clock path is The clock link clock channel 1211 is entered through the clock link clock signal output circuit 114 by the first clock signal output terminal clkout0 112, and the clock signal of the data path is transferred to the second clock signal output terminal clkout1 ( 113) enters the data link clock channel 1212 through the data link clock signal output circuit 115; The clock link clock channel 1211 receives a clock path clock signal, performs frequency division by a frequency division circuit (CLKDIV) 1211a, outputs two clock path clock signals, and a parallel serial conversion module (OSERDES) ( 1211b) converts the signal into a serial signal and transmits it to the input output buffer (IOB) 1211c, and outputs it to the external port 200 through the input output buffer (IOB) 1211c, and the output clock path clock signal The phases of are reversed; The data link clock channel 1212 receives a clock signal of a data path, performs frequency division by a frequency division circuit (CLKDIV) 1212a, and outputs two data path clock signals, and outputs a parallel serial conversion module (OSERDES). ) (1212b) to convert the signal into a serial signal and transmit it to the input output buffer (IOB) 1212c, output to the external port 200 through the input output buffer (IOB) 1212c, the output data path The phase of the clock signal is reversed.

It should be explained that the transmission of the data path clock signal corresponds to one data channel, and when the MIPI D-PHY sending circuit 100 operates, up to 4 channels can simultaneously perform data transmission, and each data channel is All correspond to one parallel-to-serial conversion module (OSERDES) 1212b and an input output buffer (IOB) 1212c, and each parallel-to-serial conversion module (OSERDES) 1212b are all frequency division circuits (CLKDIV) 1212a Receives two data path clock signals output after frequency division by .

In this embodiment, both the data channel and the clock channel of the MIPI D-PHY sending circuit are reconfigurable by the FPGA, and the signal of the data channel and the signal of the clock channel are phase adjustable.

In this embodiment, refer to FIG. 3 for a detailed operation flow of the DPHY_IO sending circuit.

The MIPI D-PHY sending circuit includes two transmission modes, a low speed mode (LP, Lower Power) and a high speed mode (HS, high speed), and the two modes work in common to transmit data and commands in the MIPI interface protocol layer. to realize

As shown in FIG. 3 , the DPHY_IO dispatch circuit 122 includes an IOL module 1221 and a dispatch circuit 1222 . In this embodiment, the DPHY_IO sending circuit includes four IOL modules 1221, and the four IOL modules 1221 include two first IOL modules 1221a for transmitting low-speed data and two first IOL modules 1221a for transmitting high-speed data. and two second IOL modules 1221b. After receiving the low-speed data, the low-speed data is output from the IOB (I/O buffer, not shown) of IO0 (stage p) and IO3 (stage n) to the external port 200, and the level standard uses LVCMOS12. After sending LP11->LP01-> LP00, TS of high-speed channel is set to 0, high-speed channel enabling is opened, and when LP11 is sent again, TS of high-speed channel is set to 1 and high-speed channel close the While the high-speed channel is open, the low-speed channel must send LP00. It should be noted that LP01 indicates that the P stage is 0, the n stage is 1, and the others are similar. After receiving the high-speed data, the two second IOL modules 1221b mix with each other to process the data, and the high-speed signal uses a differential level LVDS (Low Voltage Differential Signaling, Low Voltage Differential Signaling) standard, and enters the IOL module to realize parallel-to-serial conversion (OSERDES). For example, 8-bit parallel data is converted to serial data, and output to the external port 200 through IOB (I/O buffer, not shown) of IO1 and IO2, IOB (I/O buffer, not shown) ) must be controlled, TS is 0, close the tri-state enabling, the signal can be output from the IOB to the external port 200, and when TS is 1, open the tri-state enabling and close the external port ( 200) is enabled in a high resistance state. IO0, IO1, IO2 and IO3 are connected to the external analog circuit 300 through the external port 200, and a first resistor 140 is connected in series to the high-speed channels IO1 and IO2, where the first resistor is a 330 ohm resistor. , and a second resistor 150 is connected in series to the low-speed channels IO0 and IO4, and the second resistor may be a 50 ohm resistor, realizing electrical characteristics conforming to the MIPI norms requirements, and the electrical characteristics are common mode voltage (DC characteristic) and differential amplitude (AC characteristic). Here, tx_byte_i_clk in FIG. 2 is a byte clock of a clock channel, and it should be understood that another related name in FIG. 2 may be a corresponding byte clock.

In this embodiment, the driving capability of the DPHY_IO sending circuit can be adjusted through the IOB, using the LVDS level standard in the high-speed mode, can select 2mA~4mA; In low speed mode, it uses LVCMOS12 level standard and can select 2~12mA, it should be explained, use different drive current to adapt to different application situations.

An embodiment of the present invention provides a MIPI D-PHY dispatch circuit (100), which includes an FPGA reconfigurable dispatch clock circuit (110), and an FPGA reconfigurable DPHY_IO dispatch circuit coupled to the FPGA reconfigurable dispatch clock circuit (110). 120, a data packet recombination circuit 130, and an FPGA reconfigurable DPHY_IO dispatch circuit 120 coupled to the data packet recombination circuit 130, wherein the MIPI D-PHY dispatch circuit 110 and the MIPI protocol layer matching design, effectively reducing the circuit area and improving the resource utilization rate of the circuit, improving the sending performance by adjusting the phase for the MIPI D-PHY data channel and the clock channel The drive capability can be adjusted to improve the compatibility, and the MIPI D-PHY sending circuit can meet the needs of various applications of CSI-2 and DSI.

Example 2

On the basis of the above embodiment, this embodiment provides a four-channel protocol sending flow chart of the MIPI D-PHY sending circuit, specifically refer to FIG. 4 .

Enters standby IDLE state during system initialization.

S401: Detects whether initialization is completed in IDLE state, increases init_done upon completion, enters ST_LP_STOP state, and the long and short initialization time is set by the user. Here, ST_LP_STOP is the low speed idle state.

It should be explained that the detection of whether the initialization is completed can be determined according to whether or not the LP11 has been sent. In this embodiment, the long and short time is set by the user, the clock period is set by the PLL module of the FPGA reconfigurable outgoing clock circuit, and after setting the clock period well, the user configures the number of clock periods as needed Should be. The length of this time is determined by the number of clock cycles.

S402: Detect valid_hs signal in ST_LP_STOP state, requesting signal for high-speed data means sending high-speed data soon, enter ST_HS_RQST state, otherwise stop and wait.

S403: Send LP01 in ST_HS_RQST state, long and short time set by user, enter ST_HS_PRPR state when completed, otherwise stop and wait. Here, ST_HS_RQST is the high-speed request entry state.

S404: Send LP00 in ST_HS_PRPR state, long and short time set by user, enter ST_HS_GO state when finished, otherwise stop and wait. Here, ST_HS_PRPR is the fast ready entry state.

S405: Send high speed 0 in ST_HS_GO state, long and short time is set by user, enter ST_HS_SYNC state when finished, otherwise stop and wait. Here, ST_HS_GO is the high-speed conversion entry state.

S406: Send MIPI D-PHY synchronization head B8 in ST_HS_SYNC state, enter ST_HS_DATA state automatically. Here, ST_HS_SYNC is the high-speed data synchronization state.

It should be explained that the MIPI D-PHY synchronization head B8 is for positioning and synchronizing each data in the data transmission process. In other words, after the receiving end receives the alignment data, data transmission is possible.

S407: In the ST_HS_DATA state, it is detected whether valid_hs is “high”, if it is “high”, it stops in this state to send high-speed data of the user, and if it is “low”, it enters the ST_HS_TRAIL state.

It should be understood that the transmitted high-speed data is valid data. Here, ST_HS_DATA is the high-speed data state.

S408: Send a high-speed tail signal in ST_HS_TRAIL state, long and short time is set by the user, return to IDLE state when completed, or stop in this state. Here, ST_HS_TRAIL is the high-speed data packet tail transmission status.

It should be explained that the long and short duration of the time of this embodiment is set by the user, the clock period is set by the PLL module of the FPGA reconfigurable dispatch clock circuit, and after setting the clock period well, the user can set the clock period as needed. number must be configured. The length of this time is determined by the number of clock cycles.

In the present embodiment, the length of the high-speed tail signal may be determined according to a long or short duration of time.

The embodiment of the present invention provides a specific realization process of the MIPI D-PHY sending circuit, and through the FPGA reconfigurable MIPI D-PHY sending circuit, the matching design is carried out for the MIPI D-PHY sending circuit and the MIPI protocol layer, It effectively reduces the circuit area and improves the resource utilization rate of the circuit. By adjusting the phase of the MIPI D-PHY data channel and the clock channel, the sending performance is improved, the driving ability of the MIPI D-PHY sending circuit can be adjusted to improve compatibility, and the MIPI D-PHY sending circuit is CSI -2 and DSI can satisfy various application situation requirements.

Example 3

This embodiment provides a device, and the device may be a mobile smart device having a mirroring function, such as a smart phone, a tablet PC, a notebook computer, and a personal digital assistant (PDA), but is not limited thereto. Of course, it may be a fixed smart device such as a PC having a mirroring function or a vehicle-mounted computer, but is not limited thereto. The device includes the MIPI D-PHY sending circuit according to the above embodiment to realize the corresponding function, which will not be repeated herein.

Although the above has been described in detail with respect to the embodiments of the present invention in conjunction with specific embodiments, the specific implementation of the present invention is not limited by these descriptions. Those of ordinary skill in the art to which the present invention pertains may make some simple inferences or transformations under the premise of not departing from the spirit of the present invention.

Claims (20)

In the MIPI D-PHY sending circuit,
FPGA reconfigurable dispatch clock circuit; and
and an FPGA reconfigurable DPHY_IO dispatch circuit coupled to the FPGA reconfigurable dispatch clock circuit.
According to claim 1,
data packet recombination circuit; and
an FPGA reconfigurable DPHY_IO sending circuit coupled to the data packet recombination circuit;
MIPI D-PHY sending circuit, characterized in that the data packet recombination circuit repackages the data to be sent according to a protocol and then sends it to the FPGA reconfigurable DPHY_IO sending circuit.
According to claim 1,
and the MIPI D-PHY sending circuit performs data transmission based on the CSI-2 protocol or the DSI protocol.
4. The method according to any one of claims 1 to 3,
the FPGA reconfigurable dispatch clock circuit comprises a PLL module, the FPGA reconfigurable DPHY_IO dispatch circuit comprises a DPHY_IO clock circuit, the PLL module comprises a clock link clock signal output circuit, a data link clock signal output circuit, and wherein the DPHY_IO clock circuit comprises a clock link clock channel coupled to the clock link clock signal output circuit, and a data link clock channel coupled to the data link clock signal output circuit, respectively.
5. The method of claim 4,
the clock link clock channel includes a first frequency division circuit CLKDIV, a first parallel serial conversion module OSERDES, and a first input output buffer IOB;
The first frequency division circuit CLKDIV receives the clock channel data sent by the first PLL module, performs frequency division on the clock channel data, and then obtains first parallel data, and converts the first parallel data to the first MIPI D-PHY, characterized in that parallel transmission to a parallel-serial conversion module OSERDES, and the first parallel-serial conversion module OSERDES converts the first parallel data into first serial data and transmits to the first input output buffer IOB sending circuit.
5. The method of claim 4,
the data link clock channel includes a second frequency division circuit CLKDIV, a second parallel serial conversion module OSERDES, and a second input output buffer IOB;
The second frequency division circuit CLKDIV receives the data channel data sent by the PLL module, performs frequency division on the data channel data, and then obtains second parallel data, and divides the second parallel data into the second parallel data. MIPI D-PHY sending, characterized in that parallel transmission to a serial conversion module OSERDES, and the second parallel serial conversion module OSERDES converts the second parallel data into second serial data and transmits to the second input output buffer IOB Circuit.
According to claim 1,
and the FPGA reconfigurable DPHY_IO send circuit comprises up to 4 data output channels.
8. The method of claim 7,
and the data output channel comprises the DPHY_IO sending circuit and an external analog circuit, and the DPHY_IO sending circuit is connected to the external analog circuit.
9. The method of claim 8,
the DPHY_IO sending circuit includes an IOL module and a sending circuit coupled to the IOL module, wherein the IOL module receives low-speed data or high-speed data; the sending circuit outputs low-speed data or high-speed data to the external port; and the external analog circuit is connected to be connected to the external port.
10. The method of claim 9,
MIPI D-PHY, characterized in that the number of the IOL modules is four, and the four IOL modules include two first IOL modules for transmitting low-speed data and two second IOL modules for transmitting high-speed data sending circuit.
11. The method of claim 10,
The MIPI D-PHY sending circuit further comprises a first resistor, the first IOL module is connected to the external port through the first resistor, and the resistance value of the first resistor is 330 ohms. D-PHY sending circuit.
11. The method of claim 10,
The MIPI D-PHY sending circuit further comprises a second resistor, the second IOL module is connected to the external port through the second resistor, and the resistance value of the second resistor is 50 ohms. D-PHY sending circuit.
10. The method of claim 9,
MIPI D-PHY sending circuit, characterized in that the level standard of the high-speed data is LVDS.
14. The method of claim 13,
The high-speed data is a MIPI D-PHY sending circuit, characterized in that the current of 2 ~ 4mA.
10. The method of claim 9,
MIPI D-PHY sending circuit, characterized in that the level standard of the low-speed data is LVCMOS12.
16. The method of claim 15,
MIPI D-PHY sending circuit, characterized in that the high-speed data is a current of 2 to 12 mA.
5. The method of claim 4,
wherein the clock link clock channel is a unidirectional channel and the data link clock channel is a unidirectional channel or a bidirectional channel.
17. The method according to any one of claims 1 to 3 and 7 to 16,
and the MIPI D-PHY sending circuit is for generating a clock in a clock path and a clock in a data path, wherein the clock in the clock path and the clock in the data path are out of phase by a preset phase. Circuit.
Device characterized in that it comprises a MIPI D-PHY sending circuit according to any one of claims 1 to 3 and 7 to 16.
20. The method of claim 19,
The device comprises a smart phone, a tablet PC, a notebook computer, a PDA, and an in-vehicle computer.

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