KR101541182B1 - MIPI D-PHY circuit for Low-power mode - Google Patents

Abstract

The present invention relates to a D-PHY circuit for a MIPI operating in a low-power (LP) mode, and one embodiment of the present invention includes a low power transmitter for adjusting a rate of change of a full swing output voltage in a maximum current amount range, A D-PHY circuit for a MIPI operating in a low power mode comprising a low power receiver receiving a swing output voltage and generating a predetermined full swing logic output based on a first reference voltage and a second reference voltage, have. The D-PHY circuit for MIPI operating in the low power mode according to an embodiment of the present invention can handle asynchronous instructions with a maximum 10 Mbps speed and 1.2 V voltage swing among the MIPI D-PHY analog block for high performance low power interface .

Description

The D-PHY circuit for MIPI which operates in a low-power mode (MIPI D-PHY circuit for low-power mode)

The present invention relates to a D-PHY circuit for MIPI operating in a low-power (LP) mode.

MIPI is emerging as a new standard in the mobile industry. High-speed interface and power-saving function. Recently, LG's Nova display, which applies to LG Optimus Black, is also known to have adopted the MIPI interface. MIPI is a kind of LCD interface that attracts attention from mobile devices with its high-speed interface and power saving function, and the famous Aptina display of iPhone 4 is also designed to support MIPI interface.

LCD interface types include RGB interface, CPU interface (I80, M68), SPI interface, MDDI interface, and MIPI interface. MIPI stands for Mobile Industry Processor Interface. Mobile devices are largely composed of hardware and software. From a hardware point of view, there are various maker's processors or system on a chip (SOC) at the center of the device, which is connected to the camera, display, memory and so on.

This process is followed by an application program called software. MIPI is a new standard for hardware and software between processors and peripherals. That is, it means a new standard of serial interface between camera, display (digital area) and RF-IC (wireless area) based on BB-IC in the terminal. The MIPI Alliance, which establishes these new standards, is open to all companies within the relevant mobile industry, including:

The MIPI Alliance is currently active in more than 100 related companies and organizes its members in a hierarchy similar to other industry standards associations. The organization is divided into four areas: Adopters can develop MIPI-related products using the MIPI specification, and all companies are eligible for membership at this level. Contributors can participate in a working group to define and create MIPI specifications together, and have full authority as an adapter. There are currently several working groups, which are created and disappear as needed. The number of promoters is limited (four). Shall be elected by a vote of the Committee and shall operate for a period of two years. Founders have a standing position.

The structure of MIPI is divided into Physical Layers and Protocol Layers. MIPI D-Phy, DigRF v3 and MIPI M-Phy. DigRF v3, which started with the DigRF consortium, was incorporated into the MIPI Alliance Working Group in April 2007. This working group aims at establishing specifications between RF-IC and BB-IC.

Korea Patent Publication: No. 10-2012-0049547

A problem to be solved by one embodiment of the present invention is to provide a MIPI D-PHY analog block for a high-performance low-power interface and a DIP for a MIPI that operates in a low power mode capable of processing asynchronous commands having a maximum speed of 10Mbps and a voltage swing of 1.2V -PHY < / RTI > circuit.

Another object of the present invention is to provide a D-PHY circuit for MIPI that can be used in a single output LP mode operation.

One embodiment according to the present invention is directed to a power management system including a low power transmitter that adjusts a rate of change of a full swing output voltage in a maximum current amount range and a full swing output voltage generator that receives the full swing output voltage and generates a predetermined full swing output voltage based on a first reference voltage and a second reference voltage PHY circuit for MIPI operating in a low power mode including a low power receiver for generating a logic output.

In one embodiment, the low power transmitter includes a first inverter including a first PMOS transistor and a first NMOS transistor connected in series to a drain of the first NMOS transistor, a second PMOS transistor having a drain connected to the drain of the first NMOS transistor, And a third inverter including a second inverter and a third PMOS transistor including a second NMOS transistor connected in series and a third NMOS transistor serially connected to a drain of the third NMOS transistor.

In another embodiment, the D-PHY circuit for MIPI operating in the low power mode includes a fourth PMOS transistor having a drain connected to the gate of the first PMOS transistor, a fourth PMOS transistor having a drain connected to the gate of the second PMOS transistor, A fifth PMOS transistor having a drain connected to the gate of the third PMOS transistor, a sixth PMOS transistor having a drain connected to the gate of the third PMOS transistor, a first inverter accelerator connected to a drain of the sixth PMOS transistor, And a second inverter accelerator connected to the drain of the first inverter and having the input voltage connected to the gate.

In another embodiment, the D-PHY circuit for MIPI operating in the low power mode includes a fourth NMOS transistor having a drain connected to a gate of the first NMOS transistor, and a drain connected to a gate of the second NMOS transistor A fifth NMOS transistor, a sixth NMOS transistor having a drain connected to the gate of the third NMOS transistor, and a transmission gate for adjusting the switching order of the first inverter, the second inverter, and the third inverter And the full swing output voltage may be 1.2V.

In another embodiment, the low power receiver receives the full swing output voltage by a plurality of transistors, and performs hysteresis based on the first reference voltage and the second reference voltage to generate the full swing logic output Generating Schmitt trigger circuit.

In yet another embodiment, the D-PHY circuit for MIPI operating in the low power mode further comprises a low power contention detector coupled between the low power transmitter and the low power receiver, wherein the low power contention The detector can be activated only when the low power transmitter and the low power receiver are in the bidirectional transmission mode.

In another embodiment, the maximum transmission rate of the D-PHY circuit for MIPI operating in the low power mode may be 10 Mbps, and a temporary example of the present invention includes a D-PHY circuit for MIPI operating in a low power mode A portable terminal, a mobile terminal, a telematics terminal, a notebook computer or the like, which includes a D-PHY circuit for MIPI that can operate in a low power mode, A PDA, a Wibro Terminal, an IPTV (Internet Protocol Television) terminal, an AVN (Audio Video Navigation) terminal, a PMP (Portable Multimedia Player), and a navigation terminal And a navigation terminal (vehicle navigation device) (Navigation Terminal) can be provided.

The D-PHY circuit for MIPI operating in the low power mode according to an embodiment of the present invention can handle asynchronous instructions with a maximum 10 Mbps speed and 1.2 V voltage swing among the MIPI D-PHY analog block for high performance low power interface .

The D-PHY circuit for MIPI according to an embodiment of the present invention may be used for single output LP mode operation.

1 is a block diagram illustrating an internal configuration of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.
2 is a circuit diagram showing a low power transmitter (LP-TX) of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.
3 is a circuit diagram showing a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.
4 is a graph showing a simulation result of LP-TX according to the load capacitor according to an embodiment of the present invention.
5 is a circuit diagram showing a low power receiver (LP-RX) of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.
6 is a graph showing simulation results of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.
FIG. 7 and FIG. 8 show the results of operation characteristics of the D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.
9 is a graph showing simulation results of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.

Specific structural and functional descriptions of the embodiments of the present invention disclosed herein are for illustrative purposes only and are not to be construed as limitations of the scope of the present invention. And should not be construed as limited to the embodiments set forth herein or in the application.

The embodiments according to the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It is to be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first and / or second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises ", or" having ", or the like, specify that there is a stated feature, number, step, operation, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The Mobile Industry Processor Interface (MIPI) is a standard for optimizing the interface between processors and peripherals in rapidly growing mobile IT devices. The PHY level configuration commonly used in various application areas of the MIPI is composed of a digital part and an analog part as shown in FIG. One embodiment of the present invention is an LP (Low Power) mode operation used for a single output LP (Low Power) mode operation used for processing asynchronous commands having a maximum 10Mbps speed and a 1.2V voltage swing among MIPI D-PHY analog blocks for a high performance low power interface -TX, LP-RX, and LP-CD.

1 is a block diagram illustrating an internal configuration of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.

Referring to FIG. 1, a D-PHY circuit for MIPI operating in a low power mode according to an embodiment of the present invention may include a low power transmitter (LP-TX) and a low power receiver (LP-RX).

A low-power transmitter (LP-TX) can regulate the rate of change of the full-swing output voltage over the maximum current range.

The low power receiver (LP-RX) may receive the full swing output voltage and generate a predetermined full swing logic output based on the first reference voltage and the second reference voltage.

2 is a circuit diagram showing a low power transmitter (LP-TX) of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.

Referring to FIG. 2, a low power transmitter LP-TX according to an embodiment of the present invention may include a first inverter D1, a second inverter D2, and a third inverter D3.

The first inverter D1 may include a first PMOS transistor MPD1 and a first NMOS transistor MND1. The drain of the first PMOS transistor MPD1 may be connected to the drain of the first NMOS transistor MND1. The gate of the first PMOS transistor MPD1 may be connected to the drain of the fourth PMOS transistor MP2 and the gate of the first NMOS transistor MND1 may be connected to the drain of the fourth NMOS transistor MN2.

The second inverter D2 may include a second PMOS transistor MPD2 and a second NMOS transistor MND2. The drain of the second PMOS transistor MPD2 may be connected to the drain of the second NMOS transistor MND2. The gate of the second PMOS transistor MPD2 may be connected to the drain of the fifth PMOS transistor MP3 and the gate of the second NMOS transistor MND2 may be connected to the drain of the fifth NMOS transistor MN3.

The third inverter D3 may include a third PMOS transistor MPD3 and a third NMOS transistor MND3. The drain of the third PMOS transistor MPD3 may be connected to the drain of the third NMOS transistor MND2. The gate of the third PMOS transistor MPD3 may be connected to the drain of the sixth PMOS transistor MP4 and the gate of the third NMOS transistor MND3 may be connected to the drain of the sixth NMOS transistor MN4.

The pair of MND1 and MPD1 can constitute the first inverter D1. And the pair of MND2 and MPD2 can constitute the second inverter D2. The pair of MND3 and MPD3 can constitute a second inverter D3. This is a large inverter for driving divided into three parts for slew-rate regulation and noise reduction. MP2, MP3, MP4 and MN2, MN3 and MN4 are used to quickly turn off the PMOS and NMOS of the inverters, respectively. In the middle, MN1 and MP1 are used to turn on the inverters quickly, and transmission gates (TGs) are used as resistors to make delays to turn on in order of D3, D2, D1.

In another embodiment, a low power transmitter (LP-TX) according to an embodiment of the present invention includes a fourth PMOS transistor whose drain is connected to the gate of the first PMOS transistor, a fourth PMOS transistor whose drain is connected to the gate of the second PMOS transistor A fifth PMOS transistor having a drain connected to the gate of the third PMOS transistor, a sixth PMOS transistor having a drain connected to the gate of the third PMOS transistor, a first inverter accelerator connected to the drain of the sixth PMOS transistor, And a second inverter accelerator to which the input voltage is connected to the gate.

D3, D2, and D1 are used to increase the current drive capability in the order of the width of each inverter, and in the order of D3, D2, and D1 in reverse order. Then, when driving a small load capacitor, even if only D3 is turned on, sufficient current is supplied, the output is changed to a desired state, and D2 and D1 have already determined the output state and no current flows. When driving a large load capacitor, even if D3 is turned on, the output does not change sufficiently due to insufficient current, and D2 and D1 are turned on in order to increase the current driving the load to adjust the slew-rate of the output. If the slope of the output of the LP-TX is not greater than the given value, the occurrence of noise caused by the ground bounce can be reduced.

In another embodiment, a low power transmitter (LP-TX) according to an embodiment of the present invention includes a fourth NMOS transistor having a drain connected to the gate of the first NMOS transistor, a second NMOS transistor having a drain connected to the gate of the second NMOS transistor A fifth NMOS transistor, a sixth NMOS transistor having a drain connected to the gate of the third NMOS transistor, and a transmission gate for adjusting the switching order of the first inverter, the second inverter, and the third inverter. In addition, the full swing output voltage may be 1.2V.

3 is a circuit diagram showing a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.

Referring to FIG. 3, in a D-PHY circuit for a MIPI operating in a low-power mode according to an embodiment of the present invention, an A block represents a capacitor and a resistor for delaying a time when a transistor is turned on. The B block is for quickly turning off INV0, INV1 and INV2. The C block is for rapidly turning on INV0, INV1 and INV2. INV0, INV1 and INV2 are the interrupts for driving output loading. INV0 operates and INV2 operates after the next INV1.

When driving a small load capacitor, even if only INV0 is operated, sufficient current is supplied and the output is changed to the desired state, and the output state of INV1 and INV2 is already determined and no current flows. When driving a large load capacitor, even if INV0 is driven, INV1 and INV2 are driven in order and the slew-rate of the output is increased by increasing the current driving the load in order that the output does not change sufficiently.

4 is a graph showing a simulation result of LP-TX according to the load capacitor according to an embodiment of the present invention.

Referring to FIG. 4, when the input Vi falls, the C _LOADs are 0, 5, 20, and 70 pF, respectively. At 0, 5, 20pF, the slope of the output transition must be gentler than the reference dotted line and longer than the reference transition time. However, at 70 pF, the slope at which the output transits must change more steeply than the reference dotted line. That is, the transition time should be shorter than the reference transition time (25ns). 0.18V and 1.02V are the reference voltages that represent 15% and 85% of the LP-TX output swing, respectively.

5 is a circuit diagram showing a low power receiver (LP-RX) of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.

Referring to FIG. 5, a low power receiver according to an embodiment of the present invention can receive a full swing output voltage by a plurality of transistors. It may also be a Schmitt trigger circuit that performs hysteresis based on the first reference voltage and the second reference voltage to produce a full swing logic output.

The LP-RX is a 1.2V full-swing logic output that accepts a 1.2V full-swing output of up to 10Mbps LP-TX as input, has two reference voltages, and converts that voltage to V _IL , V _IH Hysteresis must be performed. The low-power contention detector (LP-CD) is a block that is activated only when it is in bidirectional transmission mode. It has the same structure as the LP-RX and has a different reference voltage. Therefore, the Schmitttrigger of FIG. 4 was used as an output buffer having hysteresis characteristics for LP-RX and LP-CD in MIPI D-PHY. The minimum and maximum values of the reference voltage are specified for the LP-RX and LP-CD in the MIPI D-PHY as shown in Fig. The widths of MN1, MN3, MP5, and MP6 were adjusted based on the following equations (1) and (2) to minimize the current consumption by _{matching the} reference voltages V _IH and V _IL .

6 is a graph showing simulation results of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.

Referring to FIG. 6, a hysteresis operation satisfying a reference voltage is obtained by implementing a minimum W / L size. However, a spike and an interference-related characteristic have a noise spike of 100 MHz or more Has a problem affecting the output. To solve the noise-sensitive Schmitt trigger problem, we solve the spike problem by slowing down the switching speed by increasing the L size while maintaining the W / L ratio of each MOSFET.

The maximum transmission rate of the D-PHY circuit for MIPI operating in the low power mode according to an embodiment of the present invention may be 10 Mbps. One embodiment of the present invention may provide a driver IC including a D-PHY circuit for MIPI operating in a low power mode and may be a portable terminal, a mobile terminal, a telematics terminal, A notebook computer, a digital broadcasting terminal, a personal digital assistant (PDA), a wibro terminal, an IPTV terminal, an AVN (Audio Video Navigation) terminal, a PMP Player and a navigation terminal (a navigation terminal) can be provided.

FIG. 7 and FIG. 8 show the results of operation characteristics of the D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.

Referring to FIGS. 7 and 8, the D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention increases the rise time and the fall time when the capacity of the capacitor increases Can be confirmed.

9 is a graph showing simulation results of a D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention.

Referring to FIG. 9, the D-PHY circuit for MIPI operating in a low-power mode according to an embodiment of the present invention increases the rise time and the fall time when the capacity of the capacitor increases .

The embodiments of the present invention have been described above. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

LP-TX: Low Power Transmitter
LP-RX: Low power receiver
LP-CD: Low power contention detector

Claims (10)

A low power transmitter that adjusts the rate of change of the full swing output voltage in the maximum current range; And
A low power receiver receiving the full swing output voltage and generating a predetermined full swing logic output based on a first reference voltage and a second reference voltage;
A D-PHY circuit for MIPI operating in a low power mode,
The low power transmitter includes:
A first inverter including a first PMOS transistor and a first NMOS transistor serially connected to a drain of the first NMOS transistor;
A second inverter including a second PMOS transistor and a second NMOS transistor serially connected to a drain of the second NMOS transistor;
A third inverter including a third PMOS transistor and a third NMOS transistor serially connected to a drain of the third NMOS transistor;
A fourth PMOS transistor having a drain connected to a gate of the first PMOS transistor;
A fifth PMOS transistor having a drain connected to a gate of the second PMOS transistor;
A sixth PMOS transistor having a drain connected to a gate of the third PMOS transistor;
A first inverter accelerator coupled to the drain of the sixth PMOS transistor and having an input voltage connected to the gate; And
A second inverter accelerator coupled to a drain of the sixth NMOS transistor, the input voltage being coupled to a gate;
, ≪ / RTI &
When the capacity of the load capacitor connected to the D-PHY circuit for MIPI operating in the low power mode is increased, the rise time to the maximum output and the fall time to return to the lowest output are increased compared to when the capacity of the load capacitor is small D-PHY circuit for MIPI.

delete delete delete The method according to claim 1,
Wherein the full swing output voltage is 1.2 V. The D-PHY circuit for MIPI operating in a low power mode.
The method according to claim 1,
The low power receiver is a Schmitt trigger circuit that receives the full swing output voltage by a plurality of transistors and performs hysteresis based on the first reference voltage and the second reference voltage to generate the full swing logic output D-PHY circuit for MIPI operating in low power mode.
The method according to claim 1,
The D-PHY circuit for MIPI operating in the low power mode further includes a low power content detector coupled between the low power transmitter and the low power receiver,
Wherein the low power contention detector is activated only when the low power transmitter and the low power receiver are in a bidirectional transmission mode.
The method according to claim 1,
And the maximum transmission rate of the D-PHY circuit for MIPI operating in the low power mode is 10 Mbps.
A driver IC comprising a D-PHY circuit for MIPI operating in a low power mode.
A portable terminal, a mobile terminal, a telematics terminal, a notebook computer, a digital broadcasting terminal, and a portable terminal including a D-PHY circuit for MIPI operating in a low power mode. (PDA), a Wibro Terminal, an IPTV (Internet Protocol Television) terminal, an AVN (Audio Video Navigation) terminal, a PMP (Portable Multimedia Player) and a navigation terminal Terminal).

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