CN109819191B - MIPI C-PHY signal generator and signal generating method thereof - Google Patents
MIPI C-PHY signal generator and signal generating method thereof Download PDFInfo
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- CN109819191B CN109819191B CN201910043126.XA CN201910043126A CN109819191B CN 109819191 B CN109819191 B CN 109819191B CN 201910043126 A CN201910043126 A CN 201910043126A CN 109819191 B CN109819191 B CN 109819191B
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Abstract
The invention belongs to the technical field of display, and discloses an MIPI C-PHY signal generator and a signal generating method thereof, wherein the signal generator comprises an FPGA chip and an MIPI C-PHY bridge chip, and the FPGA chip comprises an embedded processor Nios II, a network data controller, a DDR read-write controller, an image data to RGB (red, green and blue) conversion module and an RGB to MCU (micro control unit) data processing module; the FPGA-based image acquisition device is controlled by an embedded processor Nios II of an FPGA chip, image data are converted into RGB interface signals or MCU interface signals and then output, and the RGB interface signals or the MCU interface signals are converted into MIPI C-PHY interface signals through an MIPI C-PHY bridge chip. The invention can support all display modes of the MIPI C-PHY interface display module.
Description
Technical Field
The invention relates to the technical field of display, in particular to an MIPI C-PHY signal generator and a signal generating method thereof.
Background
The MIPI D-PHY is widely applied to a part of a processor connected with a display screen and a camera. With the increase of pixels and frame frequency of cameras and display screens, the data transmission speed of the prior MIPI D-PHY cannot meet the current requirement, and the latest MIPI C-PHY standard is proposed nowadays.
Compared with the MIPI D-PHY, the MIPI C-PHY supports higher resolution and refresh frequency, LCD and OLED module manufacturers take the MIPI C-PHY as a next-generation product to promote research and development schedules, and some manufacturers have come out samples, so that the requirements of MIPI C-PHY interface display module detection equipment are accelerated.
Disclosure of Invention
The purpose of the application is to provide an MIPI C-PHY signal generator and a signal generating method thereof.
An embodiment of the present application provides an MIPI C-PHY signal generator, including: an FPGA chip and an MIPI C-PHY bridging chip;
the FPGA chip comprises an embedded processor Nios II, a network data controller, a DDR read-write controller, an image data to RGB (red, green and blue) conversion module and an RGB to MCU (micro control unit) data processing module;
the embedded processor Nios II is respectively connected with the network data controller, the image data to RGB module and the RGB to MCU data processing module; the network data controller, the DDR read-write controller, the image data to RGB module and the RGB to MCU data processing module are connected in sequence; and the RGB-to-MCU data processing module is connected with the MIPI C-PHY bridge chip.
Preferably, the FPGA chip further includes: an SPI module; the embedded processor Nios II is connected with the SPI module, and the SPI module is connected with the MIPI C-PHY bridge chip.
Preferably, the image data to RGB module includes: the time sequence generating module and the image data converting module; the time sequence generation module is connected with the image data conversion module.
Preferably, the MIPI C-PHY signal generator further includes a memory DDR 3; the memory DDR3 is connected with a DDR read-write controller in the FPGA chip.
Preferably, the MIPI C-PHY signal generator further includes a PC terminal; and the PC end is connected with a network data controller in the FPGA chip.
On the other hand, the embodiment of the application provides a signal generating method of an MIPI C-PHY signal generator, which is characterized in that the signal generating method is controlled by an embedded processor Nios II of an FPGA chip, and image data are converted into RGB interface signals or MCU interface signals and then output; and converting the RGB interface signal or the MCU interface signal from the FPGA chip into an MIPI C-PHY interface signal through an MIPI C-PHY bridge chip.
Preferably, the network data controller of the FPGA chip is communicated with the PC terminal; controlling a DDR read-write controller to store image data sent from the PC end into a memory DDR3 through the embedded processor Nios II of the FPGA chip;
when the screen is clicked, a power-on command is sent to the embedded processor Nios II through the PC end, and the embedded processor Nios II controls the DDR read-write controller to read the image data; the Nios II of the embedded processor configures an image data-to-RGB module, and converts the image data into RGB interface signals; the embedded processor Nios II configures a data processing module for converting RGB to MCU, converts the RGB interface signals into MCU interface signals in a Command mode, and forwards the RGB interface signals in a Video mode; the embedded processor Nios II outputs the RGB interface signal or the MCU interface signal to the MIPI C-PHY bridge chip; and the MIPI C-PHY bridge chip converts the RGB interface signals or the MCU interface signals into MIPI C-PHY interface signals.
Preferably, in the Video mode, the Nios II embedded processor controls the SPI module to output an SPI signal to the MIPI C-PHY bridge chip.
Preferably, the image data to RGB conversion module includes a timing generation module and an image data conversion module; the time sequence generation module generates an RGB interface time sequence according to the time sequence parameter issued by the Nios II of the embedded processor; the image data conversion module decomposes the image data read from the DDR read-write controller into RGB image data according to the time sequence generated by the time sequence generation module, and outputs RGB interface signals.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
in the embodiment of the application, the MIPI C-PHY signal generator adopts an embedded processor Nios II of an FPGA chip for control, and adopts an MIPI C-PHY bridge chip for signal conversion. The FPGA chip comprises a network data controller, a DDR read-write controller, an image data to RGB (red green blue) module and an RGB to MCU (micro control unit) data processing module, the image data is finally output to be an RGB interface signal or an MCU interface signal which can be recognized by the MIPI C-PHY bridging chip through the modules in the FPGA chip, and then the MIPI C-PHY bridging chip converts the RGB interface signal or the MCU interface signal into an MIPI C-PHY interface signal for a display module with an MIPI C-PHY interface to display. The invention supports all display modes of the MIPI C-PHY interface display module, can support OTP/MTP/Gamma function, and MIPI C-PHY interface signals output by the MIPI C-PHY bridge chip can support 6Lane at most, 2.85Gbps at most per Lane, and 24bit4096 x 2160@60Hz of image resolution can be supported at most.
Drawings
In order to more clearly illustrate the technical solution in the present embodiment, the drawings needed to be used in the description of the embodiment will be briefly introduced below, and it is obvious that the drawings in the following description are one embodiment of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic diagram of a framework of an MIPI C-PHY signal generator according to an embodiment of the present invention.
Detailed Description
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
The MIPI C-PHY signal generator provided by the invention adopts an embedded processor Nios II of an FPGA chip as control, and an MIPI C-PHY bridge chip as signal conversion. The FPGA chip comprises a network data controller, a DDR read-write controller, an image data to RGB (red green blue) module, an RGB to MCU (micro control unit) data processing module and an SPI (serial peripheral interface) module, and finally outputs RGB interface signals or MCU interface signals which can be recognized by the MIPI C-PHY bridging chip, and the MIPI C-PHY interface signals are converted from the MIPI C-PHY bridging chip and are displayed by a display module with an MIPI C-PHY interface.
A system block diagram of a signal generator for implementing an MIPI C-PHY interface based on an FPGA chip is shown in fig. 1. The PC communicates with a network Data Controller (i.e., Net Data Controller in fig. 1) through an ethernet (Eth) communication interface, and then an embedded processor Nios II of the FPGA chip controls a DDR Read/Write Controller (i.e., DDR Read Write Controller in fig. 1) to store Data such as a picture, a module initialization code, a timing code, and the like sent by the PC in a DDR (i.e., DDR3 in fig. 1).
When the screen is clicked, the PC terminal sends a power-on command to an embedded processor Nios II of the FPGA chip, the embedded processor Nios II controls a DDR read-write controller to read Data such as pictures, module initialization codes, time sequence timing and the like through an internal bus, and configures an image Data to RGB module (namely a Data conversion module in FIG. 1) to finish the conversion of image Data into RGB signals; then configuring an RGB to MCU data processing module (namely RGB to MCU in figure 1), configuring whether to start the RGB to MCU by an embedded processor Nios II according to different mode settings of Video and Command, thus completing the conversion of RGB image interface to MCU interface signal in the Command mode, and forwarding the RGB interface signal in the Video mode; according to different modes, the embedded processor Nios II controls the RGB interface signals or the MCU interface signals to be output to the MIPI C-PHY bridge chip, and the MIPI C-PHY bridge chip converts the RGB interface signals or the MCU interface signals into the MIPI C-PHY interface signals. In addition, due to the requirement of the Video mode, the Nios II embedded processor also needs to control the SPI module to output an SPI signal to the MIPI C-PHY bridge chip.
1. Memory DDR3
The DDR3 is used for storing data such as a module initialization code, timing, pictures and the like required by a module dot screen.
2. DDR Read Write Controller
The DDR read-write controller is a logic-implemented multi-port DMA controller, and can dynamically adjust the burst length of read-write DDR according to the read-write length so as to achieve the maximum DDR bandwidth. Under the control of the Nios II, the DDR read-write controller can directly write the data sent by the PC end through the Ethernet into the DDR, and can also read the data from the DDR and send the data to the Nios II or the image data to RGB module.
3. Embedded processor Nios II
Nios II in the image signal generator is an FPGA embedded processor, and the main functions of the FPGA embedded processor are as follows:
1) communicating with PC terminal
The graphic signal generator communicates with the PC end through communication ports such as Ethernet and the like, so that data such as pictures, initialization codes, timing and the like are downloaded and control commands are received and transmitted.
2) DDR read-write controller
The Nios II can control the DDR read-write controller to write data such as pictures issued by the PC terminal, initialization codes, timing and the like into the DDR read-write controller and then store the data into the DDR.
Nios II can also read the initialization code, timing and other data in DDR through the DDR read-write controller.
3) Data conversion of configuration image Data to RGB module
Image data read out by DDR requires Nios II configuration related parameters to be converted into RGB interface signals, and the parameters include: timing, image movement, RGB replacement data, and the like.
4) RGB to MCU data processing module RGB to MCU
The MCU interface signals include command and image data signals, where the command signals are interactive commands originating from the Nios II, Nios II processing and bridge chips. The method comprises the functions of initial code issuing, Pgamma adjustment, RGB and MCU signal output selection and the like.
5) Configuration SPI module SPI Controller
The Video mode requires the SPI to process and bridge the interactive commands of the chip, and the SPI module needs to be configured before reading and writing the module of the SPI interface, including the operating frequency, operating mode, bit number, etc. of the SPI bus. Nios II realizes the configuration to the SPI module through the Avalon bus according to these parameters of module, output SPI signal.
6) Dot screen cutting chart
After the initialization of the module is completed, Nios II can control the DDR read-write controller to read the graph from the DDR according to the size and the address of each graph, and realize the point graph and the cut graph of the module.
4. Data conversion module for converting image Data into RGB (red, green and blue) Data
The image data-to-RGB module mainly converts DDR read data into RGB interface data required by the MIPI C-PHY bridge chip. The image data to RGB conversion module comprises a time sequence generation module and an image data conversion module.
1) Time sequence generation module
And the time sequence generation module generates an RGB interface time sequence according to the time sequence Timing parameter issued by Nios II.
2) Image data conversion module
The image data conversion decomposes the image data read out by the DDR into RGB image data according to the time sequence generated by the time sequence generation module, and outputs RGB interface signals.
5. RGB-To-MCU data processing module RGB To MCU
The RGB-to-MCU data processing module mainly converts RGB interface signals into MCU interface signals required in a COMMAND mode, and converts Nios II control information into MCU interface signals. The RGB-to-MCU data processing module converts RGB interface signals into MCU interface signals in a Command mode and forwards the RGB interface signals in a video mode.
The MIPI C-PHY signal generator and the signal generating method thereof provided by the embodiment of the invention at least have the following technical effects:
1. the RGB-MCU conversion data processing module can output RGB interface signals or MCU interface signals according to requirements, supports two display modes required by the MIPI C-PHY interface display module, and supports all four display modes of the MIPI C-PHY interface display module by combining a compression mode and a non-compression mode: compression and non-compression modes for Video, compression and non-compression modes for Command.
2. Nios II and PC communication interaction and flow control can support OTP/MTP/Gamma function.
3. The FPGA processes image data at a high speed, MIPI C-PHY interface signals output by the bridge chip can support 6Lane at the maximum, 2.85Gbps can be supported at the maximum by each Lane, and 24bit4096 x 2160@60Hz of image resolution can be supported at the maximum.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (9)
1. An MIPI C-PHY signal generation method is characterized in that an embedded processor Nios II of an FPGA chip is used for controlling, image data are converted into RGB interface signals or MCU interface signals and then output; converting the RGB interface signal or the MCU interface signal from the FPGA chip into an MIPI C-PHY interface signal through an MIPI C-PHY bridge chip;
the specific implementation manner of converting the image data into the RGB interface signal or the MCU interface signal and then outputting the RGB interface signal or the MCU interface signal is as follows: the Nios II of the embedded processor configures an image data-to-RGB module, and converts the image data into RGB interface signals; the embedded processor Nios II configures a data processing module for converting RGB to MCU, converts the RGB interface signals into MCU interface signals in a Command mode, and forwards the RGB interface signals in a Video mode.
2. The MIPI C-PHY signal generation method of claim 1, communicating with a PC side through a network data controller of the FPGA chip; controlling a DDR read-write controller to store image data sent from the PC end into a memory DDR3 through the embedded processor Nios II of the FPGA chip;
when the screen is clicked, a power-on command is sent to the embedded processor Nios II through the PC end, and the embedded processor Nios II controls the DDR read-write controller to read the image data; the embedded processor Nios II outputs the RGB interface signal or the MCU interface signal to the MIPI C-PHY bridge chip; and the MIPI C-PHY bridge chip converts the RGB interface signals or the MCU interface signals into MIPI C-PHY interface signals.
3. The MIPI C-PHY signal generation method of claim 2, wherein in the Video mode, the embedded processor Nios II controls the SPI module to output an SPI signal to the MIPI C-PHY bridge chip.
4. The MIPI C-PHY signal generation method according to claim 2, wherein the image data to RGB module includes a timing generation module and an image data conversion module; the time sequence generation module generates an RGB interface time sequence according to the time sequence parameter issued by the Nios II of the embedded processor; the image data conversion module decomposes the image data read from the DDR read-write controller into RGB image data according to the time sequence generated by the time sequence generation module, and outputs RGB interface signals.
5. A signal generator for implementing the MIPI C-PHY signal generation method of claim 1, comprising: an FPGA chip and an MIPI C-PHY bridging chip;
the FPGA chip comprises an embedded processor Nios II, a network data controller, a DDR read-write controller, an image data to RGB (red, green and blue) conversion module and an RGB to MCU (micro control unit) data processing module;
the embedded processor Nios II is respectively connected with the network data controller, the image data to RGB module and the RGB to MCU data processing module; the network data controller, the DDR read-write controller, the image data to RGB module and the RGB to MCU data processing module are connected in sequence; and the RGB-to-MCU data processing module is connected with the MIPI C-PHY bridge chip.
6. The signal generator of claim 5, wherein the FPGA chip further comprises: an SPI module; the embedded processor Nios II is connected with the SPI module, and the SPI module is connected with the MIPI C-PHY bridge chip.
7. The signal generator of claim 5, wherein the image data to RGB module comprises: the time sequence generating module and the image data converting module; the time sequence generation module is connected with the image data conversion module.
8. The signal generator of claim 5, further comprising a memory DDR 3; the memory DDR3 is connected with a DDR read-write controller in the FPGA chip.
9. The signal generator of claim 5, further comprising a PC terminal; and the PC end is connected with a network data controller in the FPGA chip.
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