CN212135498U

CN212135498U - Image processing apparatus for digital cinema projector

Info

Publication number: CN212135498U
Application number: CN202020767216.1U
Authority: CN
Inventors: 郭克威; 武美艳; 林晓飞
Original assignee: China Film Equipment Co ltd; Cfg Barco Beijing Electronics Co ltd
Current assignee: China Film Equipment Co ltd; Cfg Barco Beijing Electronics Co ltd
Priority date: 2020-05-11
Filing date: 2020-05-11
Publication date: 2020-12-11
Anticipated expiration: 2030-05-11

Abstract

The utility model provides an image processing device for a digital film projector, the digital film projector comprises a film playing server, the image processing device comprises an integrated film processing board, an FPGA controller and a signal format control board; the integrated film processing board is electrically connected with the film playing server and is used for transmitting the digital images output by the film playing server to the FGPA controller; the FPGA controller is configured with an image processing unit and a frame rate synchronization unit, the image processing unit is configured to perform image segmentation, contrast enhancement and graying on the digital image, and the processed digital image is transmitted to the signal format control board; the frame rate synchronization unit is configured to generate a synchronization signal corresponding to the digital image; the signal format control board is electrically connected with the FPGA controller and is used for controlling the transmission format of the digital image after the contrast enhancement processing. The utility model discloses can be used to improve film digital image's contrast and resolution ratio.

Description

Image processing apparatus for digital cinema projector

Technical Field

The utility model relates to an image processing technology field, concretely relates to an image processing device for digital film projector.

Background

The current digital film projector only supports conventional film projection, and has no corresponding software and hardware interfaces on the support of high-end image technologies such as resolution extension, High Dynamic Range (HDR) and the like, so that the resolution and the contrast are difficult to be greatly improved. Therefore, the FPGA-based architecture image processing board is added to the architecture of the existing digital cinema projector, and hardware support is provided for high-end image technologies such as resolution extension, High Dynamic Range (HDR) and the like.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an image processing apparatus for digital film projector can extend the processing function of digital film projector to the digital image, for high-end image technique provides hardware support, specially adapted improves operations such as contrast, resolution ratio of digital film.

In order to achieve the above object, the present invention provides an image processing apparatus for a digital cinema projector, the digital cinema projector includes a cinema playing server, an integrated cinema processing board, the image processing apparatus includes an FPGA controller and a signal format control board;

the integrated film processing board is electrically connected with the film playing server and is used for transmitting the digital images output by the film playing server to the FGPA controller;

the FPGA controller is configured with an image processing unit and a frame rate synchronization unit, the image processing unit is configured to perform image segmentation, contrast enhancement, graying, image deformation and image fusion on the digital image, and transmit the processed digital image to the signal format control board; the frame rate synchronization unit is configured to generate a synchronization signal corresponding to the digital image;

the signal format control board is electrically connected with the FPGA controller and is used for controlling the transmission format of the processed digital image.

Preferably, the image processing device further comprises a crystal oscillator circuit electrically connected with the FPGA controller, the FPGA controller is further configured with a clock management unit, the crystal oscillator circuit sends a clock signal to the clock management unit, and the clock management unit performs frequency division processing on the clock signal and sends the clock signal after the frequency division processing to the image processing unit and the frame rate synchronization unit.

Preferably, the digital image comprises red channel data, green channel data, and blue channel data;

and the FPGA controller is respectively provided with an input interface and an output interface corresponding to the red channel data, the green channel data and the blue channel data.

Preferably, the FPGA controller is provided with a plurality of parallel image output interfaces.

Preferably, the image output interface includes an HDMI signal interface.

Preferably, the FPGA controller is further configured with a plurality of signal synchronization interfaces, which are respectively electrically connected to the frame rate synchronization unit.

Preferably, the digital cinema projector comprises a frequency expander electrically connected to the signal synchronization interface.

Preferably, the digital cinema projector comprises a projection system electrically connected to the signal synchronization interface.

Preferably, the FPGA controller is further provided with a power supply port electrically connected with an external power supply of 5V, 12V or 24V.

The utility model has the advantages that:

the utility model provides an image processing device for a digital film projector, which utilizes an integrated film processing board to transmit digital images output by a film playing server to an FGPA controller; the FPGA controller is used for carrying out corresponding digital processing on the digital image, hardware support is provided for a high-end image technology, and the method is particularly suitable for improving the operations of the contrast ratio, the resolution ratio and the like of the digital film.

Drawings

Fig. 1 is a schematic diagram of the main structure of an image processing apparatus for a digital cinema projector according to the present invention.

Fig. 2 is a schematic diagram of the main structure of the image processing apparatus for a digital cinema projector according to the present invention.

Detailed Description

Referring to fig. 1 and 2, fig. 1 and 2 exemplarily show a main structure of an image processing apparatus for a digital cinema projector, and as shown in fig. 1, a digital cinema projector 10 includes a cinema playback server 11, an integrated cinema processor 12(integrated cinemasa processor), a projection system 13, and a resolution extender 14. The image processing apparatus 20 includes an FPGA controller 21, a signal format control board 22 (formatter), and a crystal oscillator circuit 23.

The integrated movie processing board 12 is electrically connected to the movie playing server 11, and is configured to transmit the digital images output by the movie playing server 11 to the FGPA controller 21. The digital image comprises red channel data R, green channel data G and blue channel data B; the FPGA controller 21 is configured with an input interface and an output interface corresponding to the red channel data R, the green channel data G, and the blue channel B data, respectively. That is, the FPGA controller 21 is configured with 3 signal input interfaces 25 corresponding to the red channel data R, the green channel data G, and the blue channel data B of the digital image, respectively. The integrated cinema processing board 12 transmits the red channel data R, the green channel data G, and the blue channel data B corresponding to the digital image to the FPGA controller 21 through different data transmission lines, respectively.

The FPGA controller 21 is configured with an image processing unit 211, a frame rate synchronization unit 212, and a clock management unit 213; the image processing unit 211 is configured to perform image segmentation, contrast enhancement, graying, image deformation and image fusion on the digital image, and transmit the processed digital image to the signal format control board 22; the frame rate synchronization unit 212 is configured to generate a synchronization signal corresponding to the digital image. The synchronization signal generated by the frame rate synchronization unit 212 may be a frame rate synchronization signal corresponding to the pre-processed digital image, or a frame rate synchronization signal corresponding to the post-processed digital image, for example, 24 frames per second for the pre-processed digital image, 96 frames per second for the post-processed digital image, the frequency of the synchronization signal generated by the frame rate synchronization unit 222 may be synchronized with 24 frames per second, or the frequency of the synchronization signal generated by the synchronization unit 222 may be synchronized with 96 frames per second. The crystal oscillator circuit 23 is electrically connected to the FPGA controller 21, the crystal oscillator circuit 23 sends a clock signal to the clock management unit 213, and the clock management unit 213 divides the frequency of the clock signal and sends the divided clock signal to the image processing unit 211 and the frame rate synchronization unit 212. Thus, the clock signal is used to avoid frame loss when the FPGA controller 21 uses high frequency for digital image acquisition.

The signal format control board 22 is electrically connected to the FPGA controller 21, and is configured to control a transmission format of the digital image after the contrast enhancement processing. That is, the FPGA controller 21 is configured with 3 signal output interfaces respectively corresponding to the red channel data R, the green channel data G, and the blue channel data B of the digital image. After the FPGA controller 21 performs contrast enhancement processing on the digital image, the digital image is transmitted to the 3 signal format control boards through the 3 signal output interfaces respectively.

The FPGA controller 21 is further configured with a plurality of parallel image output interfaces, the image output interface may be an HDMI interface 24, which may be connected to the display device 30, and the image output by the image data interface may be a digital image directly output by the image processing unit, or a grayscale image corresponding to the digital image, and the grayscale image has the same frame rate and resolution as the digital image directly output by the image processing unit. For example, the image processing unit outputs digital images of 2k96 frames, which are converted from digital images of 4k24 frames, and the image output interface outputs grayscale images of 2k96 frames.

The FPGA controller 21 is further configured with a plurality of signal synchronization interfaces 25, each electrically connected to the frame rate synchronization unit 212. The signal synchronization interface 25 is used for outputting the synchronization signal generated by the frame rate synchronization unit 212, and the signal synchronization interface 25 can send the synchronization signal to the projection system 13, the frequency expander 14, or other image processing device for function expansion. In this embodiment, there are 3 signal synchronization interfaces 25, one electrically connected to the frequency expander 14, one electrically connected to the projection system 13, and one for standby.

Furthermore, the FPGA controller 21 is further provided with a power supply port 26, which can be electrically connected to an external power supply 40 of 5V, 12V or 24V to supply power to the FPGA controller.

To sum up, the image processing board for the digital cinema projector provided by the utility model utilizes the integrated cinema processing board to transmit the digital images output by the cinema playing server to the FGPA controller; the FPGA controller is used for carrying out corresponding digital processing on the digital image, hardware support is provided for a high-end image technology, and the method is particularly suitable for improving the operations of the contrast ratio, the resolution ratio and the like of the digital film. The FPGA controller has the advantages of high operation speed, rich internal resources, low cost and capability of saving the design of external electronic hardware and the use of optical accessories.

The above description is the preferred embodiment of the present invention and the technical principle applied by the preferred embodiment, and for those skilled in the art, without departing from the spirit and scope of the present invention, any obvious changes based on the equivalent transformation, simple replacement, etc. of the technical solution of the present invention all belong to the protection scope of the present invention.

Claims

1. An image processing apparatus for a digital cinema projector, the digital cinema projector comprising a cinema playback server, an integrated cinema processing board, characterized in that the image processing apparatus comprises an FPGA controller and a signal format control board;

the integrated film processing board is electrically connected with the film playing server and is used for transmitting the digital image output by the film playing server to the FPGA controller;

2. The image processing apparatus for a digital cinema projector according to claim 1, further comprising a crystal oscillator circuit electrically connected to the FPGA controller, wherein the FPGA controller is further provided with a clock management unit, the crystal oscillator circuit sends a clock signal to the clock management unit, and the clock management unit performs frequency division processing on the clock signal and sends the frequency-divided clock signal to the image processing unit and the frame rate synchronization unit.

3. The image processing apparatus for a digital cinema projector according to claim 2, wherein the digital image includes red channel data, green channel data, and blue channel data;

4. The image processing apparatus for a digital cinema projector according to claim 3, wherein said FPGA controller is provided with a plurality of image output interfaces connected in parallel.

5. The image processing apparatus for a digital cinema projector according to claim 4, wherein the image output interface includes an HDMI signal interface.

6. The image processing apparatus for a digital cinema projector according to claim 3, wherein said FPGA controller is further configured with a plurality of signal synchronization interfaces electrically connected to said frame rate synchronization unit, respectively.

7. The image processing apparatus for a digital cinema projector according to claim 5, wherein the digital cinema projector comprises a frequency expander electrically connected to the signal synchronization interface.

8. The image processing apparatus as claimed in claim 6, wherein said digital cinema projector comprises a projection system electrically connected to said signal synchronization interface.

9. The image processing device for the digital cinema projector according to any one of claims 1 to 8, characterized in that the FPGA controller is further provided with a power supply port electrically connected with an external power supply of 5V or 12V or 24V.