CN103838533B - The synchronous method of figure signal and sync card in computer cluster splice displaying system - Google Patents
The synchronous method of figure signal and sync card in computer cluster splice displaying system Download PDFInfo
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- CN103838533B CN103838533B CN201210477542.9A CN201210477542A CN103838533B CN 103838533 B CN103838533 B CN 103838533B CN 201210477542 A CN201210477542 A CN 201210477542A CN 103838533 B CN103838533 B CN 103838533B
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Abstract
The present invention provides the synchronous method of figure signal in a kind of computer cluster splice displaying system, including: receive the figure signal of each computer display card output in cluster, and each figure signal is changed into digital graphic data stream；According to synchronizing reception logic, each graphics streams is write corresponding FIFO memory, and according to synchronism output logic, output synchronizing signal based on system and clock signal, graphics streams is read from FIFO memory；After each graphics streams read changes into figure signal, output is to corresponding display device.The invention also discloses a kind of sync card.The present invention utilizes computer cluster jointly to generate the single ultrahigh resolution figure formed by multiple graphic joinings, the frame per second making each figure signal that output arrives display system is the most consistent with synchronizing signal phase place, system entirety output picture is smooth without tear, the system built than the high-end video card synchronized outside support based on single model, has low cost and higher motility.
Description
Technical field
The present invention relates to computer graphical processing field, more particularly, to the synchronous method of figure signal in a kind of computer cluster splice displaying system and sync card.
Background technology
In recent years, in fields such as virtual reality, engineering design, geospatial information visualizations, increasing system is had to use multi-display or multi-projector display ultrahigh resolution, the figure of overlarge area.This kind of system generally requires the highest data-handling capacity and the disposal ability to figure, and computer cluster can provide the high-performance required for this kind of system, the task distribution that ultrahigh resolution figure generates is completed on multiple stage computer.Group system also has extensibility and modular feature, has the highest motility and higher cost performance.In such systems, the key issue that needs solve is, if being generated by ultrahigh resolution figure of task calculates meter according to the multiple stage that screen area is distributed in group system and completes, the multiple graphics output signals resulting from multiple stage computer how are made to accomplish smooth and seamless when constituting single ultrahigh resolution figure, without producing the problems such as picture tear because of the output frame rate of each display card and the difference of synchronizing signal phase place, in addition, some system also requires that the computer graphical signal of output and a television image signal synchronize, this is also that common computer display system is irrealizable.
At present, the computer display card of a few high-end provides the function of outer synchronization, the output timing making display card is consistent with external reference signal, by the most all of computer all uses such display card, the single ultrahigh resolution figure of smooth and seamless can be generated, but this kind of display card is all high-end specialty display card, expensive, the highest to the configuration requirement of computer, add the cost of system, the computer being additionally, since in system can only use special display card, therefore can not make full use of existing general purpose computer resource.
In addition, in applied environment less demanding to graphical quality, the frame per second that some system realizes the new output frame of each computer also by software approach is unanimous on the whole, do not consider phase problem, every frame figure of each computer export cannot guarantee that and belongs to same picture, such system unavoidably there will be the problem of picture tear, and its application is very limited.
Summary of the invention
In view of this, present invention is primarily targeted at synchronous method and the sync card that figure signal in a kind of computer cluster splice displaying system is provided, can solve the problem that present in prior art when multiple stage computer generates single ultrahigh resolution figure simultaneously, it is impossible to the problem making the figure signal precise synchronization of each computer export.
For reaching above-mentioned purpose, the technical scheme is that and be achieved in that:
On the one hand, it is provided that the synchronous method of figure signal in a kind of computer cluster splice displaying system, including: the figure signal of each computer display card output in reception cluster, and each figure signal is changed into digital graphic data stream；Each graphics streams is write corresponding FIFO FIFO memory according to synchronizing reception logic by control module, and according to synchronism output logic, output synchronizing signal based on system and clock signal, is read by graphics streams from FIFO memory；After each graphics streams read changes into figure signal, output is to corresponding display device.
Preferably, described according to synchronizing reception logic by FIFO FIFO memory corresponding for the write of each graphics streams, including: when the graph data amount in FIFO memory reaches default upper threshold value, during the vertical flyback of tablet pattern signal, control module sends to suspend to main frame interrupts application, and forbid to the graph data that FIFO memory write is new, hereafter, graph data amount in FIFO memory gradually decreases, when graph data amount less than preset when restarting threshold value, control module sends to main frame restarts interruption application, and allow to write new graph data to FIFO memory.
Preferably, described according to synchronism output logic, output synchronizing signal based on system and clock signal, graphics streams is read from FIFO memory, including: when the graph data amount in certain FIFO memory in cluster is less than the lower threshold value preset, after the control module corresponding with this FIFO memory reads whole graph datas of present frame, again read pointer is placed in the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback broadcasting figure signal before broadcasting repeating frame, the control module corresponding with this FIFO memory can send repeating frame pulse to other all of control modules, read pointer is also placed in and has been played out at the start address of frame before by other all control modules, in an ensuing frame time, repeat the frame broadcasted before broadcasting.
Preferably, in receiving cluster before the figure signal of each computer display card output, the method also includes: every main frame carries out serial number to the generation of self needs and the graphic frame broadcasted.
Preferably, in described control module after main frame sends time-out interruption application, the method also includes: main frame response suspends interruption and applies for, suspends and broadcasts new graphic frame, records the up-to-date numbering having been played out graphic frame.
Preferably, described after interruption application is restarted in main frame transmission, the method also includes: interruption application is restarted in main frame response, again sends new graphic frame to computer display card, and the numbering of last graphic frame broadcasted before the numbered time-out of new graphic frame adds one.
Preferably, synchronizing signal and clock signal are generated based on reference video input signal or self clock free-running operation by main timing generation module, and synchronizing signal and clock signal are sent to corresponding control module.
Preferably, synchronizing signal and clock signal are exported to arbitrary adjacent thereto from timing generation module by main timing generation module, generate from timing generation module and be sent to corresponding control module with the synchronizing signal of synchronizing signal synchronised received and clock signal, and the synchronizing signal received and clock signal are transmitted to adjacent thereto another from timing generation module.
On the other hand, provide a kind of sync card, including, figure signal receiver module, timing generation module, control module, FIFO FIFO memory and figure signal sending module, wherein, figure signal receiver module, it is connected with computer display card and control module respectively, for receiving the figure signal of computer display card output, and export to control module after figure signal is changed into digital graphic data stream；Timing generation module, is connected with control module, is used for generating synchronizing signal and clock signal to control module；Control module, it is connected with FIFO memory, timing generation module, figure signal receiver module and figure signal sending module, for receiving logic according to synchronization, graphics streams is write FIFO memory, and according to synchronism output logic, output synchronizing signal based on system and clock signal, export to figure signal sending module after being read by graphics streams from FIFO memory；FIFO memory, is connected with control module, for control based on control module, caches graphics streams；Figure signal sending module, is connected with control module and display device respectively, for receiving the graphics streams that control module transmits, and graphics streams changes into output extremely described display device after figure signal.
Preferably, described according to synchronizing reception logic by the described graphics streams described FIFO memory of write, and according to synchronism output logic, output synchronizing signal based on system and clock signal, described graphics streams is read from described FIFO memory and includes: when the graph data amount in FIFO memory reaches default upper threshold value, during the vertical flyback of tablet pattern signal, control module sends to suspend to main frame interrupts application, and forbid to the graph data that FIFO memory write is new, hereafter, graph data amount in FIFO memory gradually decreases, when graph data amount less than preset when restarting threshold value, control module sends to main frame restarts interruption application, and allow to write new graph data to described FIFO memory；When the graph data amount in certain FIFO memory in cluster is less than the lower threshold value preset, after the control module corresponding with this FIFO memory reads whole graph datas of present frame, again read pointer is placed in the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback broadcasting figure signal before broadcasting repeating frame, the control module corresponding with this FIFO memory can send repeating frame pulse to other all of control modules, read pointer is also placed in and has been played out at the start address of frame before by other all control modules, in an ensuing frame time, repeat the frame broadcasted before broadcasting.
Preferably, control module also includes controlling pulse input/output interface, is connected with other all control modules, is used for sending starting impulse or repeating frame pulse to other all control modules.
Preferably, when timing generation module is main timing generation module, synchronizing signal and clock signal generate based on reference video input signal or according to self clock free-running operation, timing generation module is when timing generation module, synchronizing signal and clock signal be based on come autonomous timing generation module self occur synchronizing signal and clock signal and generate.
Preferably, timing generation module also includes: figure synchronizing signal output interface and figure synchronizing signal input interface, wherein:
Figure synchronizing signal output interface, when timing generation module is main timing generation module, export to adjacent from timing generation module for the synchronizing signal that self is occurred and clock signal, when timing generation module is from timing generation module, adjacent from timing generation module for the synchronizing signal of input and clock signal are transmitted to.
Figure synchronizing signal input interface, for receiving the synchronizing signal from adjacent timing generation module and clock signal.
Preferably, sync card also includes computer external interface, is connected with control module, is connected with main frame by computer bus interface, and main frame carries out communication by computer external interface and control module.
The technique effect of the present invention:
1. the present invention utilizes computer cluster jointly to generate the single ultrahigh resolution figure formed by multiple graphic joinings, store after input signal being converted to graph data according to synchronization input logic after the figure signal receiving computer display card output, and according to synchronism output logic, output synchronizing signal based on system and clock signal, graph data is read and is converted to figure signal and transmit to display device, the frame per second making each figure signal that output arrives display system is the most consistent with synchronizing signal phase place, system entirety output picture is smooth without tear, graphical quality is better than the system synchronized based on software frame per second；
2. can use any computer display card due to technical scheme, the system built compared to the high-end video card synchronized outside support based on single model, there is lower cost and higher motility.
3. can realize computer graphical signal and the synchronization of a television image signal due to technical scheme, solve common computer display system in prior art and can not realize the problem Tong Bu with TV signal.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, and the schematic description and description of the present invention is used for explaining the present invention, is not intended that inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 shows the flow chart of the synchronous method of figure signal in the computer cluster splice displaying system of according to embodiments of the present invention；
Fig. 2 shows the concrete process chart of the synchronous method of figure signal in the computer cluster splice displaying system of according to embodiments of the present invention two；
Fig. 3 shows the synchronous method Computer Host Interrupt process chart of figure signal in the computer cluster splice displaying system of according to embodiments of the present invention three；
Fig. 4 shows the structural representation of the sync card of according to embodiments of the present invention four；
Fig. 5 shows the structural representation of the sync card of according to embodiments of the present invention five；
Fig. 6 shows the connection diagram of multiple stage computer sync card in the cluster splice displaying system of according to embodiments of the present invention six；
Fig. 7 shows the structural representation of the sync card of according to embodiments of the present invention seven.
Detailed description of the invention
Below with reference to the accompanying drawings and in conjunction with the embodiments, the present invention is described in detail.
Embodiment one
Fig. 1 shows the flow chart of the synchronous method of figure signal in the computer cluster splice displaying system of according to embodiments of the present invention, as it is shown in figure 1, the method includes:
Step S101, receives the figure signal of each computer display card output in cluster, and each figure signal is changed into digital graphic data stream；
Wherein, the figure signal received can be: the forms such as VGA, DVI, HDMI；Before step S101, the method also includes: every main frame carries out serial number to the generation of self needs and the graphic frame broadcasted, such as, in system, one ultrahigh resolution figure is exported respectively by the images outputting software in N platform computer, images outputting software in every computer is responsible for generating and exporting a part of corresponding whole ultrahigh resolution figure, and, every computer is to self needing the graphic frame generating and broadcasting to carry out serial number, i.e. from the beginning of the 1st frame, to nth frame, N+1 frame ...
Step S102, control module is according to synchronizing reception logic by FIFO FIFO memory corresponding for the write of each graphics streams, and according to synchronism output logic, output synchronizing signal based on system and clock signal, graphics streams is read from FIFO memory；
Concrete, each FIFO memory presets a upper threshold value, restart threshold value and lower threshold value, when the output frame rate of computer display card is faster than the output frame rate of sync card, FIFO memory will become full, when the graph data amount in FIFO memory reaches default upper threshold value, during the vertical flyback of tablet pattern signal, control module sends to suspend to main frame interrupts application, and forbid to the graph data that FIFO memory write is new, hereafter, graph data amount in FIFO memory gradually decreases, when graph data amount less than preset when restarting threshold value, control module sends to main frame restarts interruption application, and allow to write new graph data to FIFO memory.
When the output frame rate of computer display card is slower than the output frame rate of sync card, FIFO memory can become empty, when the graph data amount in certain FIFO memory in cluster is less than the lower threshold value preset, after the control module corresponding with this FIFO memory reads whole graph datas of present frame, again read pointer is placed in the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback broadcasting figure signal before broadcasting repeating frame, the control module corresponding with this FIFO memory can send repeating frame pulse to other all of control modules, read pointer is also placed in and has been played out at the start address of frame before by other all control modules, in an ensuing frame time, repeat the frame broadcasted before broadcasting.That is, when certain sync card is when repeating to broadcast nth frame figure, other all sync cards all repeat to broadcast nth frame, it is ensured that the broadcast frame number of all sync cards is the most identical.
Synchronizing signal and clock signal are generated based on reference video input signal or self clock free-running operation by main timing generation module, and synchronizing signal and clock signal are sent to corresponding control module.
Synchronizing signal and clock signal are exported to arbitrary adjacent thereto from timing generation module by main timing generation module, generate from timing generation module and be sent to corresponding control module with the synchronizing signal of synchronizing signal synchronised received and clock signal, and the synchronizing signal received and clock signal are transmitted to adjacent thereto another from timing generation module.
Step S103, after each graphics streams read changes into figure signal, output is to corresponding display device.
Embodiments of the invention utilize computer cluster jointly to generate the single ultrahigh resolution figure formed by multiple graphic joinings, store after input signal being converted to graph data according to synchronization input logic after the figure signal receiving computer display card output, and according to synchronism output logic, output synchronizing signal based on system and clock signal, graph data is read and is converted to figure signal and transmit to display device, the frame per second making each figure signal that output arrives display system is the most consistent with synchronizing signal phase place, system entirety output picture is smooth without tear, graphical quality is better than the system synchronized based on software frame per second.
Embodiment two
Fig. 2 shows the concrete process chart of the synchronous method of figure signal in the computer cluster splice displaying system of according to embodiments of the present invention two, as shown in Figure 2, in systems, actual output frame rate based on each computer display card is different, therefore, some computer display card output frame rates are faster than the output frame rate of sync card, some computer display card output frame rates are slower than the output frame rate of sync card, the graphic frame that sequence number is identical is broadcasted in order to make all of figure sync card synchronize, each sync card needs the figure signal of input is carried out synchronization process, synchronization process step is as follows:
The write logic of FIFO memory performs odd number step, and the reading logic of FIFO memory performs even number step；When, after system start-up, the execution step of FIFO memory write logic is i.e.
Step S201, FIFO memory allows write graph data, graphic frame numbering N=1, and FIFO memory write pointer resets, i.e. FIFO memory is write logic initialization；
Step S203, figure incoming frame starts？If so, step S205 is performed, if it is not, return step S201；
Step S205, it is allowed to graphic frame writes？If so, step S207 is performed, if it is not, perform step S217；
Step S207, writes graph data and flows to FIFO memory；
Step S209, vertical trace terminates？If so, step S211 is performed, if it is not, return step S207；
Step S211, frame number N=N+1；
Step S213, FIFO memory data volume reaches upper threshold value？If so, perform step S215, now send to suspend to main frame and interrupt application, if it is not, return step S201；
Step S215, FIFO memory forbid write graphics streams, this step complete after return step S201；
Step S217, vertical flyback starts？If so, step S219 is performed；If it is not, return step S205；
Step S219, the data volume of FIFO memory reaches to restart threshold value？If so, step S223 is performed, if it is not, perform step S221；
Step S221, vertical flyback terminates？If so, step S201 is returned, if it is not, perform step S219；
Step S223, FIFO memory allows write graphics streams, now sends to main frame and restart interruption application.
When, after system start-up, FIFO memory reads the execution step of logic i.e.
Step S202, removes repeating frame mark, and FIFO memory read pointer resets, i.e. FIFO memory is read logic initialization；
Step S204, if be main sync card？If so, step S204-1 is performed, if it is not, perform step S204-2；Step S204-1, reaches to start threshold value？If so, perform step S204-11, i.e. send starting impulse, perform step S206；Return step S204 if not；Step S204-2, receives starting impulse？If so, step S206 is performed, if it is not, return step S204；
Polylith sync card needs to start output simultaneously, and needs to make FIFO memory restart after filling a part of graph data, it is to avoid quickly occurs that FIFO memory is empty, and makes write pointer forever be ahead of read pointer.
Step S206, images outputting frame starts？If so, step S208 is performed, if it is not, return step S204-11 for main sync card, for then returning step S204-2 from sync card；
Step S208, repeating frame mark is effective？If so, step S210 is performed, if it is not, perform step S212；
Step S210, read pointer points to the start address of previous frame, removes repeating frame mark；
Step S212, reads graphics streams from FIFO memory；
Step S214, vertical trace terminates？If so, step S216 is performed, if it is not, return step S212；
Step S216, FIFO memory reaches lower threshold value？If so, step S218 is performed, if it is not, perform step S220；
Step S218, puts repeating frame mark, sends repeating frame pulse, returns step S204-11；
Step S220, vertical flyback terminates？If so, step S204-11 is returned for main sync card, for then returning step S204-2 from sync card, if it is not, perform step S222；
Step S222, receives repeating frame pulse？If so, step S224 is performed, if it is not, return step S220；
Step S224, puts repeating frame pulse, returns step S204-2.
Above-mentioned steps completes arbitrary sync card synchronization process to tablet pattern signal in system.
Embodiment three
Fig. 3 shows the synchronous method Computer Host Interrupt process chart of figure signal in the computer cluster splice displaying system of according to embodiments of the present invention three；As it is shown on figure 3, main frame interrupt processing step is as follows:
Step S301, system start-up；
Step S302, broadcasts graphic frame；
Step S303, main frame receives time-out and interrupts application？If so, perform step S304, return step S302 if not；
Step S304, records up-to-date numbering N having been played out graphic frame；
Step S305, stops broadcasting new graphic frame；
Step S306, computer receives restarts interruption application？If so, step S307 is performed, if it is not, return step S305；
Step S307, sends new graphic frame to computer display card again, and the numbering of last graphic frame broadcasted before the numbered time-out of new graphic frame adds one, i.e. starts to restart broadcast graphic frame from N+1 frame.
Embodiment four
Fig. 4 shows the structural representation of the sync card of according to embodiments of the present invention four, as shown in Figure 4, this sync card includes: figure signal receiver module 10, timing generation module 20, control module 30, FIFO FIFO memory 40 and figure signal sending module 50, wherein
Figure signal receiver module 10, is connected with computer display card and control module 30 respectively, for receiving the figure signal of computer display card output, and exports to control module 30 after figure signal changes into digital graphic data stream；
Wherein, the figure signal received can be: the forms such as VGA, DVI, HDMI；It addition, the display mode information that figure signal receiver module 10 also stores sync card support reads for computer display card；
Timing generation module 20, is connected with control module 30, is used for generating synchronizing signal and clock signal to control module 30；
Wherein, when timing generation module is main timing generation module, synchronizing signal and clock signal generate (the reference video input shown in accompanying drawing 4 is optional) based on reference video input signal or according to self clock free-running operation, timing generation module is when timing generation module, synchronizing signal and clock signal be based on come autonomous timing generation module self occur synchronizing signal and clock signal and generate.
Control module 30, respectively with FIFO memory 40, figure signal receiver module 10 and figure signal sending module 50 are connected, for receiving logic according to synchronization, graphics streams is write FIFO memory 40, and according to synchronism output logic, output synchronizing signal based on system and clock signal, export to figure signal sending module 50 after being read by graphics streams from FIFO memory 40；Concrete operations are:
When the graph data amount in FIFO memory 40 reaches default upper threshold value, during the vertical flyback of tablet pattern signal, control module 30 sends to suspend to main frame interrupts application, and forbid writing new graph data to FIFO memory 40, hereafter, graph data amount in FIFO memory 40 gradually decreases, when graph data amount less than preset when restarting threshold value, control module 30 sends to main frame restarts interruption application, and allows to write new graph data to FIFO memory 40；When the graph data amount in certain FIFO memory 40 in cluster is less than the lower threshold value preset, after the control module 30 corresponding with this FIFO memory 40 reads whole graph datas of present frame, again read pointer is placed in the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback broadcasting figure signal before broadcasting repeating frame, the control module 30 corresponding with this FIFO memory 40 can send repeating frame pulse to other all of control modules 30, read pointer is also placed in and has been played out at the start address of frame before by other all control modules 30, in an ensuing frame time, repeat the frame broadcasted before broadcasting.
FIFO memory 40, is connected with control module 30, for control based on control module 30, caches graphics streams；
Figure signal sending module 50, it is connected with control module 30 and display device respectively, for receiving the graphics streams that control module 30 transmits, and graphics streams is changed into output extremely described display device after figure signal, additionally, figure signal sending module 50 can also read the display mode information that display device is supported, for control module 30.
In embodiments of the invention, computer cluster is utilized jointly to generate the single ultrahigh resolution figure formed by multiple graphic joinings, store after input signal being converted to graph data according to synchronization input logic after the figure signal receiving computer display card output, and according to synchronism output logic, output synchronizing signal based on system and clock signal, graph data reads and is converted into figure signal transmit to display device, the frame per second making each figure signal that output arrives display system is the most consistent with synchronizing signal phase place, system entirety output picture is smooth without tear, graphical quality is better than the system synchronized based on software frame per second；Any computer display card can be used simultaneously, the system built compared to the high-end video card synchronized outside support based on single model, there is lower cost and higher motility.
Embodiment five
Fig. 5 shows the structural representation of the sync card of according to embodiments of the present invention five；As it is shown in figure 5, control module 30 also includes: control pulse input/output interface 302, be connected with other all control modules 30, be used for sending starting impulse or repeating frame pulse to other all control modules 30.Wherein, as the control module 30 of main sync card in order to make all to start from sync card simultaneously, starting impulse can be sent to all control modules 30 from sync card, but whether the control module of main sync card is still from the control module of sync card, according to synchronism output logic and based on synchronizing signal and clock signal, the repeating frame pulse control module to other all of sync cards can be sent.
Embodiment six
Fig. 6 shows the connection diagram of multiple stage computer graphical sync card in the group system of according to embodiments of the present invention six；As shown in Figure 6, we are as a example by three computer graphical sync cards, and the signal input/output relation between sync card and connected mode be described:
First, timing generation module 20 also includes: figure synchronizing signal output interface 202 and figure synchronizing signal input interface 204, wherein:
Figure synchronizing signal output interface 202, when timing generation module is main timing generation module, export to adjacent from timing generation module for the synchronizing signal that self is occurred and clock signal, when timing generation module is from timing generation module, adjacent from timing generation module for the synchronizing signal of input and clock signal are transmitted to.
Figure synchronizing signal input interface 504, for receiving the synchronizing signal from adjacent timing generation module and clock signal.
Wherein, figure synchronizing signal output interface 202 and figure synchronizing signal input interface 204 are bidirectional interfaces, both input interface can be worked as and output interface can also be worked as, if sync card is as main sync card, its figure synchronizing signal input interface 204 is used when output interface, i.e., figure synchronizing signal is exported to it adjacent from sync card by main sync card respectively, figure synchronizing signal input interface from sync card receives the figure synchronizing signal from adjacent sync card, the figure synchronizing signal ring received is gone out by the figure synchronizing signal output interface from sync card, it is transmitted to an other adjacent sync card.
As the control module 30 of main sync card in order to make all to start from sync card simultaneously, starting impulse can be sent to all control modules 30 from sync card, but whether the control module of main sync card is still from the control module of sync card, the repeating frame pulse control module to other all of sync cards can be sent according to synchronism output logic and based on synchronizing signal and clock signal.
Embodiments of the invention utilize computer cluster jointly to generate the single ultrahigh resolution figure formed by multiple graphic joinings, a sync card installed by every computer in cluster, the figure signal of computer display card output is connected to the sync card of correspondence, the output signal of sync card is connected to the display device of correspondence, in system, all of sync card synchronizes to broadcast the graphic frame that sequence number is identical, every sync card carries out output pattern signal after synchronization process to display device corresponding to this computer to the figure signal of input, sync card is also to corresponding computer feedback operation state, and accept the control of computer, the frame per second making each figure signal that output arrives display system is the most consistent with synchronizing signal phase place, system entirety output picture is smooth without tear, graphical quality is better than the system synchronized based on software frame per second.
Embodiment seven
Fig. 7 shows the structural representation of the sync card of according to embodiments of the present invention seven；As shown in Figure 7, sync card also includes: computer external interface 60, it is connected with control module 30, is connected with main frame by computer bus interfaces such as PCI, PCIe, main frame carries out communication by computer external interface 60 and control module 30, query facility state, configuration device parameter, receives and the interrupt requests etc. of response module generation.
It addition, when bus bandwidth is enough, sync card is also used as capture card and is gathered by graph data into computer, or will broadcast on the graphical data transmission in computer to sync card.
Embodiments of the invention utilize computer cluster jointly to generate the single ultrahigh resolution figure formed by multiple graphic joinings, a sync card installed by every computer in cluster, the figure signal of computer display card output is connected to the sync card of correspondence, the output signal of sync card is connected to the display device of correspondence, in system, all of sync card synchronizes to broadcast the graphic frame that sequence number is identical, every sync card carries out output pattern signal after synchronization process to display device corresponding to this computer to the figure signal of input, sync card is also to corresponding computer feedback operation state, and accept the control of computer, the frame per second making each figure signal that output arrives display system is the most consistent with synchronizing signal phase place, system entirety output picture is smooth without tear, graphical quality is better than the system synchronized based on software frame per second；Owing to technical scheme can use any computer display card, the system built compared to the high-end video card synchronized outside support based on single model, there is lower cost and higher motility.Owing to technical scheme can realize computer graphical signal and the synchronization of a television image signal, solve common computer display system in prior art and can not realize the problem Tong Bu with TV signal.
Obviously, those skilled in the art should be understood that, each module of the above-mentioned present invention or each step can realize with general calculating device, they can concentrate on single calculating device, or it is distributed on the network that multiple calculating device is formed, alternatively, they can realize with calculating the executable program code of device, thus, can be stored in storing in device and be performed by calculating device, or they are fabricated to respectively each integrated circuit modules, or the multiple modules in them or step are fabricated to single integrated circuit module realize.So, the present invention is not restricted to the combination of any specific hardware and software.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (11)
1. the synchronous method of figure signal in a computer cluster splice displaying system, it is characterised in that including:
Receive the figure signal of each computer display card output in cluster, and described each figure signal is changed into digital graphic data stream；
Control module is according to synchronizing reception logic by FIFO FIFO memory corresponding for the write of described each graphics streams, and according to synchronism output logic, output synchronizing signal based on system and clock signal, read described graphics streams from described FIFO memory；
Wherein, described according to synchronizing reception logic by FIFO FIFO memory corresponding for the write of described each graphics streams, including: when the graph data amount in described FIFO memory reaches default upper threshold value, during the vertical flyback of tablet pattern signal, described control module sends to suspend to main frame interrupts application, and forbid to the graph data that the write of described FIFO memory is new, hereafter, graph data amount in described FIFO memory gradually decreases, when described graph data amount less than preset when restarting threshold value, described control module sends to main frame restarts interruption application, and allow to write new graph data to described FIFO memory；
Described according to synchronism output logic, output synchronizing signal based on system and clock signal, described graphics streams is read from described FIFO memory, including: when the graph data amount in the described FIFO memory of certain in cluster is less than the lower threshold value preset, after the described control module corresponding with this FIFO memory reads whole graph datas of present frame, again read pointer is placed in the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback broadcasting figure signal before broadcasting repeating frame, the described control module corresponding with this FIFO memory can send repeating frame pulse to other all of control modules, read pointer is also placed in and has been played out at the start address of frame before by other all control modules, in an ensuing frame time, repeat the frame broadcasted before broadcasting；
After the described each graphics streams read changes into figure signal, output is to corresponding display device.
The synchronous method of figure signal in computer cluster splice displaying system the most according to claim 1, it is characterised in that in described reception cluster before the figure signal of each computer display card output, the method also includes:
Every main frame is to self needing the graphic frame generating and broadcasting to carry out serial number.
The synchronous method of figure signal in computer cluster splice displaying system the most according to claim 1, it is characterised in that in described control module after main frame sends time-out interruption application, the method also includes:
The described time-out of main frame response interrupts application, suspends and broadcasts new graphic frame, records the up-to-date numbering having been played out graphic frame.
The synchronous method of figure signal in computer cluster splice displaying system the most according to claim 1, it is characterised in that in described control module after interruption application is restarted in main frame transmission, the method also includes:
Restarting interruption application described in main frame response, again send new graphic frame to computer display card, the numbering of last graphic frame broadcasted before the numbered time-out of new graphic frame adds one.
The synchronous method of figure signal in computer cluster splice displaying system the most according to claim 1, it is characterized in that, described synchronizing signal and clock signal are generated based on reference video input signal or self clock free-running operation by main timing generation module, and described synchronizing signal and clock signal are sent to corresponding control module.
The synchronous method of figure signal in computer cluster splice displaying system the most according to claim 5, it is characterized in that, described synchronizing signal and clock signal are exported to arbitrary adjacent thereto from timing generation module by described main timing generation module, described generation from timing generation module is sent to corresponding control module with the synchronizing signal of described synchronizing signal synchronised received and clock signal, and the described synchronizing signal received and clock signal is transmitted to adjacent thereto another from timing generation module.
7. a sync card, it is characterised in that including: figure signal receiver module, timing generation module, control module, FIFO FIFO memory and figure signal sending module, wherein,
Described figure signal receiver module, is connected with computer display card and described control module respectively, for receiving the figure signal of described computer display card output, and exports to described control module after described figure signal is changed into digital graphic data stream；
Described timing generation module, is connected with described control module, is used for generating synchronizing signal and clock signal to described control module；
Described control module, it is connected with described FIFO memory, described timing generation module, described figure signal receiver module and described figure signal sending module, for according to synchronizing reception logic by the described graphics streams described FIFO memory of write, and according to synchronism output logic, output synchronizing signal based on system and clock signal, export to described figure signal sending module after being read by described graphics streams from described FIFO memory；
Wherein, described according to synchronizing reception logic by the described graphics streams described FIFO memory of write, including: when the graph data amount in described FIFO memory reaches default upper threshold value, during the vertical flyback of tablet pattern signal, described control module sends to suspend to main frame interrupts application, and forbid to the graph data that the write of described FIFO memory is new, hereafter, graph data amount in described FIFO memory gradually decreases, when described graph data amount less than preset when restarting threshold value, described control module sends to main frame restarts interruption application, and allow to write new graph data to described FIFO memory；
Described according to synchronism output logic, output synchronizing signal based on system and clock signal, described graphics streams is read from described FIFO memory, including: when the graph data amount in the described FIFO memory of certain in cluster is less than the lower threshold value preset, after the described control module corresponding with this FIFO memory reads whole graph datas of present frame, again read pointer is placed in the beginning of this frame, repeat to broadcast this frame, simultaneously, during the vertical flyback broadcasting figure signal before broadcasting repeating frame, the described control module corresponding with this FIFO memory can send repeating frame pulse to other all of control modules, read pointer is also placed in and has been played out at the start address of frame before by other all control modules, in an ensuing frame time, repeat the frame broadcasted before broadcasting；
Described FIFO memory, is connected with described control module, for control based on described control module, caches described graphics streams；
Described figure signal sending module, is connected with described control module and display device respectively, for receiving the graphics streams that described control module transmits, and described graphics streams changes into output extremely described display device after figure signal.
Sync card the most according to claim 7, it is characterised in that described control module also includes controlling pulse input/output interface, is connected with other all control modules, is used for sending starting impulse or described repeating frame pulse to other all control modules.
Sync card the most according to claim 7, it is characterized in that, when described timing generation module is main timing generation module, described synchronizing signal and clock signal generate based on reference video input signal or according to self clock free-running operation, described timing generation module is when timing generation module, and described synchronizing signal and clock signal are to generate based on the synchronizing signal occurred from described main timing generation module self and clock signal.
Sync card the most according to claim 9, it is characterised in that described timing generation module also includes: figure synchronizing signal output interface and figure synchronizing signal input interface, wherein:
Described figure synchronizing signal output interface, when described timing generation module is main timing generation module, for the synchronizing signal that self is occurred and clock signal export to described in adjacent from timing generation module, when described timing generation module is from timing generation module, adjacent from timing generation module for the synchronizing signal of input and clock signal are transmitted to；
Described figure synchronizing signal input interface, for receiving the synchronizing signal from adjacent described timing generation module and clock signal.
11. sync cards according to claim 7, it is characterized in that, also including computer external interface, be connected with described control module, be connected with main frame by computer bus interface, main frame carries out communication by described computer external interface and described control module.
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| CN110677553B (en) * | 2019-10-31 | 2020-11-24 | 威创集团股份有限公司 | Method, device, system and equipment for synchronously displaying signals of splicing wall |
| CN113672413B (en) * | 2021-10-25 | 2022-02-11 | 摩尔线程智能科技(北京)有限责任公司 | Data flow control method and device of independent display card and independent display card |
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| CN101776985B (en) * | 2009-12-29 | 2011-07-27 | 广东威创视讯科技股份有限公司 | Synchronous display device, and synchronous splicing display system and synchronous display method thereof |
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