CN110677553B - Method, device, system and equipment for synchronously displaying signals of splicing wall - Google Patents
Method, device, system and equipment for synchronously displaying signals of splicing wall Download PDFInfo
- Publication number
- CN110677553B CN110677553B CN201911055724.5A CN201911055724A CN110677553B CN 110677553 B CN110677553 B CN 110677553B CN 201911055724 A CN201911055724 A CN 201911055724A CN 110677553 B CN110677553 B CN 110677553B
- Authority
- CN
- China
- Prior art keywords
- signal
- data
- line
- codes
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2624—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects for obtaining an image which is composed of whole input images, e.g. splitscreen
Abstract
The application discloses a method, a device, a system and equipment for synchronously displaying signals of a splicing wall, which encode output synchronous signals into image signal data for transmission, then receive the data for decoding, analyze the image time sequence information of the image signal data, continuously read the image signal data and display the images, thereby realizing the synchronous display of the signals of the splicing wall, the synchronous display mode does not need to use a synchronous line, does not need to use a synchronous line on the splicing wall, avoids the stability problem caused by abnormal connection of the synchronous line of the splicing wall, solves the technical problems that the prior splicing wall system needs to use the synchronous line to transmit the synchronous signals in each display unit of the splicing wall to realize the signal synchronization, the circuits on the splicing wall are more, the display of each display unit on the splicing wall is caused when the abnormal connection of the synchronous line, and the stability of the splicing wall system is influenced, meanwhile, the cost caused by using the synchronous line is reduced, and the cost problem of the spliced wall system is solved.
Description
Technical Field
The present application relates to the field of signal processing technologies, and in particular, to a method, an apparatus, a system, and a device for synchronizing signals of a splicing wall.
Background
The spliced wall is formed by splicing a plurality of display units, and the image splicing display mode is that image signals are transmitted to each display unit in a cascading mode and are displayed after being processed by the display units. In the splicing wall system, in order to ensure that the image frames output and displayed by each display unit are synchronous and realize the synchronization of the image frames displayed by each unit and the played images, all the display units are connected through a synchronization line, the synchronization line transmits synchronization signals, and each display unit outputs and displays according to the synchronization signals, thereby realizing the synchronization.
The currently used synchronization line is a BNC line, and the synchronization signal transmitted through the BNC line is a periodic pulse signal, the period of which is the frame rate of display, for example, the frame rate of display of a tiled wall is 60Hz, and the synchronization signal is a 60Hz pulse signal. As shown in fig. 1, in addition to a BNC line, a BNC line is connected to each unit on a splicing wall, and a SERDES line for cascading input image signals is also connected to each display unit, when no external synchronization signal is input, a synchronization signal is generated by a first display unit of the splicing wall and transmitted to all display units through the BNC line, when an external synchronization signal is input, for example, a video camera takes a picture and transmits the picture to the splicing wall, the video camera outputs the synchronization signal, the synchronization signal output by the video camera is the external synchronization signal, the externally input synchronization signal is input to the first display unit, and the first display unit transmits the externally input synchronization signal to all display units through the BNC line. However, the number of lines on the spliced wall is large, and asynchronous display of each display unit on the spliced wall can be caused when the synchronous line connection is abnormal, so that the stability of the spliced wall system is influenced.
Disclosure of Invention
The application provides a method, a device, a system and equipment for synchronously displaying signals of a spliced wall, which are used for solving the technical problems that the prior spliced wall system needs to use a synchronous line to transmit synchronous signals in each display unit of the spliced wall to realize signal synchronization, more lines are arranged on the spliced wall, the asynchronous display of each display unit on the spliced wall is caused when the synchronous line connection is abnormal, and the stability of the spliced wall system is influenced.
In view of the above, a first aspect of the present application provides a method for synchronously displaying a signal on a splicing wall, including:
taking a line effective signal as a write enable signal, writing acquired image signal data into a first line data cache, delaying the line effective signal by one line to be taken as a read enable signal, reading a start mark K code of the line signal and an end mark K code of the line signal, wherein the image signal data adopts a D code;
under the trigger of a synchronous signal, if image signal data are sent at the rising edge moment of the synchronous signal, pulling down a read enabling signal, and after inserting two first filling K codes into SERDES serial data corresponding to the rising edge moment, pulling up the read enabling signal to continuously send the image signal data;
when two continuous start mark K codes are received, a write enable signal is pulled up, the image signal data is written into a second line of data cache, until two continuous first filling K codes are received in the process of writing into the second line of data cache, the write enable signal is pulled up after two clocks are pulled down, the image signal data is continuously written into the second line of data cache, and until two continuous end mark K codes are received, the write enable signal is pulled down;
and analyzing the image time sequence information of the image signal data, determining a data effective signal, taking the data effective signal as a read enable signal of the second line data cache, and reading the image signal data from the second line data cache for image display.
Optionally, under the trigger of the synchronization signal, if image signal data is sent at a rising edge time of the synchronization signal, the read enable signal is pulled down, and after two first padding K codes are inserted into serial data of the SERDES corresponding to the rising edge time, the read enable signal is pulled up, and the image signal data continues to be sent, before further including:
and detecting whether an external synchronous signal is input, if so, taking the external synchronous signal as the synchronous signal, otherwise, triggering a first display unit of the spliced wall to generate the synchronous signal.
Optionally, under the trigger of the input synchronization signal, if the image signal data is sent at the rising edge time of the input synchronization signal, the read enable signal is pulled down, and after two first padding K codes are inserted into the serial data of the SERDES corresponding to the rising edge time, the read enable signal is pulled up to continue sending the image signal data, further including:
if the image signal data is not sent at the rising edge moment of the synchronous signal, replacing two second filling K codes of SERDES serial data corresponding to the rising edge moment with the two first filling K codes;
accordingly, the number of the first and second electrodes,
and when two continuous first filling K codes are received, the clock of the synchronous signal corresponding to the first filling K codes is pulled high.
Optionally, the first padding K code is K28.6, the start marker K code is K28.1, and the end marker K code is K28.2.
Optionally, the second padded K-code is K28.4.
The second aspect of the present application provides a synchronous display device for signal of a splicing wall, including:
the writing module is used for writing the acquired image signal data into a first line data cache by taking a line effective signal as a writing enabling signal, delaying the line effective signal by one line to be taken as a reading enabling signal, reading a starting mark K code of the line signal and an ending mark K code of the line signal, wherein the image signal data adopts a D code;
the encoding sending module is used for pulling down a read enabling signal if image signal data are sent at the rising edge moment of the synchronous signal under the trigger of the synchronous signal, pulling up the read enabling signal after two first filling K codes are inserted into SERDES serial data corresponding to the rising edge moment, and continuously sending the image signal data;
the receiving module is used for pulling up a write enable signal when two continuous start mark K codes are received, writing the image signal data into a second line of data cache until two continuous first filling K codes are received in the process of writing into the second line of data cache, pulling down the write enable signal by two clocks and then pulling up the write enable signal, and continuously writing the image signal data into the second line of data cache until two continuous end mark K codes are received, and pulling down the write enable signal;
and the decoding display module is used for analyzing the image time sequence information of the image signal data, determining a data effective signal, taking the data effective signal as a read enabling signal of the second line data cache, and reading the image signal data from the second line data cache for image display.
Optionally, the method further comprises:
and the detection module is used for detecting whether an external synchronous signal is input, if so, the external synchronous signal is used as the synchronous signal, otherwise, a first display unit of the spliced wall is triggered to generate the synchronous signal.
Optionally, the encoding sending module is further configured to:
if the image signal data is not sent at the rising edge moment of the synchronous signal, replacing two second filling K codes of SERDES serial data corresponding to the rising edge moment with the two first filling K codes;
accordingly, the number of the first and second electrodes,
the receiving module is further configured to pull up the clock of the synchronization signal corresponding to the first K-pad code when two consecutive first K-pad codes are received.
The third aspect of the application provides a system for synchronously displaying signals of a splicing wall, which comprises a sending end and a receiving end;
the sending end is used for:
taking a line effective signal as a write enable signal, writing acquired image signal data into a first line data cache, delaying the line effective signal by one line to be taken as a read enable signal, reading a start mark K code of the line signal and an end mark K code of the line signal, wherein the image signal data adopts a D code;
under the trigger of a synchronous signal, if image signal data are sent at the rising edge moment of the synchronous signal, pulling down a read enabling signal, and after inserting two first filling K codes into SERDES serial data corresponding to the rising edge moment, pulling up the read enabling signal to continuously send the image signal data;
the receiving end is used for:
when two continuous start mark K codes are received, a write enable signal is pulled up, the image signal data is written into a second line of data cache, until two continuous first filling K codes are received in the process of writing into the second line of data cache, the write enable signal is pulled up after two clocks are pulled down, the image signal data is continuously written into the second line of data cache, and until two continuous end mark K codes are received, the write enable signal is pulled down;
and analyzing the image time sequence information of the image signal data, determining a data effective signal, taking the data effective signal as a read enable signal of the second line data cache, and reading the image signal data from the second line data cache for image display.
The fourth aspect of the present application provides a synchronous display device for signals of a splicing wall, the device comprising a processor and a memory:
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is used for executing any one of the spliced wall signal synchronous display methods of the first aspect according to instructions in the program code.
According to the technical scheme, the embodiment of the application has the following advantages:
the application provides a method for synchronously displaying signals of a splicing wall, which comprises the following steps: taking the line effective signal as a write enable signal, writing the acquired image signal data into a first line data cache, delaying one line of the line effective signal to be taken as a read enable signal, reading a start mark K code of the line signal and an end mark K code of the line signal, and adopting a D code for the image signal data; under the trigger of the synchronizing signal, if image signal data are sent at the rising edge moment of the synchronizing signal, pulling down a read enabling signal, and after inserting two first filling K codes into SERDES serial data corresponding to the rising edge moment, pulling up the read enabling signal to continuously send the image signal data; when two continuous start mark K codes are received, the write enable signal is pulled up, the image signal data is written into the second line data cache, until two continuous first filling K codes are received in the process of writing into the second line data cache, the write enable signal is pulled up after two clocks are pulled down, the image signal data is continuously written into the second line data cache, and until two continuous end mark K codes are received, the write enable signal is pulled down; and analyzing the image time sequence information of the image signal data, determining a data effective signal, taking the data effective signal as a read enable signal of the second line data buffer, and reading the image signal data from the second line data buffer for image display.
The method writes image signal data into line data buffer memory to ensure that the image signal data is not lost when inserting synchronous codes, utilizes K codes as mark codes for outputting synchronous, detects the rising edge time of synchronous signals, if the image signal data is sent, pulls down a read enabling signal, inserts two first filling K codes into SERDES serial data corresponding to the rising edge time, codes the output synchronous signals into the image signal data, pulls up the read enabling signal, continues to send the image signal data, decodes when receiving the data, buffers the image line for ensuring the continuity of the image signal data, analyzes the image time sequence information of the image signal data, continuously reads the image signal data and displays the image, thereby realizing the synchronous display of the spliced wall signal, synchronous display mode need not use the synchronizing line, need not use the synchronizing line on the concatenation wall, the stability problem of having avoided concatenation wall synchronizing line to connect abnormal the bringing, it needs to use the synchronizing line to transmit synchronizing signal in each display element of concatenation wall to realize the signal synchronization to have solved current concatenation wall system, the circuit on the concatenation wall is more, it is asynchronous that each display element shows on the concatenation wall can be caused when the synchronizing line is connected unusually, the technical problem of the stability of influence concatenation wall system, the cost that the use synchronizing line brought has also been reduced simultaneously, the cost problem of concatenation wall system has been solved.
Drawings
FIG. 1 illustrates a splicing wall synchronization signal and image signal cascade method in the prior art;
fig. 2 is a schematic flowchart of a method for synchronously displaying signals on a splicing wall according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of codes embedded in output synchronization during image signal data transmission according to an embodiment of the present application;
FIG. 4 is a schematic diagram of the encoding of the output synchronization provided in the embodiment of the present application when the image signal data is not transmitted;
fig. 5 is another schematic flow chart of a method for synchronously displaying signals on a splicing wall according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a synchronous display device for signals of a splicing wall provided in an embodiment of the present application;
fig. 7 is a schematic structural diagram of a transmitting end in a synchronous display system for a signal of a splicing wall provided in an embodiment of the present application;
fig. 8 is a schematic structural diagram of a receiving end in a synchronous display system for a signal of a splicing wall according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For easy understanding, referring to fig. 1 to 3, an embodiment of a method for synchronously displaying a signal on a tiled wall according to the present invention includes:
It should be noted that, as shown in fig. 1, in the prior art, in addition to the BNC line connecting the units, a SERDES line for cascading the input image signal is also connected to each display unit on the mosaic wall. The purpose of the application is to cancel a BNC line, and realize synchronization by encoding an output synchronization signal into image signal data transmitted by a SERDES, so that the unstable risk of a splicing wall signal caused by abnormal BNC connection is reduced. The data transmitted by the splicing wall system can be transmitted by a high-speed serial transceiver SERDES, the transmitted data comprises K codes and D codes, the D codes are mainly used for transmitting data by the high-speed serial transceiver, the total number of the K codes is 12, the data is mainly used for controlling the high-speed serial transceiver and comprises bit alignment and high and low marks, the K codes are used as mark codes for outputting synchronization in the embodiment of the application, and the D codes are used for transmitting image signal data. The acquired image signal data is written into the first line of data cache, so that data loss caused by inserting data when the image signal data is subsequently coded can be prevented. The start flag K code in step 101 may be K28.1, and the end flag K code may be K28.2.
And 102, under the trigger of the synchronous signal, if the image signal data is sent at the rising edge moment of the synchronous signal, pulling down the read enabling signal, and after inserting two first filling K codes into SERDES serial data corresponding to the rising edge moment, pulling up the read enabling signal to continuously send the image signal data.
It should be noted that, when there is a synchronization signal, a rising edge of the synchronization signal is detected, if the image signal data is being transmitted by the high-speed serial transceiver SERDES at the time of the rising edge of the synchronization signal, that is, the D code is being transmitted by the SERDES at the time of the rising edge of the synchronization signal, the read enable signal is pulled down, the two first padding K codes are inserted, and the image signal data is encoded, as shown in fig. 3, after the insertion is completed, the read enable signal is pulled up, and the image data is continuously transmitted.
And 103, pulling up the write enable signal when two continuous start mark K codes are received, writing the image signal data into the second line data cache, pulling down the write enable signal by two clocks and then pulling up the write enable signal until two continuous first filling K codes are received in the process of writing into the second line data cache, and continuously writing the image signal data into the second line data cache until two continuous end mark K codes are received, and pulling down the write enable signal.
It should be noted that, when the image data sent in step 102 is received and two consecutive start mark K codes are received, it indicates that line data starts, at this time, the write enable signal is pulled high, and the image line data is written into the second line data buffer, until two consecutive end mark K codes are received in the writing process, the write enable signal is pulled low. Writing the image line data into the second line data buffer and continuously reading out the image line data can ensure the continuity of the image signal data.
And step 104, analyzing the image time sequence information of the image signal data, determining a data effective signal, taking the data effective signal as a read enable signal of the second row data cache, and reading the image signal data from the second row data cache for image display.
The image signal data is decoded, the image timing information of the image signal data is analyzed, the image timing is generated, the field synchronization signal, the line synchronization signal and the data valid signal can be determined according to the image timing information, the data valid signal is used as a read enable signal of the second line data buffer, and the image signal data is read from the second line data buffer for image display. The decoding process can be described as: receiving image signal data, determining that a current frame image starts to be transmitted when an image frame start code is received, receiving a data code, analyzing image frame information of the frame image according to the data code, determining a field synchronizing signal, a line synchronizing signal and a data effective signal according to the image frame information, determining a line effective signal rising edge of the frame image when the line start code is received, receiving a line data signal of the frame image, determining a line effective signal falling edge of the frame image when a line end code is received, and determining that decoding of the current frame image is completed when the frame end code is received.
The method for synchronously displaying the spliced wall signals, provided by the embodiment of the application, writes the image signal data into a line data cache to ensure that the image signal data is not lost when the synchronous codes are inserted, utilizes a K code as a mark code for outputting the synchronization, detects the rising edge moment of the synchronization signal, if the image signal data is sent, lowers a read enabling signal, inserts two first filling K codes into SERDES serial data corresponding to the rising edge moment, codes the output synchronization signal into the image signal data, then raises the read enabling signal, continuously sends the image signal data, decodes when receiving the data, caches the image line to ensure the continuity of the image signal data when decoding, continuously reads the image signal data after analyzing the image time sequence information of the image signal data and displays the image, thereby realizing the synchronous display of the spliced wall signals, synchronous display mode need not use the synchronizing line, need not use the synchronizing line on the concatenation wall, the stability problem of having avoided concatenation wall synchronizing line to connect abnormal the bringing, it needs to use the synchronizing line to transmit synchronizing signal in each display element of concatenation wall to realize the signal synchronization to have solved current concatenation wall system, the circuit on the concatenation wall is more, it is asynchronous that each display element shows on the concatenation wall can be caused when the synchronizing line is connected unusually, the technical problem of the stability of influence concatenation wall system, the cost that the use synchronizing line brought has also been reduced simultaneously, the cost problem of concatenation wall system has been solved.
For ease of understanding, please refer to fig. 3 to 5, as a modification of the previous embodiment, step 1012 may also be performed before step 102 in the present application.
And 1012, detecting whether an external synchronous signal is input, if so, taking the external synchronous signal as the synchronous signal, otherwise, triggering a first display unit of the splicing wall to generate the synchronous signal.
It should be noted that the synchronization signal in this application may be input from the outside, for example, an external synchronization signal provided by a camera connected to the splicing wall, or may be provided by a first display unit of the splicing wall, where the first display unit of the splicing wall is a display unit in the upper left corner of the splicing wall by default. Therefore, the method for determining the synchronization signal may be to detect whether an external synchronization signal is input into the tiled wall, preferentially use the external synchronization signal as the synchronization signal of the tiled wall if the external synchronization signal is input, and generate a synchronization signal by the first display unit of the tiled wall if the external synchronization signal is not input.
In step 102 of the previous embodiment, as shown in fig. 4, in a case that the image signal data is not transmitted at the rising edge time of the synchronization signal, two second padded K codes of the SERDES serial data corresponding to the rising edge time may be replaced by two first padded K codes, where the second padded K code may be K28.4, and the first padded K code may be K28.6. Meanwhile, under the condition that the image signal data is not sent at the rising edge moment of the synchronous signal, two continuous first filling K codes K28.6 are received when the data are received, at the moment, the synchronous signal clock corresponding to the first filling K codes K28.6 is pulled high, and the output synchronization at other clock moments keeps low level, so that the decoding recovery of the output synchronous signal is realized.
For easy understanding, please refer to fig. 6, which provides an embodiment of a synchronous display device for a tiled wall signal, including:
the writing module 301 is configured to write the acquired image signal data into the first line data buffer by using the line valid signal as a write enable signal, delay the line valid signal by one line to serve as a read enable signal, and read a start flag K code of the line signal and an end flag K code of the line signal, where the image signal data adopts a D code.
The code sending module 302 is configured to, under the trigger of the synchronization signal, pull down the read enable signal if image signal data is sent at the rising edge time of the synchronization signal, and pull up the read enable signal after two first padding K codes are inserted into SERDES serial data corresponding to the rising edge time, so as to continue sending the image signal data.
The receiving module 303 is configured to pull up the write enable signal when two consecutive start mark K codes are received, write the image signal data into the second line data cache, pull up the write enable signal after pulling down two clocks until two consecutive first filling K codes are received in the process of writing into the second line data cache, and continue to write the image signal data into the second line data cache until two consecutive end mark K codes are received, pull down the write enable signal.
And the decoding display module 304 is configured to parse the image timing information of the image signal data, determine a data valid signal, take the data valid signal as a read enable signal of the second line data buffer, and read out the image signal data from the second line data buffer for image display.
As a further improvement, the method can further comprise the following steps:
the detecting module 305 is configured to detect whether an external synchronization signal is input, if so, use the external synchronization signal as a synchronization signal, and otherwise, trigger a first display unit of the tiled wall to generate the synchronization signal.
The code sending module 302 is further configured to:
if the image signal data is not sent at the rising edge moment of the synchronous signal, replacing two second filling K codes of the SERDES serial data corresponding to the rising edge moment with two first filling K codes;
accordingly, the number of the first and second electrodes,
the receiving module 303 is further configured to pull up a clock of a synchronization signal corresponding to the first K-pad code when two consecutive first K-pad codes are received.
For easy understanding, please refer to fig. 3, fig. 4, fig. 7, and fig. 8, which provide an embodiment of a system for synchronously displaying signals on a splicing wall, including a transmitting end and a receiving end;
the sending end is used for:
taking a line effective signal as a write enabling signal, writing the acquired image signal data into a first line data cache, delaying the line effective signal by one line to be taken as a read enabling signal, reading a start mark K code of the line signal and an end mark K code of the line signal, wherein the image signal data adopts a D code;
under the trigger of the synchronizing signal, if image signal data are sent at the rising edge moment of the synchronizing signal, pulling down a read enabling signal, after inserting two first filling K codes into SERDES serial data corresponding to the rising edge moment, pulling up the read enabling signal, and continuously sending the image signal data;
the receiving end is used for:
when two continuous start mark K codes are received, the write enable signal is pulled up, the image signal data is written into the second line data cache, until two continuous first filling K codes are received in the process of writing into the second line data cache, the write enable signal is pulled up after two clocks are pulled down, the image signal data is continuously written into the second line data cache, and until two continuous end mark K codes are received, the write enable signal is pulled down;
and analyzing the image time sequence information of the image signal data, determining a data effective signal, taking the data effective signal as a read enable signal of the second line data buffer, and reading the image signal data from the second line data buffer for image display.
It should be noted that, as shown in fig. 7, in the splicing wall signal synchronous display system in the embodiment of the present application, the operation performed by the sending end is:
after the image signal data is input, the line effective signal is used as a write enable signal, the image signal data is written into the line data cache, the line effective signal is delayed by one line to be used as a read enable signal, two K28.1 are sent as a mark for line data starting when the read signal starts, and two K28.2 are sent as an end mark when the read signal finishes.
And detecting whether external synchronous input exists or not, if the external synchronous input exists, using the external synchronization, and if the external synchronous input does not exist, triggering a first display unit of the splicing wall to generate a synchronous signal.
And detecting a rising edge of the synchronizing signal, if the SERDES sends the second filling K code K28.4 at the moment, indicating that no image signal data is transmitted, at the moment, replacing the two second filling K codes K28.4 corresponding to the rising edge moment with the two first filling K codes K28.6, if the rising edge of the synchronizing signal is detected, sending an image signal data D code by the SERDES, pulling down the read enabling signal, inserting the two K28.6, then pulling up the read enabling signal, and continuing to send the image signal data D code.
As shown in fig. 8, the receiving end performs the following operations:
and after two continuous K28.6 signals are received, the output synchronous signal is pulled high, the output synchronization at other clock moments keeps low level, and the decoding recovery of the output synchronous signal is realized.
When two continuous K28.1 starting mark codes are received, it is indicated that line data starts to be transmitted, at this time, a write enable signal is pulled high, image line data is written into a line data cache, when two K28.6 signals are received in the writing process, the write enable signal is pulled high after being pulled low by two clocks, the line data is continuously written into the cache until two continuous K28.2 ending mark codes are received in the writing process, it is indicated that the line data receiving is ended, at this time, the write enable signal is pulled low.
Decoding image time sequence information of the image signal data, generating image time sequence, determining a field synchronizing signal, a line synchronizing signal and a data effective signal according to the image time sequence information, taking the data effective signal as a read enabling signal of a line data buffer, and reading the image data from the line buffer for image display.
The application also provides a splicing wall signal synchronous display device, which comprises a processor and a memory:
the memory is used for storing the program codes and transmitting the program codes to the processor;
the processor is used for executing any one of the spliced wall signal synchronous display method embodiments according to instructions in the program code.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (8)
1. A splicing wall signal synchronous display method is characterized by comprising the following steps:
taking a line effective signal as a write enable signal, writing acquired image signal data into a first line data cache, delaying the line effective signal by one line to be taken as a read enable signal, reading a start mark K code of the line signal and an end mark K code of the line signal, wherein the image signal data adopts a D code;
under the trigger of a synchronous signal, if image signal data are sent at the rising edge moment of the synchronous signal, pulling down a read enabling signal, and after inserting two first filling K codes into SERDES serial data corresponding to the rising edge moment, pulling up the read enabling signal to continuously send the image signal data;
when two continuous start mark K codes are received, a write enable signal is pulled up, the image signal data is written into a second line of data cache, until two continuous first filling K codes are received in the process of writing into the second line of data cache, the write enable signal is pulled up after two clocks are pulled down, the image signal data is continuously written into the second line of data cache, and until two continuous end mark K codes are received, the write enable signal is pulled down;
if the image signal data is not sent at the rising edge moment of the synchronous signal, replacing two second filling K codes of SERDES serial data corresponding to the rising edge moment with the two first filling K codes;
accordingly, the number of the first and second electrodes,
when two continuous first filling K codes are received, the clock of the synchronous signal corresponding to the first filling K codes is pulled high;
and analyzing the image time sequence information of the image signal data, determining a data effective signal, taking the data effective signal as a read enable signal of the second line data cache, and reading the image signal data from the second line data cache for image display.
2. The method for synchronously displaying signals on a splicing wall according to claim 1, wherein under the trigger of the synchronization signal, if the image signal data is transmitted at the rising edge time of the synchronization signal, the read enable signal is pulled down, and after two first K-pad codes are inserted into serial data of a SERDES corresponding to the rising edge time, the read enable signal is pulled up, and the image signal data is continuously transmitted, the method further comprises:
and detecting whether an external synchronous signal is input, if so, taking the external synchronous signal as the synchronous signal, otherwise, triggering a first display unit of the spliced wall to generate the synchronous signal.
3. The method for synchronously displaying splicing wall signals according to claim 1, wherein the first padding K code is K28.6, the start mark K code is K28.1, and the end mark K code is K28.2.
4. The method for synchronously displaying a spliced wall signal as claimed in claim 1, wherein the second K-padded code is K28.4.
5. A splicing wall signal synchronous display device is characterized by comprising:
the writing module is used for writing the acquired image signal data into a first line data cache by taking a line effective signal as a writing enabling signal, delaying the line effective signal by one line to be taken as a reading enabling signal, reading a starting mark K code of the line signal and an ending mark K code of the line signal, wherein the image signal data adopts a D code;
the encoding sending module is used for pulling down a read enabling signal if image signal data are sent at the rising edge moment of the synchronous signal under the trigger of the synchronous signal, pulling up the read enabling signal after two first filling K codes are inserted into SERDES serial data corresponding to the rising edge moment, and continuously sending the image signal data;
the receiving module is used for pulling up a write enable signal when two continuous start mark K codes are received, writing the image signal data into a second line of data cache until two continuous first filling K codes are received in the process of writing into the second line of data cache, pulling down the write enable signal by two clocks and then pulling up the write enable signal, and continuously writing the image signal data into the second line of data cache until two continuous end mark K codes are received, and pulling down the write enable signal;
the code sending module is further configured to:
if the image signal data is not sent at the rising edge moment of the synchronous signal, replacing two second filling K codes of SERDES serial data corresponding to the rising edge moment with the two first filling K codes;
accordingly, the number of the first and second electrodes,
the receiving module is further configured to pull up the clock of the synchronization signal corresponding to the first K-pad code when two consecutive first K-pad codes are received;
and the decoding display module is used for analyzing the image time sequence information of the image signal data, determining a data effective signal, taking the data effective signal as a read enabling signal of the second line data cache, and reading the image signal data from the second line data cache for image display.
6. The synchronous display device of splicing wall signals according to claim 5, further comprising:
and the detection module is used for detecting whether an external synchronous signal is input, if so, the external synchronous signal is used as the synchronous signal, otherwise, a first display unit of the spliced wall is triggered to generate the synchronous signal.
7. A synchronous display system for signals of a splicing wall is characterized by comprising a sending end and a receiving end;
the sending end is used for:
taking a line effective signal as a write enable signal, writing acquired image signal data into a first line data cache, delaying the line effective signal by one line to be taken as a read enable signal, reading a start mark K code of the line signal and an end mark K code of the line signal, wherein the image signal data adopts a D code;
under the trigger of a synchronous signal, if image signal data are sent at the rising edge moment of the synchronous signal, pulling down a read enabling signal, and after inserting two first filling K codes into SERDES serial data corresponding to the rising edge moment, pulling up the read enabling signal to continuously send the image signal data;
if the image signal data is not sent at the rising edge moment of the synchronous signal, replacing two second filling K codes of SERDES serial data corresponding to the rising edge moment with the two first filling K codes;
the receiving end is used for:
when two continuous start mark K codes are received, a write enable signal is pulled up, the image signal data is written into a second line of data cache, until two continuous first filling K codes are received in the process of writing into the second line of data cache, the write enable signal is pulled up after two clocks are pulled down, the image signal data is continuously written into the second line of data cache, and until two continuous end mark K codes are received, the write enable signal is pulled down;
when two continuous first filling K codes are received, the clock of the synchronous signal corresponding to the first filling K codes is pulled high;
and analyzing the image time sequence information of the image signal data, determining a data effective signal, taking the data effective signal as a read enable signal of the second line data cache, and reading the image signal data from the second line data cache for image display.
8. A splicing wall signal synchronous display device is characterized by comprising a processor and a memory:
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is used for executing the spliced wall signal synchronous display method of any one of claims 1-4 according to instructions in the program code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911055724.5A CN110677553B (en) | 2019-10-31 | 2019-10-31 | Method, device, system and equipment for synchronously displaying signals of splicing wall |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911055724.5A CN110677553B (en) | 2019-10-31 | 2019-10-31 | Method, device, system and equipment for synchronously displaying signals of splicing wall |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110677553A CN110677553A (en) | 2020-01-10 |
| CN110677553B true CN110677553B (en) | 2020-11-24 |
Family
ID=69085497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911055724.5A Active CN110677553B (en) | 2019-10-31 | 2019-10-31 | Method, device, system and equipment for synchronously displaying signals of splicing wall |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110677553B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005156731A (en) * | 2003-11-21 | 2005-06-16 | Fujitsu General Ltd | Signal processor |
| CN101000755A (en) * | 2006-12-21 | 2007-07-18 | 康佳集团股份有限公司 | Multi-screen display splicing controller |
| CN201523431U (en) * | 2009-09-03 | 2010-07-07 | 中国电子科技集团公司第四十一研究所 | Video montaging device |
| CN102226943A (en) * | 2011-04-29 | 2011-10-26 | 杭州海康威视数字技术股份有限公司 | System and method for realizing screen splicing |
| CN103838533A (en) * | 2012-11-21 | 2014-06-04 | 北京同步科技有限公司 | Synchronization method for graph signals in tiled display system of computer cluster and synchronization card |
| CN104216671A (en) * | 2014-08-19 | 2014-12-17 | 宁波Gqy视讯股份有限公司 | Method for realizing synchronous cooperated display on multiple sets of spliced display screens |
| CN105489155A (en) * | 2015-12-30 | 2016-04-13 | 广东威创视讯科技股份有限公司 | Master control board of display unit of joint wall, display system of joint wall, and window opening method |
| CN106161871A (en) * | 2016-07-28 | 2016-11-23 | 深圳市昊源科技有限公司 | Synchronizing signal processing method and processing device |
-
2019
- 2019-10-31 CN CN201911055724.5A patent/CN110677553B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005156731A (en) * | 2003-11-21 | 2005-06-16 | Fujitsu General Ltd | Signal processor |
| CN101000755A (en) * | 2006-12-21 | 2007-07-18 | 康佳集团股份有限公司 | Multi-screen display splicing controller |
| CN201523431U (en) * | 2009-09-03 | 2010-07-07 | 中国电子科技集团公司第四十一研究所 | Video montaging device |
| CN102226943A (en) * | 2011-04-29 | 2011-10-26 | 杭州海康威视数字技术股份有限公司 | System and method for realizing screen splicing |
| CN103838533A (en) * | 2012-11-21 | 2014-06-04 | 北京同步科技有限公司 | Synchronization method for graph signals in tiled display system of computer cluster and synchronization card |
| CN104216671A (en) * | 2014-08-19 | 2014-12-17 | 宁波Gqy视讯股份有限公司 | Method for realizing synchronous cooperated display on multiple sets of spliced display screens |
| CN105489155A (en) * | 2015-12-30 | 2016-04-13 | 广东威创视讯科技股份有限公司 | Master control board of display unit of joint wall, display system of joint wall, and window opening method |
| CN106161871A (en) * | 2016-07-28 | 2016-11-23 | 深圳市昊源科技有限公司 | Synchronizing signal processing method and processing device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110677553A (en) | 2020-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DK2911381T3 (en) | METHOD AND DEVICE FOR PROCESSING A VIDEO PICTURE | |
| US7555693B2 (en) | Auxiliary data transmitted within a display's serialized data stream | |
| KR102344545B1 (en) | Image processing apparatus and control method thereof | |
| US10185621B2 (en) | Method and apparatus for providing a display stream embedded with non-display data | |
| CN108965819B (en) | Synchronous signal processing method and device and video transmission system | |
| CN102256092B (en) | Data send and data receiver, data send and data method of reseptance | |
| CN113271392B (en) | Video image synchronous processing method, device, system and storage medium | |
| US11587274B2 (en) | Time code display system and method, displaying device, storage medium and electronic apparatus | |
| CN110677553B (en) | Method, device, system and equipment for synchronously displaying signals of splicing wall | |
| CN103024453A (en) | Method and device for synchronously playing stitched video in indirectly acquired video application occasion | |
| KR101770938B1 (en) | Transmission device, reception device, and transmission/reception system | |
| EP3716260A1 (en) | Receiving circuit and signal processing method for high definition multimedia interface | |
| CN113206957B (en) | Image processing method and system for endoscope and storage medium | |
| CN114153414A (en) | Image anti-tearing method and related device | |
| CN112995559B (en) | Video processing method, device and system, display controller and display control system | |
| JP4781688B2 (en) | Video signal transmission method and video signal transmission apparatus | |
| JPWO2010097876A1 (en) | Serial data transmission / reception device and digital camera | |
| CN111133741B (en) | Video signal synchronization method, device and system for splicing wall | |
| US11841740B2 (en) | DP-out adapter and associated control method | |
| JP5551998B2 (en) | Image signal generator | |
| US20220165237A1 (en) | Image output device and image output method | |
| CN114390238A (en) | Data conversion device and high-definition multimedia interface receiving device | |
| KR100740688B1 (en) | Circuit and Method for Decoding Color Code of a 3D display | |
| CN116260921A (en) | Video signal switching method and device, electronic equipment and storage medium | |
| CN117499680A (en) | Video stream compression synchronous control circuit, method and equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |