CN107277373A - A kind of hardware circuit of high speed real time image processing system - Google Patents
A kind of hardware circuit of high speed real time image processing system Download PDFInfo
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- CN107277373A CN107277373A CN201710628070.5A CN201710628070A CN107277373A CN 107277373 A CN107277373 A CN 107277373A CN 201710628070 A CN201710628070 A CN 201710628070A CN 107277373 A CN107277373 A CN 107277373A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
Abstract
The invention discloses a kind of high speed real time image processing system, wherein, including：Master control process circuit, image decoding circuit, data storage circuitry, simulative display circuit and serial communication circuit；Wherein master control process circuit includes：Using FPGA and two DSP, FPGA is used to coordinate each circuit work of control and the pretreatment of view data, and two DSP are used for operation image algorithm；Image decoding circuit, for the image information of external camera to be decoded, and is sent to FPGA；Data storage circuitry, the data storage for carrying out FPGA11 and two DSP；Simulative display circuit, for by FPGA vision signal output display；Serial communication circuit, serial communication is carried out for FPGA with outside；Wherein, FPGA11 receives view data after activation video camera, and the FPGA storage for controlling arbitration to set image decoding data has limit priority, to ensure to be unable to frame losing；The interface of dsp chip is set to the second priority, and simulative display circuit is set to third priority；When the gap in the ranks and frame gap that are stored in image, the read data request of response second and third priority.
Description
Technical field
The present invention relates to a kind of high speed real time image processing system circuit, be based on Camera Link interfaces and two CSTR+
The high frame frequency image processing circuit of FPGA architecture.
Background technology
In the war of modernization, image processing techniques greatly improves military engagement ability, to object identification, mesh
Demarcation position, real-time tracking, quick destruction and landform detecting, information play very important effect in terms of obtaining.With
The rapid advances maked rapid progress with information technology of science and technology, requirement of the people to the speed and quality of image procossing is carried further
It is high.Industrial digital camera using CCD device as sensor devices is quickly grown, and CCD device is regarded towards high frame frequency is wide at this stage
The direction at angle is developed, the result is that the continuous lifting of data volume, is embodied in the lifting of image pixel and the increase of frame frequency, one
The pixel of two field picture develops into several ten million by hundreds of thousands, the lifting that the frame frequency of image is also measured, and is developed into by tens frames
Hundred frames, in addition the thousands of frames of hundreds of frames rank.In many camera interface agreements, Camera Link interfaces are because operating efficiency is high, association
Assess a bid for tender remote, the with low cost advantage of accurate simple, superior performance, communication distance, have in New Image processing system very wide
General development space.At present, the image processing circuit of conventional Camera Link interfaces can not meet wanting for high speed processing
Ask.
The content of the invention
It is an object of the invention to provide a kind of high speed real time image processing system, for solving asking for above-mentioned prior art
Topic.
A kind of high speed real time image processing system of the present invention, it is characterised in that including：Master control process circuit, image decoding
Circuit, data storage circuitry, simulative display circuit and serial communication circuit；Wherein master control process circuit includes：Using FPGA
It is used to coordinate each circuit work of control and the pretreatment of view data with two DSP, FPGA, two DSP are used for operation image algorithm；Figure
As decoding circuit, for the image information of external camera to be decoded, and FPGA is sent to；Data storage circuitry, is used for
Carry out FPGA and two DSP data storage；Simulative display circuit, for by FPGA vision signal output display；Serial communication
Circuit, serial communication is carried out for FPGA with outside；Wherein, FPGA receives view data after activation video camera, FPGA's
The storage that control arbitration sets image decoding data has limit priority, to ensure to be unable to frame losing；The interface of dsp chip is put
For the second priority, simulative display circuit is set to third priority；When the gap in the ranks and frame gap that are stored in image, response second
With the read data request of third priority.
According to an embodiment of the high speed real time image processing system of the present invention, wherein, data storage circuitry includes：Four
DDR3 chips and two DDR2 chips；Four DDR3 chips are connected with FPGA, and decoded all two field picture numbers are stored respectively
According to the data in two DDR3 chips of each of which group are respectively supplied to a DSP and VGA simulative display and used again；Other two
DDR2 chips are articulated on two DSP respectively, register map picture when making Tracking Recognition algorithm for dsp chip.
According to an embodiment of the high speed real time image processing system of the present invention, wherein, image decoding circuit is using 5 figures
As decoding chip collocation electric capacity blocking filtering and resistance, video decoding chip group is constituted.
According to an embodiment of the high speed real time image processing system of the present invention, wherein, simulative display circuit turns including DA
Parallel operation and peripheral capacitance resistance.
According to an embodiment of the high speed real time image processing system of the present invention, wherein, the signal of video camera includes：Image
Data-signal, camera control signal, serial communication signal and power supply signal.
According to an embodiment of the high speed real time image processing system of the present invention, wherein, FPGA is carried to simulative display circuit
For the R of 10, G, B component data signal and blanking signal, the tristimulus signals of simulation are converted into, pass through D-Sub cable connections
Onto the interface of VGA displays；And line synchronising signal and field sync signal by FPGA produce after be directly accessed D-Sub cables, mould
Intend row field synchronization and blanking signal that display circuit produces sequential coupling.
According to an embodiment of the high speed real time image processing system of the present invention, wherein, serial communication circuit is comprising a piece of
Electrical level transferring chip and a RS62 driving chip, RS62 driving chips are used to Transistor-Transistor Logic level being converted to RS62 level, and level turns
Change the level conversion that chip is used between FPGA and RS62 driving chips.
According to an embodiment of the high speed real time image processing system of the present invention, wherein, FPGA model
XC6VLX130T-2FFG1156；DSP model TMS320C6455.
According to an embodiment of the high speed real time image processing system of the present invention, wherein, image decoding circuit includes 5 solutions
Code chip, 3 Camera Link interfaces LVDS to CMOS/TTL conversion chips, 1 COMS/TTL to LVDS conversion chips will be controlled
Signal processed is converted to LVDS signals, 1 include COMS/TTL to LVDS and LVDS to COMS/TTL bi-directional conversion chip.
According to an embodiment of the high speed real time image processing system of the present invention, wherein, analog video display circuit is selected
D/A converter model ADV7123JST chips.
In high speed real time image processing system of the present invention, FPGA is that more extensive programmable logic device is applied in ASIC
Part, the processing of its abundant resource and outstanding parallel processing capability to a large amount of high-speed data signals is more advantageous, and DSP is good at
The complicated algorithm of processing structure, and have the advantages that arithmetic speed is fast, addressing system is flexible and communication performance is powerful, can be light
Handle high speed signal.
Brief description of the drawings
Fig. 1 show a kind of module map of high speed real time image processing system of the invention；
Fig. 2 show a kind of hardware circuit schematic diagram of high speed real time image processing system；
Fig. 3 show FPGA data flow control and arbitral procedure control flow chart；
Image decoding circuit schematic diagram shown in Fig. 4；
Fig. 5 show data caching circuit schematic diagram；
Fig. 6 show simulative display circuit diagram；
Fig. 7 show serial communication circuit schematic diagram.
Embodiment
To make the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to the present invention's
Embodiment is described in further detail.
Fig. 1 show a kind of module map of high speed real time image processing system of the invention, and it is real-time that Fig. 2 show a kind of high speed
The hardware circuit schematic diagram of image processing system, high speed real time image processing system includes：Master control process circuit 1, image decoding
Circuit 2, data storage circuitry 3, simulative display circuit 4 and serial communication circuit 5.Wherein master control process circuit 1 is used
The mode of the two CSTRs 12 and 13 of FPGA11 two is realized.Image decoding circuit 2 using 5 special image decoding chips collocation electric capacity every
Straight filtering, resistance termination, composition video decoding chip group 21, and coordinate Camera-link video cameras 7 to work.Data storage electricity
Realized using two groups of four DDR3 chips 31, and two DDR2 chips 32 and 33 on road 3；Simulative display circuit 4 is changed using DA
Device 41 coordinates peripheral capacitance resistance to realize.
As shown in Figure 1 and Figure 2, the FPGA11 of master control process circuit 1 makees main control chip, is responsible for coordinating each circuit work of control
Make and view data pretreatment, DSP12 and 13 decides process chip, is responsible for operation image algorithm.
Fig. 3 show FPGA data flow control and arbitral procedure control flow chart, as shown in Figure 1 to Figure 3, to meet video
The requirement of real-time, FPGA11 above all completes control and arbitration to high frame frequency data flow.FPGA11 is in activation
Great amount of images data will be received after Camera link video cameras, on the one hand, FPGA11 needs to integrate decoding data, extracts
View data and control information, and picture frame ranks pixel is write into DDR3 chips 31 in time, on the other hand, DSP Processor
12 and 13 need to read each frame image data in real time, and D/A converter 41 needs the video frequency output for completing to specify frame frequency, so
FPGA11 is respectively completed task of effective image data are read from DDR3 chips 31 again, so controls of the FPGA11 to data flow
System is extremely important with arbitrating.Because of demand of each interface to view data, FPGA11 control arbitral procedure is set to DDR3
The priority of the operation of chip 31, the storage of setting image decoding data has limit priority, to ensure to be unable to frame losing；DSP
The interface of chip 12 and 13 does recognition and tracking algorithm computing because needing, can not frame losing thus be set to the second priority, D/A converter
41 corresponding VGA displays are because of 6 controllable display frame frequencies (current setting shows 60 frame per second, far below 500 frames of camera), number
It is controllable and smaller according to measuring, therefore it is set to third priority.Video decoding chip group 21 parse data while can produce frame number and
Line number, in this, as the reference of storage address, according to the sequential of image decoding, DDR3 chips 31 are stored in by view data is about to.
When gap in the ranks only in storage, frame gap, arbitral procedure can just respond the read data request of second and third priority.It is i.e. sharp
Exchange the complete realization of multiple interface live video stream processing functions for the zero access speed advantage of DDR3 chips 31.
Image decoding circuit schematic diagram shown in Fig. 4, as shown in figure 4, the signal of Camera Link video cameras 7 is broadly divided into：
Viewdata signal, camera control signal, serial communication signal and power supply signal, correspond to the work(that its hardware interface circuit is realized
Can be：1) video decoding chip group 21 is carried out, the conversion of LVDS signals to CMOS/TTL signals；2) controls of the FPGA11 to phase generator terminal
System；3) FPGA11 carries out asynchronous serial communication with Camera Link video cameras 7.Therefore can be 21 strokes by video decoding chip group
It is divided into 3 parts：Data receiver circuit, control signal circuit and serial communication circuit.The standard of Camera Link video cameras 7
Signal needs to use after parsing by decoding circuit, and the signal that Camera Link video cameras 7 are provided is entirely difference
Signal.One, two, three decodings of the differential pair signal that the interface of Camera Link video cameras 7 is come in Jing Guo video decoding chip group 21
After be transformed into 3.3V single ended digital signals, then as needed for electrical level transferring chip 23 by 3.3V signal conversion costs FPGA11 I/O port
2.5V signals.Wherein video decoding chip group 21 1, two, three decodes the data-signal of Camera Link video cameras 7 respectively, control
Signal and serial communication signal processed.In addition, the pcb bus of the LVDS signals of Camera Link video cameras 7 is to ensure that difference hinders
Anti- 100 Ω, and 100 Ω build-out resistor is connect to reduce signal reflex in FPGA11 receiving terminal pin, it is ensured that signal integrity,
Even electric capacity need to be moved back for the addition of video decoding chip group 21 in addition, to reduce noise, improve signal quality.
Fig. 5 show data caching circuit schematic diagram, as shown in Figure 1, Figure 2 and shown in Fig. 5, and data caching circuit is altogether by 4 groups
DDR is constituted, wherein two groups of DDR3 chips 31 are connected with FPGA11, decoded all frame image datas is stored respectively, wherein often
Data in one group of DDR3 chip 31 are respectively supplied to a DSP12 again or 13 and VGA simulative displays are used；Other two groups of DDR2
Chip 32 and 33 are articulated on dsp chip 12 or 13 respectively, register map picture when making Tracking Recognition algorithm for dsp chip 12 or 13
With.
Fig. 6 show simulative display circuit diagram, as shown in Figure 1, Figure 2 and shown in Fig. 6, and simulative display circuit 4 is turned by DA
Parallel operation 41 and level switch module 43 are constituted.USB interface is shown at least to be needed to provide five signals to VGA displays 6 in sequential,
That is three primary colour signals of RGB and row, field sync signal.In design, FPGA11 provides 10 R, G, B to D/A converter 41
Component digital signals and blanking signal, are converted into the tristimulus signals of simulation, and the signal needs to arrive by D-Sub cable connections
On the interface of VGA displays 6；And line synchronising signal and field sync signal (data signal) directly connect after being produced by FPGA11
Enter D-Sub cables, therefore to produce in D/A converter 41 the row field synchronization and blanking signal of sequential coupling.In circuit design
In should be noted following problem：The reference amplifier that COMP signals are used for D/A converter 41 is compensated, and should pass through 0.1 μ F's
The pin of D/A converter 41 is connected on its analog power by ceramic condenser；Voltage Reference output pin during Vref, should pass through one
The pin is connected on analog power by 0.1 μ F ceramic condenser；Rset pins are used for controlling the full amplitude of vision signal, Ke Yi
Be connected to simulation ground terminal through a 560 Ω resistance or adjustable rheostat on the pin, if connect on the pin be can modulation
Hinder device, power-up test before should line measure Rset resistance to earth value, the value can not be too small；For improve picture quality, it is necessary to
Connect 75 Ω terminating resistor respectively at IOR, IOG, IOB output pin, and off-chip piece is as near as possible, it is anti-to reduce
Penetrate.In addition, D/A converter 41 belongs to analog device, power supply and earth signal should all be differentiated with numerical portion.3.3VA analog voltage
It can be obtained by adding magnetic bead on PCB 3.3V, simulation earth signal is also same processing method, while in order to be done
Net analog power, it should add decoupling capacitance between the power end and simulation ground of D/A converter 41.
Fig. 7 show serial communication circuit schematic diagram, as shown in fig. 7, serial communication circuit includes a piece of level conversion core
Piece 53 and a RS62 driving chip 51.RS62 driving chips 51 can be converted to Transistor-Transistor Logic level RS62 level, its operating voltage
It is 3.3V, so needing addition electrical level transferring chip 55 to connect FPGA11 communication.
As shown in Figure 1 and Figure 2, for an embodiment, in master control process circuit 1, FPGA11 is using Xilinx companies
XC6VLX130T-2FFG1156.Using the video write is decoded, VGA is shown and DDR3 IP kernel is controlled inside FPGA11；
DSP12 and 13 has selected the high-performance processor TMS320C6455 that TI companies release, and kernel crest frequency is up to 1.0GHz, peak
Value disposal ability is 8000MIPS, and possesses high-speed communication interface SRIO and can meet the real-time reading of view data.
As shown in Figure 1, Figure 2 and shown in Fig. 4, for an embodiment, the normal work of image decoding circuit 2 is in FULL patterns, together
When compatibility BASE patterns, it is therefore desirable to 3 kinds of decoding chips amount to 5：3 Camera Link interfaces LVDS to CMOS/TTL turn
Chip is changed, control signal is converted to LVDS signals by 1 COMS/TTL to LVDS conversion chips, and 1 includes COMS/TTL extremely
LVDS and LVDS to COMS/TTL bi-directional conversion chip.According to the recommendation of Camera Link interface standards, three kinds of chip difference
DS90CR288A, DS90LV047 and FIN1019 chip are selected, wherein DS90CR288A realizes that LVDS signals are changed, and speed can be with
Reach 85MHz.It is 3.3V interface levels additionally, due to Camera Link conversion chips, and the V6FPGA11 highests in embodiment
Support 2.5V interface levels, therefore the addition TI companies between Camera Link video cameras 7 and FPGA11 I/O pin
SN74ALVC16645 chips realize the level conversion between 2.5V and 3.3V.The LVDS signals of Camera Link video cameras 7
Pcb bus is to ensure that the Ω of differential impedance 100, and terminates 100 Ω build-out resistor to reduce signal reflex in receiving terminal, it is ensured that
Signal integrity, needs to move back even electric capacity for the addition of DS90CR288A chips in addition, to reduce noise, improves signal quality.By upper
State the signal that circuit parses and be divided into three kinds, be viewdata signal, camera control signal and serial communication signal respectively.Image
Data-signal be divided into frame useful signal FVAL, row useful signal LVAL, data valid signal DVAL, stick signal sum it is believed that
Number.Data-signal can have different passages point according to the difference (Base, Medium, Full Three models) of camera mode of operation
Method of completing the square.Under Base patterns, data-signal is only taken up under tri- passages of A, B, C, Medium patterns, and data-signal takes A~F six
Under individual passage, Full patterns, data-signal takes eight passages of A~H.
As shown in Figure 1 and Figure 2, data storage circuitry 3 selects DDR particle chips, and plug-in two groups of wherein FPGA11 is independent
DDR3 chips 31, every group using two panels magnesium light company produce 16 storage bit wide 4Gb capacity MT41K256M16HA-
125IT chips, constitute 32bits, design work speed is up to 1066MHz, and theoretical readwrite bandwidth is per second up to 4.16GB, completely
The read-write requirement of high frame frequency image can be met.MIG IP kernels have been used in FPGA11 as DDR3 controllers.In order to as far as possible
Increase the memory capacity of DSP12 and 13 plug-in memory, it is necessary to the addressability of DDR2 controllers is made full use of, so system
Design be mount 512MB, 32bit data width DDR2-SDRAM, using two panels 16bit chip cascade enter line position expand
Exhibition, the memory capacity of every is 256MB.The data wire of two panels DDR2 chips 32 and 33 is respectively coupled to DSP12 and 13 DDR2 controls
High 16 of device processed and low 16, LDM and UDM are respectively coupled to DSDDQM [1:0] and DSDDQM [3:2], LDQS/LDQS# and
UDQS/UDQS# is respectively coupled to DSDDQS [1:0]/DSDDQS#[1:0] and DSDDQS [3:2]/DSDDQS#[3:2].Other controls
Line two panels DDR2SDRAM is shared.DSP12 and 13 is internally integrated DDR2 controllers, writes after the good DDR controller of code configuration, just
DDR2 chips can normally be accessed.
As shown in Figure 1, Figure 2 and shown in Fig. 6, that analog video display circuit 4 is selected is the ADV7123JST of AD companies of the U.S.
Chip, as audio D/A converter 41, the chip is a high-speed A/D converter part, with the separate height in 10, three tunnel
Fast digital-to-analogue conversion input port, is R [0~9], G [0~9], B [0~9] respectively, and can realize complementary output.Single supply can
Choosing+5V or+3.3V powers, and is powered to reduce in power consumption, system using+3.3V analog voltages.Due to foregoing selected Camera
The pixel that Link video cameras 7 are exported is 10, can just meet the input of 3 10 pixels in tunnel of ADV7123 chips.Reset is drawn
Pin controls the size of full scale vision signal with being connected to by a resistance, when nominal image level two terminates 75 Ω loads
When, Rset=560 Ω.Corresponding USB interface uses the pin D-Sub of standard 15 definition.
As shown in Figure 1, Figure 2 and shown in Fig. 7, serial communication circuit 5 is using driving chip of the MAX3490 chips as RS62
The SN74ALVC16645 chips of 51, TI companies as 3.3v and 2.5v electrical level transferring chip 53.
A kind of scan picture circuit of high frame frequency of the present invention, camera frame frequency is per second up to 500 frames, image pixel
1280x1024, pixel depth 10bits, actual bandwidth 781.25MB/s, process circuit will be known to each two field picture
Tracking is not handled, result can be immediately sent to external system devices and can display image and tracked information in real time VGA
On display, VGA output pixels 1280x1024,60 frames are per second.Using high frame frequency industrial camera, vision bandwidth 781.25MB/s,
Multigroup DDR caching image datas, FPGA adds two CSTR to carry out image procossing, and VGA displays show the image of cameras capture in real time,
And the tracked information of target object is superimposed in real time, breach rate limit.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these improve and deformed
Also it should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of high speed real time image processing system, it is characterised in that including：Master control process circuit, image decoding circuit, data
Storage circuit, simulative display circuit and serial communication circuit；
Wherein master control process circuit includes：Using FPGA and two DSP, FPGA is used to coordinate each circuit work of control and view data
Pretreatment, two DSP be used for operation image algorithm；
Image decoding circuit, for the image information of external camera to be decoded, and is sent to FPGA；
Data storage circuitry, the data storage for carrying out FPGA and two DSP；
Simulative display circuit, for by FPGA vision signal output display；
Serial communication circuit, serial communication is carried out for FPGA with outside；
Wherein, FPGA receives view data after activation video camera, and FPGA control arbitration sets image decoding data
Storage has limit priority, to ensure to be unable to frame losing；The interface of dsp chip is set to the second priority, and simulative display circuit is set
For third priority；When the gap in the ranks and frame gap that are stored in image, the read data request of response second and third priority.
2. high speed real time image processing system as claimed in claim 1, it is characterised in that data storage circuitry includes：Four
DDR3 chips and two DDR2 chips；Four DDR3 chips are connected with FPGA, and decoded all two field picture numbers are stored respectively
According to the data in two DDR3 chips of each of which group are respectively supplied to a DSP and VGA simulative display and used again；Other two
DDR2 chips are articulated on two DSP respectively, register map picture when making Tracking Recognition algorithm for dsp chip.
3. high speed real time image processing system as claimed in claim 1, it is characterised in that image decoding circuit is using 5 figures
As decoding chip collocation electric capacity blocking filtering and resistance, video decoding chip group is constituted.
4. high speed real time image processing system as claimed in claim 1, it is characterised in that simulative display circuit is changed including DA
Device and peripheral capacitance resistance.
5. high speed real time image processing system as claimed in claim 1, it is characterised in that the signal of video camera includes：Image
Data-signal, camera control signal, serial communication signal and power supply signal.
6. high speed real time image processing system as claimed in claim 1, it is characterised in that FPGA is provided to simulative display circuit
R, G, B component data signal and the blanking signal of 10, is converted into the tristimulus signals of simulation, is arrived by D-Sub cable connections
On the interface of VGA displays；And line synchronising signal and field sync signal by FPGA produce after be directly accessed D-Sub cables, simulate
Display circuit produces the row field synchronization and blanking signal of sequential coupling.
7. high speed real time image processing system as claimed in claim 1, it is characterised in that serial communication circuit includes a piece of electricity
Flat conversion chip and a RS62 driving chip, RS62 driving chips are used to Transistor-Transistor Logic level being converted to RS62 level, level conversion
The level conversion that chip is used between FPGA and RS62 driving chips.
8. high speed real time image processing system as claimed in claim 1, it is characterised in that FPGA model
XC6VLX130T-2FFG1156；DSP model TMS320C6455.
9. high speed real time image processing system as claimed in claim 1, it is characterised in that image decoding circuit includes 5 solutions
Code chip, 3 Camera Link interfaces LVDS to CMOS/TTL conversion chips, 1 COMS/TTL to LVDS conversion chips will be controlled
Signal processed is converted to LVDS signals, 1 include COMS/TTL to LVDS and LVDS to COMS/TTL bi-directional conversion chip.
10. high speed real time image processing system as claimed in claim 4, it is characterised in that analog video display circuit is selected
D/A converter model ADV7123JST chips.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108763144A (en) * | 2018-03-30 | 2018-11-06 | 北京计算机技术及应用研究所 | A kind of SIP encapsulated circuits of integrated four core DSP and 1553B bus control units |
| CN109215565A (en) * | 2018-09-21 | 2019-01-15 | 华中科技大学 | A kind of reception card, data storage dispatching method and LED display control program |
| CN111698387A (en) * | 2020-06-19 | 2020-09-22 | 西安微电子技术研究所 | LVDS-to-VGA display signal conversion module and working method |
| CN114968870A (en) * | 2022-04-25 | 2022-08-30 | 江苏集萃清联智控科技有限公司 | Navigation information processor and method thereof |
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