CN103826072B - A kind of Minitype infrared imaging system - Google Patents

Abstract

The invention discloses a kind of Minitype infrared imaging system, the system converges to the infra-red radiation that target object is sent on infrared focal plane array using the infrared lens for being operated in specific band, focal plane arrays (FPA) produces response signal to infra-red radiation, reading circuit is output to response signal on signal-processing board, signal-processing board carries out a series of signal processing to it, is finally synthesizing and is sent to display screen for video standard signal and shows.The system can be perceived to the infra-red radiation that target is sent, gather, handle, showing and can realize store function in real time.In terms of signal transacting, the present invention proposes the method that the infrared image that a kind of new Space-time domain combines filters noise reduction, meanwhile, system of the invention has the advantages of low in energy consumption, small volume, in light weight, cost is low, reliability is high.Based on above-mentioned advantage, the present invention has broad prospects in the application of military field, commercial field and industrial circle.

Description

A kind of Minitype infrared imaging system

Technical field

The invention belongs to infrared image field, and in particular to FPGA（Field Programmble Gate Array, scene Programmable gate array）Technology, hardware description language（Verilog language）, SOPC technologies, Digital Image Processing and VGA show Technology.In particular, provide a kind of system and method for being suitable for the shooting of moving target real-time Infrared video.

Background technology

With the progress of science and the development of technology, infrared imagery technique be widely used in military, industry, business, medical treatment, The every field such as forest fire protection, environmental protection.It is still industrially, and in scientific research, infrared either in national defence Imaging technique is related in the field of national economy at these to be suffered from extremely being widely applied, and plays a part of can not be ignored. It may be said that infrared imagery technique is one of key technology for weighing a national military strength.

Infrared imagery technique is the technology that an emerging infrared signal after World War II is changed and is acted upon, The transmitting of main research infrared energy, transmission, the rule and its implementation process received.All temperature of nature are higher than absolute zero The object for spending (- 273.15 DEG C) can be to heat radiation around, and this is due to that object in the Nature is all and the thing by molecular composition The charged particle in internal portion is all ceaselessly to move, and interparticle relative motion will produce heat energy, and infra-red radiation belongs to heat A part for radiation, the heat radiation Main Ingredients and Appearance that the object in normal temperature is sent is exactly infra-red radiation.Infra-red radiation is that one kind can not See light, it is adjacent with visible wavelength.Wherein, it is seen that between 0.38~0.76um, the wavelength of infrared ray exists the wavelength of light Between 0.76~1000um.The radiation temperature of object is directly proportional to intensity and spectral component that infra-red radiation is sent, it is clear that target The intensity of the temperature of object more high infrared radiation is bigger, and the intensity of temperature Low emissivity is with regard to low.Non refrigerating infrared imaging instrument is general It is operated in 8~14um wave bands.

Most of high-precision infrared imaging devices are all to use FPGA+DSP frameworks in the market, and wherein DSP relies on it Powerful operational capability mainly realizes data operation, data communication and data management function；And FPGA has flexible online volume Cheng Nengli, mainly realizes the fixed signal transacting such as nonuniformity correction, blind element compensation, Video Composition and SECO function, two The real-time processing to infrared image is completed in person's mutual cooperation.However, in such systems, based on the time-multiplexed DSP of bus and FPGA needs control of the frequent switching to memory, and this will necessarily reduce the data transmission efficiency of whole system, increases system The complexity of logic control, design and the application of nonsystematic bring inconvenience.Importantly, using DSP+FPGA frameworks Circuit volume is larger, it is difficult to the requirement of adaptive system miniaturization.

The present invention proposes a kind of SOPC technologies based on FPGA, using programmable system on piece, realizes miniaturization low-power consumption Requirement.Nowadays, embedded system develops towards higher performance, smaller volume, more low-power consumption, more cheap direction, and is embedded in The design and exploitation of formula system are then towards based on chip, particularly system-level programmable chip（SOPC）Direction develop.Simultaneously In order to reduce development difficulty, designed frequently with fusion microprocessor technology, Digital Signal Processing, system-level programmable chip With Hardware/Software Collaborative Design in one the design method based on embedded intelligent platform, to improve the development efficiency of system, Shorten the cycle that product enters market.With the progress of VLSI Design technology and the raising of manufacturing technology level, And the increase of On-chip logic door number, Embedded System Design is increasingly sophisticated, on one single chip the increase of logic gate number make While design objective becomes complexity, also develop design for designer and open new world, whole system can be integrated into On one chip, i.e., so-called system-on-chip technology（SOC）, SOC is the inexorable trend of integrated circuit development.

The content of the invention

Present invention aims at providing a kind of small low-consumption low cost infrared imaging system, compared to it is traditional it is infrared into As system, there is the characteristics such as low cost, low-power consumption, miniaturization, reliability height, while the system is suitable to modularized design, upgrading Property it is good, be easy to safeguard, reliability is high, and transplanting is convenient.

To reach above-mentioned purpose, the present invention uses following technical proposals：

The small low-consumption low cost infrared imaging system of the present invention includes power circuit block, analog voltage collection mould Block, FPGA image procossings and modular converter, vision signal synthesis module, infrared lens, Uncooled FPA, liquid crystal display Module and SDRAM, serial FLASH module.The FPGA is using the cost-effective Cyclone II series of altera corp EP2C5Q208C8 model chips, the caching of video data, serial FLASH are carried out using 1M × 4Banks × 16Bits SDRAM To realize the solidification of FPGA programs, plate level on-line debugging is realized using jtag interface, Video Decoder is by infrared focal plane array The analog video signal of output is converted into the digital video signal of ITU-BT.656 forms, delivers in FPGA and is deinterleaved, goes here and there And change, the operation such as color notation conversion space, image procossing, vision signal is stored in SDRAM by fifo buffer, has deposited one Two field picture is read vision signal from SDRAM by FIFO and delivers in video encoder the synthesis for carrying out video standard signal again, Video encoder under the control of FPGA output display clocks, and constructed in FPGA video display module control under line by line Effective infrared video is shown column by column.

Above-mentioned memory module uses the SDRAM chips of 1M × 4Banks × 16Bits sizes, the space point of total 64M sizes For 4 Bank, each Bank is the space of 1M sizes, it is necessary to which 12 address wires, it is 16 digital video data to be communicated with FPGA, is taken Data are R [7:3]、G[7:2]、B[7:3].

Above-mentioned Video decoding module be used for receive infrared focal plane array output analog signal, target object it is infrared Radiation is received and converged on Uncooled FPA, the thermo-sensitive material sense of focal plane arrays (FPA) by infrared optical lens Answer the heat distribution field of target, and by temperature transition into voltage signal exporting and decoded to Video Decoder line by line, depending on Analog video signal is converted into the digital video signal of ITU-BT.656 forms by frequency decoder, delivers in FPGA and is handled, FPGA is configured by I2C interface to video decoding chip.

Above-mentioned series arrangement module is used for by program Solidification into fpga chip, and the FPGA used in the present invention is based on SRAM Technique, FPGA reverts to white tiles after power down, and internal logic relation is lost, it is necessary to configures a piece of special storage chip to FPGA EPCS16, program curing is stored, after electricity FPGA on, program is transferred to RAM inside FPGA from configuring in chip EPCS16 Middle operation.

Above-mentioned FPGA internal processing modules are used for handling digital video signal, and are cached by fifo buffer Into SDRAM so that follow-up real-time video is shown.In comprising the following steps that for FPGA inter-process：

Step 1：The digital video frequency flow that Video Decoder is sent is deinterleaved, by continuously judging FF, 00,00 He XY carries out F, V, H extraction and the judgement of effective video signal, so as to produce YCbCr effective video signals, identification trip, field Synchronizing signal and odd even field signal；

Step 2：By 4:2:2 serial datas are transformed into 4:4:4 parallel data, the Cb of intercalary delection, Cr values pass through interpolation Mode produce.One counter of design is selected, and is Cb when counting is 0 and 2, Cr signals, is believed when counting is 1 and 3 for Y Number, so as to complete the process that serial signal switchs to parallel signal；

Step 3：The effective YCbCr data values separated are converted into the data value of rgb format.Arrived for YCbCr RGB conversion is carried out according to below equation：

R=1.164（Y-16）+1.596（Cr-128）

G=1.164（Y-16）-0.813（Cr-128）-0.392（Cb-128）

B=1.164（Y-16）+（Cb-128）

Realized in FPGA with Verilog language, the vision signal after conversion is stored in SDRAM by fifo buffer Row caching；

Step 4：By the Infrared Video Signal after conversion, background estimating is first carried out, time-domain difference fortune then is carried out to it Calculate, to reduce video noise, then realized with time domain variance filter method and eliminate background on a large scale, it is finally strong using spatial domain edge Degree filtering carries out edge protrusion to infrared image.

Small low-consumption low cost infrared imaging system of the present invention, feature are as main process task chip using FPGA So that the system of design has the characteristics that low-power consumption, flexible design, portable height, upgradability are strong, and utilize FPGA hardware Intrinsic concurrency tables look-up system to perform the algorithm of infrared image processing with unique, realizes software algorithm Hardware, protects The requirement of system real time is demonstrate,proved.It is widely used in each necks such as military affairs, industry, business, medical treatment, forest fire protection, environmental protection Domain.

Brief description of the drawings

Fig. 1 is the hardware frame figure of the infrared video real-time acquisition and display hardware system of the present invention；

Fig. 2 is the system power supply module frame chart of the present invention；

Fig. 3 is the system video decoder module hardware frame figure of the present invention；

Fig. 4 is the FPGA minimum systematic module hardware frame figures of the present invention；

Fig. 5 is the system sdram memory module hardware frame figure of the present invention；

Fig. 6 is the system serial download configuration module hardware frame figure of the present invention；

Fig. 7 is the system video coding module hardware frame figure of the present invention；

Fig. 8 is the system video data process chart of the present invention；

Fig. 9 is the system colour space transformation flow chart of the present invention；

Figure 10 is the Infrared video image filtering noise reduction flow chart of the present invention.

Embodiment

In order to make the purpose , technical scheme and advantage of the present invention be clearer, below with reference to accompanying drawing, to the present invention A kind of small low-consumption low cost infrared imaging system be described in further detail.

Fig. 1 describes the hardware frame figure of the small low-consumption low cost infrared imaging system of the present invention.Hardware components by Power supply, video decoding, FPGA main process tasks, Video coding, SDRAM, series arrangement chip, JTAG, AS, reset circuit, clock electricity Road forms.Video decoding chip the analog voltage signal of output be converted into digital video signal be sent into FPGA in carry out it is a series of Processing, the vision signal for being finally synthesizing standard are output in display screen by USB interface.Serial FLASH is used to solidify FPGA's Program code, is power down not loss storage, and SDRAM is used for the temporary of infrared image, waits and be filled with a frame output display.Video is compiled Decoding circuit carries out the communication of digital video signal by connector of good performance with FPGA, and jtag interface is used for program generation The on-line debugging of code.Reset circuit, clock circuit, the part that power supply is FPGA minimum systems.

Fig. 2 describes the system power supply module frame chart of the present invention.The present invention considers the power supply requirement of whole logic circuit, FPGA core voltage needs 1.2V, TVP5150 to need 1.8V voltage, 3.3V provide most of circuit and FPGA on plate, TVP5150, ADV7123 IO voltages, wherein, FPGA bank1, bank2 and TVP5150 share a 3.3V, FPGA's Bank3, bank4 and ADV7123 share a 3.3V.Reason for this is that draw to reduce LDO-3.3V because electric current is excessive The heating risen.

From the 12V voltages of power supply output, by capacitor filtering, it is input in MP1591 power conversion chips, the electricity of output Pressure obtains 5V burning voltages by inductance, of the invention to use four AMS1117 chips, respectively AMS1117-3.3V, AMS1117-1.8V, AMS1117-1.2V, AMS1117-3.3V, by 5V voltage conversions it is 3.3V, 1.2V using this four chips And 1.8V, AMS1117 are a positive low dropout voltage regulators, 1.2V is reduced in 1A current downs.AMS1117 has two versions： Fixed output version and tunable versions, fixed output voltage is 1.5V, 1.8V, 2.5V, 2.85V, 3.0V, 3.3V, 5.0V, is had 1% precision；The precision that fixed output voltage is 1.2V is 2%.AMS1117 is internally integrated overtemperature protection and current-limiting circuit, is The optimal selection of battery powered and portable computer.

Fig. 3 describes the system video decoder module hardware frame figure of the present invention.TVP5150 is a super low-power consumption video Decoder, the analog voltage signal exported from Uncooled FPA is converted into carrying out in digital video signal feeding FPGA Processing.The decoder is supplied using 1.8V for its analog- and digital- power supply, and provides voltage with 3.3V for I/O mouths.FPGA passes through I2C bus configurations TVP5150 mode of operation and parameter setting, the design only use AIP1A passages, AIP1B passages are grounded, Crystal oscillator is using 14.31818MHZ without source crystal oscillator.

TVP5150 configuration is completed by I2C bus standards.I2C buses pass through serial date transfer/output line （SDA）With clock input/output line（SCL）Carry out data transmission, standard speed is 100 kbit/s, flank speed 400 kbit/s.The system, using Verilog language structure I2C bus control units, uses the kbit/s's of standard 100 inside FPGA Speed completes the configuration to TVP5150.According to I2C agreements, the sequence of operations such as generation initial conditions, addressing, write operation are carried out, The assignment to each register is respectively completed, so as to realize the configuration to TVP5150.

Fig. 4 describes the FPGA minimum systematic module hardware frame figures of the present invention.FPGA signal processing modules are with Cyclone The fpga chip EP2C5Q208C8 of II series is core, and surrounding is respectively configuration chip EPCS16 and SDRAM chip HY57V641620.Significant data and configuration information in the main storage image processing procedure of storage chip, because considering and FPGA Frequent exchange data, therefore in component placement, as long as in the case of allowing in space, close proximity to master chip, and signal Line as far as possible ensure matching and it is isometric, avoid causing signal delay in transmitting procedure.Row pin of the coding and decoding video module from side above Introduce, codec chip is individually positioned in the right and left, avoids the crosstalk between them.Power module is compiled by contact pin for video Decoder module and FPGA signal processing modules provide stable voltage.The stand of 2 double ten pins on the left side is JTAG and AS Peripheral interface, jtag interface is mainly used to realize the debugging of whole system, and AS interfaces mainly select pof texts under AS patterns Part downloads to Cyclone II chips, by program Solidification into fpga chip.

Fig. 5 describes the system sdram memory module hardware frame figure of the present invention.The design is from Hynix company HY57V641620 model chips, HY57V641620 are a kind of high-performance dynamic RAMs manufactured using CMOS technology, It is divided into 4 BANKS, each BANK is 1M × 16bits.The rising edge synch of all inputs and output and clock input.Data Inside track streamline reaches very high bandwidth, and all inputs and output-voltage levels are compatible with LVTTL.

VGA display pixel clocks involved in the present invention are 800*600@60Hz's, and transmission speed will reach 40M* 16bit.Therefore, infrared video real-time display is realized, it is necessary to the data buffer storage that will first have been handled with SDRAM, when a frame After data are all written in SDRAM, then are read in video d/a chip and shown, it is possible to see that VGA shows full picture And it is always maintained at stabilization.

Fig. 6 describes the system serial download configuration module hardware frame figure of the present invention.Most of FPGA is all based on SRAM techniques, and information will lose the chip of SRAM techniques after a power failure, so in order to complete in each system electrification Paired FPGA configuration is, it is necessary to separately add the special configuration chips of a piece of FPGA.When upper electric, FPGA by configure chip in program and Data are loaded into ram in slice, are completed with postponing, FPGA enters normal operating conditions.And after power down, the circuit inside FPGA Logical relation disappears automatically, and now FPGA reverts to the chip of sky again, and FPGA has two kinds of downloading modes, and one kind is JTAG mode, On-line debugging program is facilitated to use, another kind is series arrangement pattern i.e. AS patterns, and fpga chip power down is not save routine, When needing program Solidification into FPGA, it is necessary to using AS patterns, by the EPCS16 of program Solidification to FPGA configuration core In piece.

Fig. 7 describes the system video coding module hardware frame figure of the present invention.The system needs to build mark in FPGA Line synchronising signal H, field sync signal V required for accurate USB interface and the simulated video d/a conversion used of digital image information Device control signal.The system output be clock be 40 MHz, field frequency is 60 Hz, vaild act 600, often row effective pixel points For 800 video data, so being computed construction, often row has 1056 clocks, the picture frame period of 628 rows is shared, in this frame In cycle the line synchronising signal for meeting VGA standard is constructed using counter（H_SYNCH）, row crop signal（H_FRONT_ PORCH）, row back porch signal（H_BACK_PORCH）, field sync signal（V_SYNCH）, field crop signal（V_FRONT_ PORCH）, field back porch signal（V_BACK_PORCH）.Clock is input in pixel pulse counter of the mould equal to 1056, works as picture Plain step-by-step counting exports low level between 40~168 pulses, other output high level, in this, as line synchronising signal H_SYNCH； Then counted in units of H_SYNCH row beats, low level is exported when meter is to 1 and 5, other output high level, work as meter During to 628 line synchronising signals, counter clear 0, in this, as field sync signal V_SYNCH.Similarly built and gone on a journey with counter Crop signal（H_FRONT_PORCH）, row back porch signal（H_BACK_PORCH）, field crop signal（V_FRONT_PORCH）, field Back porch signal（V_BACK_PORCH）, the sequential and control signal that have constructed deliver to D/A turns together with the RGB data stream being converted into Change in chip ADV7123.

Fig. 8 describes the system video data process chart of the present invention.Hardware circuit is mainly used to complete adopting for data Collection and transmission work, and the processing of video data is changed, bus marco etc. is then realized by the logic circuit inside FPGA.This is Logic circuit inside the main process task chip FPGA of system mainly includes PLL phaselocked loops generation module, I2C bus configurations module, number According to collection and processing module and video display module.Wherein PLL phase-locked loop modules be SDRAM module for reading and writing, VGA display modules, FPGA processing modules provide working frequency；I2C bus configurations module provides channel selecting, address choice, right for Video Decoder Than the configuration of the registers such as degree, colourity；Data acquisition and procession module realize receive vision signal, using FIFO realize with SDRAM clock-domain crossing data transmission, and color notation conversion space etc.；The Data Synthesis that video display module will receive from FIFO Normal video, it is sent to ADV7123 chips and is handled.Modules cooperate to complete the desired function of circuit, the system The function of modules inside FPGA is realized using hardware description language Verilog.

Fig. 9 describes the system colour space transformation flow chart of the present invention.The module by three steps in FPGA it is right The data for the BT.656 forms that video decoding chip is sent enter line translation.The first step is de-interleaving block, produces YCbCr and effectively regards Frequency signal, identification trip, field sync signal.The complete ITU-R BT.656 data of one frame are divided into odd even two, often row ITU-R 288 byte that BT.656 data start are row control signal, and 4 byte of beginning are EAV（Effective video terminates）Signal, immediately 280 fixed filling data, last 4 byte is SAV（Effective video originates）Signal.SAV signals and EAV signals have 3 Byte's is leading：FF, 00,00；Last 1 byte XY are by fixed data 1, F（Parity flag position）, V（Vertical blanking mark Position）, H（Horizontal blanking mark）With by F, V, H calculate low 4 compositions of generation.By continuously judging FF, 00,00 and XY enters Row F, V, H extraction and the judgement of effective video signal, for follow-up video control, frame buffer and DAC module sequential construction Control signal is provided；Second step is serioparallel exchange, and this module is by 4:2:2 serial datas are transformed into 4:4:4 parallel data, it is middle The Cb of missing, Cr value are produced by way of interpolation.One counter of design is selected, and is Cb when counting is 0 and 2, and Cr believes Number, it is Y-signal when counting is 1 and 3, so as to complete the process that serial signal switchs to parallel signal, realizes YCbCr serial datas Separation；3rd step is color space conversion, and the module is converted into the effective YCbCr data values separated according to certain formula The data value of rgb format, to be sent to the output display that video data is carried out in DAC.

Figure 10 describes the filtering noise reduction flow chart of the Infrared video image of the present invention.The module is realized by three steps The background filtering noise reduction process of Infrared video image.The first step be to infrared image sequence carry out temporal low-pass filter, and with original Beginning infrared image sequence carries out difference, is reduced the infrared image of noise；Second step is when obtained differential signal is carried out Domain variance filter processing, the step can eliminate background on a large scale；3rd step is to carry out spatial domain to the filtered video of variance Edge strength filtering process, the gradient correlation properties of infrared image are taken full advantage of, the edge enhancing of infrared image can be realized, Projecting edge information.

Claims (7)

1. a kind of Minitype infrared imaging system,：The imaging system include power circuit block, analog voltage acquisition module, FPGA image procossings and modular converter, vision signal coding module, vision signal decoder module, infrared lens, non-brake method are burnt Planar array, LCD MODULE and SDRAM, serial FLASH module；The infra-red radiation that target object is sent passes through Propagation in atmosphere is received by infrared lens, and is converged on the un-cooled infrared focal plane array, non-refrigerating infrared focal plane battle array The input for being transformed into analog voltage signal and being output to vision signal decoder module by infra-red radiation line by line is arranged, by decoding Video Decoder in module converts thereof into digital video signal and is input to image procossing and modular converter progress in FPGA Deinterleaving, serioparallel exchange, color notation conversion space, image filtering noise reduction process, video data is then cached to outside In SDRAM, a frame is deposited and has just been output to the real-time display that video is completed in vision signal coding module；The system is according to fortune The performance of moving-target, realize that the filtering to infrared image is dropped with the image filtering method that time domain is combined using a kind of spatial domain Make an uproar processing, it is characterised in that the filtering method is：

The first step is that temporal low-pass filter is carried out to infrared image sequence, and carries out difference with original infrared image sequence, is obtained Reduce the infrared image of noise；Second step is that obtained differential signal is carried out into time domain variance filter processing, and the step can It is large-scale to eliminate background；3rd step is to carry out spatial domain edge strength filtering process to the filtered video of variance, is made full use of The gradient correlation properties of infrared image, the edge enhancing of infrared image, projecting edge information can be realized；

The data for the BT.656 forms that the FPGA image procossings are sent with modular converter to video decoding chip enter line translation Method is：The first step is de-interleaving block, produces YCbCr effective video signals, identification trip, field sync signal；One frame is complete Whole ITU-R BT.656 data are divided into odd even two, and 288 byte that often row ITU-R BT.656 data start are row Control signal, 4 byte of beginning are EAV（Effective video terminates）Signal, and then fix filling data for 280, most 4 byte are SAV afterwards（Effective video originates）Signal；SAV signals and EAV signals have that 3 byte's is leading：FF, 00,00；Last 1 byte XY are by fixed data 1, F（Parity flag position）, V（Vertical blanking flag bit）, H（It is horizontal Blanking mark）With by F, V, H calculate low 4 compositions of generation,

By continuously judging FF, 00,00 and XY carries out F, V, H extraction and the judgement of effective video signal, after being Continuous video control, frame buffer and DAC module sequential construction provides control signal；Second step is serioparallel exchange, and this module will 4:2:2 serial datas are transformed into 4:4:4 parallel data, the Cb of intercalary delection, Cr values are produced by way of interpolation,

One counter of design is selected, and is Cb when counting is 0 and 2, Cr signals, and counting is when being 1 and 3 Y signals, so as to complete the process that serial signal switchs to parallel signal, realize the separation of YCbCr serial datas；3rd step For color space conversion, the effective YCbCr data values separated are converted into RGB lattice by the module according to certain formula The data value of formula, to be sent to the output display that video data is carried out in DAC.

2. imaging system according to claim 1, it is characterised in that the imaging system uses SOPC technologies, three blocks of electricity Road flaggy stack structure design realizes the miniaturization of system；And the FPGA core voltages using 1.2V.

3. the infrared imaging system according to claim 1, it is characterised in that：Described analog voltage acquisition module, by Single 14.318MHz crystal oscillators supply, FPGA are configured by I2C buses to the internal register of Video Decoder, While completion is configured to Video Decoder, the analog voltage signal of Uncooled FPA output is sent into video decoding Decoded in device, the video data for converting thereof into ITU-R BT.656 forms is delivered in FPGA and handled.

4. the infrared imaging system according to claim 3, it is characterised in that：The configuration includes colourity, contrast, satisfied With degree information.

5. the infrared imaging system according to claim 1, it is characterised in that：Described FPGA image procossings are with turning Change the mold block, in the real-time processing to infrared image, using the intrinsic concurrency of FPGA hardware and it is unique table look-up system come The algorithm of infrared image processing is performed, software algorithm Hardware is realized, ensure that the requirement of system real time.

6. the infrared imaging system according to claim 1, it is characterised in that：Described color space conversion is to realize From the video datas of ITU-R BT.656 forms to the conversion of RGB signals, comprise the following steps that：Step 1：To video The digital video frequency flow that decoder is sent is deinterleaved, and produces YCbCr effective video signals, identification trip, field sync signal ；Step 2：By YCbCr4:2:The serial data of 2 forms is converted to YCbCr4 by way of resampling:4:4 and Row data, it is easy to the conversion of next step；Step 3：The effective YCbCr4 that will be separated:4:4 data values are converted into The data value of RGB forms.

7. the infrared imaging system according to claim 1, it is characterised in that：Video encoding module output video be The vision signal of 24 RGB colors, output display valid pixel arranges for 800,600 rows, field frequency 60Hz, with FPGA Interface is the RGB signals of 24, clock frequency 40MHz, is provided by the clock that output is synthesized inside Video Decoder, Complete the conversion that digital video flows to analog video data.