CN103595924B - A kind of image fusion system based on Cameralink and method thereof - Google Patents
A kind of image fusion system based on Cameralink and method thereof Download PDFInfo
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Abstract
The invention discloses a kind of image fusion system based on Cameralink and method thereof, including two-way Cameralink Video Reception System, FPGA, memorizer, multi-core DSP, display, two-way Cameralink Video Reception System is connected with FPGA respectively, and this FPGA is connected with memorizer, multi-core DSP, display respectively.The two-path video input that the present invention merges is Cameralink, and transmission bandwidth, up to more than Gpbs, has significant advantage in high-resolution height frame frequency image procossing；The data TTL signal sequential that Cameralink camera signal produces through Video Reception System solution difference block is simple, and there is the least phase contrast between synchronization two-path video, in FPGA, two-way image is merged realization.
Description
Technical field
The invention belongs to high-speed image sampling technical field, a kind of image fusion system based on Cameralink and method thereof.
Background technology
Image co-registration is important branch and the study hotspot of information fusion.Image co-registration is advanced image processing techniques Same Scene comprehensively being become piece image from the multiple image that different qualities, different time, different resolution sensor obtain.Image fusion technology is obtained for extensively application in many fields, including analysis and the process, automatically identification, computer vision, Medical Image Processing etc. of remote sensing images.Fusion image has stronger robustness, has a strong impact on even if fusion image also will not be produced by particular sensor fault；Image co-registration can work in coordination with the multiple sensors image information of Same Scene, exports the fusion image that a width is more suitable for human vision perception or computer processes further and analyzes.It can obviously improve the deficiency of single-sensor, improves definition and the information amount of comprising of image.The research of image fusion technology has important theory and using value.
Cameralink agreement is Dalsa, Basler, the camera suppliers such as Coreco and image acquisition company combine release in October, 2000 and are intended to simplify the connection between CCD and capture card, and Cameralink can be the connection of the digital camera offer simple and flexible of high-speed, high precision.Cameralink interface is to aim at a kind of view data, video data control signal and the EBI of camera control signal transmission that digital camera is formulated, and message transmission rate reaches as high as 2.38Gbps, is sufficient for the digital camera requirement in current transmission speed.After using this standard so that the data-interface output of digital camera uses less line number, connects cables manufacturing convenient, has more versatility, and the transmission range of data is more farther than normal transmission mode.Its topmost feature is to have employed LVDS (Low Voltage Differential Signaling, Low Voltage Differential Signal) technology, thus simplify the workflow such as number conversion, video signal coding and decoding, make the message transmission rate of video camera be greatly improved.Cameralink has Base, Medium, Full Three models, under Full pattern, can transmit 8 pixels, image resolution ratio is up to 2048*2048, and frame frequency is up to 2000 frames simultaneously, transmission bandwidth is up to 8000MB/S, and this interface can carry out the storage of data, real-time Transmission can go back to ground or connect capture card by connecting image capture device.Cameralink transfer rate is fast, volume is little, lightweight, be easy to detection and evaluate camera imaging quality increasingly come more to be widely applied in image digitization field.
The real-time implementation of image fusion technology has suitable difficulty, after blending algorithm determines, if picture resolution, number of greyscale levels, sequencing contro etc. change, the most generally, the corresponding hardware circuit in system, overall timing control signal etc. also locally or globally to adjust.I.e. it is difficult to one image fusion system of design, it is possible to meet various different picture characteristics.And for the picture signal of Cameralink transmission, it is not necessary to change circuit hardware structure, only in FPGA, instruction, i.e. adjustable picture resolution, and number of greyscale levels need to be sent to by the serial communication signal in Cameralink agreement.And through the picture signal decoded chip (DS90CR288A of Cameralink transmission, DS90LV031, DS90LV019) after decoding, for stable TTL viewdata signal, there is no the communications protocol of complexity, directly decoded TTL viewdata signal can be processed, it is easier to realize real time fusion.
The image co-registration hardware system of main flow is that two-way network interface transmission video is merged at present, network interface transmission meets GigEg Vision agreement, numerous manufacturers support, its application is widest, but bandwidth is little, can only transmit a pixel, in high-resolution, the applications of high frame frequency just can not reach requirement every time.Cameralink can transmit the image of high-resolution height frame frequency, and resolution is up to 4K*4K, and frame frequency can be with more than 2000fps, and in high-resolution, the occasion of high frame frequency provides new solution.And the image fusion system of two-way Cameralink transmission is the most difficult owing to the special requirement of differential signal realizes aspect at hardware.
Summary of the invention
It is an object of the invention to provide a kind of image fusion system based on Cameralink and method thereof, thus quickly realize the fusion of high-resolution height frame frequency image.
The technical solution realizing the object of the invention is:
nullA kind of image fusion system based on Cameralink，Including two-way Cameralink Video Reception System、FPGA、Memorizer、Multi-core DSP、Display，Two-way Cameralink Video Reception System is connected with FPGA respectively，This FPGA respectively with memorizer、Multi-core DSP、Display connects，This Cameralink Video Reception System is by two MDR26 adapters、Three solve difference block、Serial communication module、Differential driving module forms，Oneth MDR26 adapter is respectively with first、Two solve difference block connects，2nd MDR26 adapter solves difference block with the 3rd respectively、Serial communication module、Differential driving module connects，This is first years old、Two、Three solve difference block and serial communication module、Differential driving module is connected with FPGA respectively；Cameralink camera signal under two-way Full pattern is transferred in Cameralink Video Reception System, every road Full mode data differential signal solves difference block through three and is converted into data TTL signal, serial communication signal is decoded by serial communication module, control differential signal to produce through differential driving module, the data TTL signal entrance FPGA solving difference block generation merges, data exchange is carried out with memorizer during image procossing, multi-core DSP is sent into through Rapid IO after Image semantic classification, FPGA is passed back again through Rapid IO, finally the image after process is shown in VGA interface display.
A kind of image interfusion method based on Cameralink, step is as follows:
The first step, the Cameralink camera signal under two-way Full pattern according to Cameralink protocol transmission to two-way Cameralink Video Reception System；
Second step, two-way Cameralink Video Reception System will carry out fusion treatment in feeding FPGA real-time for data, every road Cameralink Video Reception System is made up of two MDR26 adapters, three solution difference block, serial communication module, differential driving modules, oneth MDR26 adapter solves difference block with first and second respectively and is connected, 2nd MDR26 adapter solves difference block with the 3rd respectively, serial communication module, differential driving module are connected, and this first, second and third solution difference block and serial communication module, differential driving module are connected with FPGA respectively；Every road Full mode data differential signal solves difference block through three and is converted into data TTL signal, and serial communication signal is decoded by serial communication module, controls differential signal and produces through differential driving module, and the data TTL signal that solution difference block produces enters FPGA；
3rd step, Cameralink camera signal enters FPGA through the data TTL signal that Video Reception System solution difference block produces and merges, these TTL data signals include clock signal, valid data signal, line synchronising signal and frame synchronizing signal, these signal sequences are simple, in FPGA, two-way image is merged easily realization, the data TTL signal i.e. produced using the image of a wherein road Cameralink camera transmission through Video Reception System solution difference block is as benchmark, the data TTL signal time delay in addition in FPGA, the picture signal on the second tunnel produced through Video Reception System solution difference block, two-way row is synchronized and frame synchronizing signal synchronizes, then respective pixel is done weighted average, weighted average formula is:
F(m1,m2)=W1N1(m1,m2)+W2N2(m1,m2) (1)
N in formula (1)1, N2Represent the first, the second width image, W respectively1, W2The weight coefficient that the first, the second width image is corresponding, and W1+W2=1；
4th step, memorizer is responsible for fusion image data signal in FPGA to read, is stored in external memory storage；Or being buffered in the data read-out of external memory storage in FPGA；
5th step, the viewdata signal after being processed by FPGA is sent into multi-core DSP by Rapid IO and is processed；
6th step, the image after being processed by multi-core DSP passes back in FPGA, and with the form of VGA standard, the result finally merged is exported display terminal.
The present invention compared with prior art, its remarkable advantage: the input of two-path video that (1) merges is Cameralink, and transmission bandwidth, up to more than Gpbs, has significant advantage in high-resolution height frame frequency image procossing；(2) two-way Cameralink video input is Full pattern, compares general Base pattern and more can meet the requirement of high rate burst communication；(3) the data TTL signal sequential that Cameralink camera signal produces through Video Reception System solution difference block is simple, and there is the least phase contrast between synchronization two-path video, in FPGA, two-way image is merged realization.
Below in conjunction with the accompanying drawings the present invention is described in further detail.
Accompanying drawing explanation
Fig. 1 is the entire block diagram of present invention image fusion system based on Cameralink.
Fig. 2 is the embodiment block diagram of present invention image fusion system based on Cameralink.
Fig. 3 is camera register address.
Fig. 4 read write command form.
Fig. 5 is FPGA built-in system flow chart.
Fig. 6 is row field sync signal sequential chart.
Detailed description of the invention
In conjunction with Fig. 1, present invention image fusion system based on Cameralink, system composition and internal signal thereof flow to as follows:
System includes two-way Cameralink Video Reception System, FPGA, memorizer, multi-core DSP, display, two-way Cameralink Video Reception System is connected with FPGA respectively, this FPGA respectively with memorizer, multi-core DSP, display connects, this Cameralink Video Reception System is by two MDR26 adapters, three solve difference block, serial communication module, differential driving module forms, oneth MDR26 adapter is respectively with first, two solve difference block connects, 2nd MDR26 adapter solves difference block with the 3rd respectively, serial communication module, differential driving module connects, this is first years old, two, three solve difference block and serial communication module, differential driving module is connected with FPGA respectively；Cameralink camera signal under two-way Full pattern is transferred in Cameralink Video Reception System, every road Full mode data differential signal solves difference block through three and is converted into data TTL signal, serial communication signal is decoded by serial communication module, control differential signal to produce through differential driving module, the data TTL signal entrance FPGA solving difference block generation merges, data exchange is carried out with memorizer during image procossing, multi-core DSP is sent into through Rapid IO after Image semantic classification, FPGA is passed back again through Rapid IO, finally the image after process is shown on USB interface display.
In conjunction with Fig. 2, present invention image interfusion method based on Cameralink, step is as follows:
The first step, two groups of Video Reception Systems are selected to accept the Low Voltage Differential Signal that Cameralink interface camera transmits, next group Cameralink signal packet of Full pattern is containing 21 pairs of differential signals, including 12 pairs of data differential signals, 3 pairs of clock signals, 2 pairs of serial communication signals and 4 pairs of camera control signals, difference chip DS90CR288A is solved through 3, differential data signals differential clock signal exports TTL data signal and clock signal in the ratio of 7:1, and the maximum clock frequency that can pass through is up to 85MHz.The two-path video input that this hardware system merges is Cameralink, and all can reach Full pattern, as a example by 8 bit images of common 2048*2048, when shooting frame frequency and being 100 frames/second, the data volume needing real-time Transmission is 3200Mb/s, and the total bandwidth of two-way can reach 6400Mb/s.For the circuit of the data division under Full pattern by a Cameralink interface, two panels solution difference chip DS90CR288A is constituted, this MDR26 adapter accesses 4 pairs of data differential signals on Y road and the differential signal on 1 pair of clock difference sub-signal and 4 pairs of data differential signals on Z road and 1 pair of clock difference sub-signal .Y road 29 TTL signal of generation after DS90CR288A decodes that camera transmits, the differential signal on Z road generates 29 TTL signal, the resistors match effect being added in circuit between differential signal after another sheet DS90CR288A decodes.
Camera controlling part includes 4 pairs of differential signals (CC1, CC2, CC3 and CC4), selects differential driving chip DS90LV031 here, and this chip just can drive 4 to differential signal.
Serial communication part includes 2 pairs of differential signals, and serial communication is defined as asynchronous communication model, can be to the various parameters of the camera such as camera exposure time by serial communication, and resolution etc. is configured.Select the chip DS90LV019 with 1 pair of difference transmission and 1 pair of differential received just differential pair signal can be converted into TTL signal, also TTL signal can be converted to differential signal.Basler provides two kinds of instruction databases to facilitate camera to arrange and to control, one is to use Basler pylon api function by software, another kind is to configure camera by the way of FPGA directly accesses depositor. project is selected the second way control camera, the parameters such as Basler provides register address, instruction format.Register address as it is shown on figure 3, read write command form as shown in Figure 4.
Second step, select XC6SLX45T-FPGA as digital signal processing core chip, because it has 4.3 ten thousand logical blocks (LE), 190 I/O mouths with various modes, core voltage is 1.2V, low-power consumption, high-performance, the various interface devices of periphery can be directly connected to, such as LVDS-TTL transducer, DDR3SDRAM storage chip etc..DDR3 sdram size is 1024M bytes, employs two panels DDR3SDRAM memorizer, and Cameralink can transmit 8 pixels simultaneously, and resolution is maximum up to 2048*2048, and frame frequency is up to 100 frames/second, and this capacity meets design requirement.
null3rd step，Cameralink camera signal enters FPGA through the data TTL signal that Video Reception System solution difference block produces and merges，These TTL data signals include clock signal，Valid data signal，Line synchronising signal and frame synchronizing signal，These signal sequences are simple，In FPGA, two-way image is merged easily realization，Owing to the Cameralink camera signal under two-way Full pattern is transferred to two-way Cameralink video reception subsystem simultaneously，So there is the least phase contrast between synchronization two-path video，Using the image of a wherein road camelink camera transmission as benchmark，Picture signal time delay in addition to the second tunnel，Two-way row is synchronized and frame synchronizing signal synchronizes，Then respective pixel is done weighted average，Fused image standard deviation diminish noise reduce.Weighted average formula is:
F(m1,m2)=W1N1(m1,m2)+W2N2(m1,m2) (1)
N in formula (1)1, N2Represent the first, the second width image, W respectively1, W2The weight coefficient that the first, the second width image is corresponding, and W1+W2=1.Participate in merge two width images provide a lot of complementary informations, improve reliability and the noise of detection, fused image standard deviation diminish noise reduce.
4th step, designs DDR3 memory read/write module, and this module is data cache module, it is responsible for fusion image data signal in FPGA to read, and is stored in external memory storage, owing to the image data amount of input is the biggest, speed is very fast, and therefore system uses two panels DDR3 SDRAM to realize the slow mechanism of table tennis.First the view data in FPGA is cached in DDR3 SDRAM, starts to read after writing full frame data, when writing SDRAM2, SDRAM1 is carried out read operation, and when writing DDR3 SDRAM1, DDR3SDRAM2 is carried out read operation.Read-write switching can be controlled by frame useful signal FVAL, by image buffer storage complete for a frame to a piece of DDR3 SDRAM, it is simple to follow-up process.FPGA built-in system flow chart is as shown in Figure 5: after starting working, first FPGA initializes, then camera data is stored, read camera data the most again, 24 pixels are determine whether, if it is not, continue to read camera data by tabling look-up, if carrying out fusion treatment, delivering to DSP after fusion treatment and being further processed.
5th step, owing to the FPGA model in system is for selecting XC6SLX45T, this chip includes 4 pairs of high speed serialization transceivers, this transceiver is primarily used to DSP and FPGA and interacts with each other data, this high speed port speed up to Gbit, in Spartan-6, Rapid transceiver is on BANK0, and clock is produced a pair differential clocks by special differential clocks chip IC S844021, again by ICS8543 generation four to differential clocks, to Rapid transceiver.Differential clocks is 125MHZ, can meet the Rapid I/O module requirement to reference clock in design.The image processed through FPGA sends into TMS320C6678 process through Rapid IO, due to containing much information after fused process, edge extracting based on Prewittz operator can be realized and to functions such as the background subtractions of static object with some image processing algorithms in dsp.
6th step, the image after being processed by DSP passes back in FPGA.The result finally merged is exported display terminal with the form of VGA standard.As selected ADV7123 as video d/a transducer.ADV7123 is three tunnels high speeds, the video d/a transducer of 1O position input, has the maximum sample rate of 330MH Z, compatible with multiple high-precision display system, it is possible to meet many-sided application demand.Produce three tunnel simulation outputs by ADV7123, complete the display of image in combination with row field sync signal.If the image being buffered in SDRAM is shown at USB interface display, it would be desirable to structure scanning sequence.Design needs to meet the output image of VGA75Hz form, the valid pixel resolution of i.e. 1024 X 768, and frame frequency 75Hz, line frequency 60kHz, owing to crystal oscillator inputs 27MHz clock signal, to the pixel clock producing 81MHz after its frequency multiplication.Therefore, line period=81MHz ÷ 60kHz=1350, frame period=60kHz/75Hz=800, horizontal blanking=1350 1024=326, frame blanking=800-768=32.Field synchronization, line synchronising signal can be built by FPGA.The 81MHz produced after choosing frequency multiplication inputs as pixel clock, it is entered into mould equal in the pixel pulse enumerator of HP (=1350), the output low level when step-by-step counting is less than HB=326, other exports high level, in this, as line synchronising signal Hsys；Then counting in units of Hsys row beat, the output low level when count value is less than VB=32, other exports high level, and after count value is equal to VP (=800) individual line synchronising signal, counter O reset, in this, as field sync signal Vsys.Row field sync signal sequential chart is as shown in Figure 6.
Claims (1)
1. an image interfusion method based on Cameralink, it is characterised in that step is as follows:
The first step, the Cameralink camera signal under two-way Full pattern is according to Cameralink protocol transmission
To two-way Cameralink Video Reception System；
Second step, two-way Cameralink Video Reception System will melt in feeding FPGA real-time for data
Conjunction process, every road Cameralink Video Reception System by two MDR26 adapters, three solve difference block,
Serial communication module, differential driving module form, and a MDR26 adapter solves difference with first and second respectively
Module connects, and the 2nd MDR26 adapter drives with the 3rd solution difference block, serial communication module, difference respectively
Dynamic model block connects, and this first, second and third solution difference block and serial communication module, differential driving module are respectively
It is connected with FPGA；Every road Full mode data differential signal solves difference block through three and is converted into data TTL
Signal, serial communication signal is decoded by serial communication module, controls differential signal and produces through differential driving module,
Solve the data TTL signal entrance FPGA that difference block produces；
3rd step, data TTL that Cameralink camera signal produces through Video Reception System solution difference block
Signal enter FPGA merge, these TTL data signals include clock signal, valid data signal,
Line synchronising signal and frame synchronizing signal, these signal sequences are simple, melted by two-way image in FPGA
Close and easily realize, i.e. with the image of a wherein road Cameralink camera transmission through Video Reception System solution difference
The picture signal on the second tunnel, as benchmark, is connect in FPGA by the data TTL signal that module produces through video
Receive the data TTL signal in addition time delay that Solutions of Systems difference block produces so that two-way row synchronizes and frame synchronization is believed
Number synchronize, then respective pixel is done weighted average, weighted average formula is:
F(m1,m2)=W1N1(m1,m2)+W2N2(m1,m2) (1)
N in formula (1)1, N2Represent the first, the second width image, W respectively1, W2The first, the second width figure
As corresponding weight coefficient, and W1+W2=1；
4th step, memorizer is responsible for fusion image data signal in FPGA to read, is stored in external memory storage
In；Or being buffered in the data read-out of external memory storage in FPGA；
5th step, the viewdata signal after being processed by FPGA is sent into multi-core DSP by Rapid IO and is carried out
Process；
6th step, the image after being processed by multi-core DSP passes back in FPGA, by the result that finally merges with
The form of VGA standard exports display terminal.
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| CN105025291A (en) * | 2015-07-30 | 2015-11-04 | 武汉精测电子技术股份有限公司 | Method and device for generating TTL video signal |
| CN106341571A (en) * | 2016-08-18 | 2017-01-18 | 深圳市金立通信设备有限公司 | Image processing method and terminal |
| CN106251279A (en) * | 2016-08-18 | 2016-12-21 | 深圳市金立通信设备有限公司 | A kind of image processing method and terminal |
| CN106991657A (en) * | 2017-03-22 | 2017-07-28 | 南京理工大学 | A kind of infrared small target detection method and system based on FPGA |
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| CN108154493B (en) * | 2017-11-23 | 2021-11-30 | 南京理工大学 | FPGA-based dual-waveband infrared image pseudo-color fusion algorithm |
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| CN111698387A (en) * | 2020-06-19 | 2020-09-22 | 西安微电子技术研究所 | LVDS-to-VGA display signal conversion module and working method |
| CN112256627A (en) * | 2020-10-21 | 2021-01-22 | 四川望望科技有限公司 | High-definition high-frame-frequency real-time image processing platform and method for photoelectric tracking system |
| CN113459131A (en) * | 2021-07-13 | 2021-10-01 | 江苏华途数控科技有限公司 | Industrial long-distance VGA analog signal display equipment |
| CN114866710B (en) * | 2022-06-02 | 2023-09-19 | 中国科学院光电技术研究所 | Universal decoding and data acquisition device based on Camera-link Camera |
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