CN105721818B - A kind of signal conversion method and device - Google Patents
A kind of signal conversion method and device Download PDFInfo
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- CN105721818B CN105721818B CN201610155894.0A CN201610155894A CN105721818B CN 105721818 B CN105721818 B CN 105721818B CN 201610155894 A CN201610155894 A CN 201610155894A CN 105721818 B CN105721818 B CN 105721818B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
- H04N7/012—Conversion between an interlaced and a progressive signal
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
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Abstract
The invention discloses a kind of signal conversion method and devices, carry out image data dividing processing by the LVDS signals of the low resolution and brush frequency that are exported to traditional images signal source, field frequency multiplication is handled, signal of the generation suitable for V BY ONE display module screen tests；To achieve the purpose that the V BY ONE display modules in such a way that existing image signal source lights 4k, 8k, 10k resolution ratio, various different display Lane numbers and split-screen display；Device provided by the invention can receive exterior arrangement, be suitable for the V BY ONE modules of different resolution by high-level interface module, and may be adapted to the LVDS picture signals of various traditional images signal source inputs, have the advantages that simple and efficient to handle；On the other hand, the present invention can realize that technical solution is flexible, and cost of implementation is relatively low, has the characteristics that stable work in work by fpga chip.
Description
Technical field
The invention belongs to signal processing technology fields, and low resolution image signal source point is used more particularly, to a kind of
The signal conversion method and device of bright ultrahigh resolution V-BY-ONE display modules.
Background technology
With the development of LCD technology, the large-sized display devices of ultra high-definition 4K resolution ratio (3840 × 2160) are (aobvious
Show that area is more than 50 English inch) it has popularized, the very large-sized display devices amount of also beginning to of high definition 8K resolution ratio (7680 × 4320)
Production.In order to reach the display performance of ultrahigh resolution, it is ensured that the reliability used, and manufacturing cost is reduced, these display equipment
Module mostly uses V-BY-ONE video interfaces technology to receive picture signal.
V-BY-ONE display modules are mainly detected by showing still image.Due to much produce commercial city be from
Common full HD module turns to the production of ultra high-definition module, therefore still has a large amount of traditional LVDS image signal sources to be used for module
Detection；It is 30Hz or 60Hz that this kind of LVDS image signal sources highest resolution, which is no more than 1920 × 1080, field frequency, can not be generated more
The picture signal of high-resolution and higher field frequency；But normally lighting V-BY-ONE modules needs 4k or 8k resolution ratio, field frequency to exist
100Hz, 120Hz or 240Hz, and the picture signal with high speed transmission of signals rate；This exceeds the LVDS of traditional images signal source
The data transmission rate upper limit.In order to continue with this kind of image signal source, the testing cost of V-BY-ONE modules is reduced, one kind is needed
It can be using the signal conversion method and dress of the bright ultrahigh resolution V-BY-ONE display modules of traditional low resolution image signal source point
It sets.
Invention content
For the disadvantages described above or Improvement requirement of the prior art, the present invention provides a kind of signal conversion method and device,
Its object is to the LVDS signals exported to image signal source to carry out image data dividing processing, field frequency multiplication processing, to generate
Signal suitable for V-BY-ONE display module screen tests.
To achieve the above object, according to one aspect of the present invention, a kind of signal conversion method is provided, is used for low field
The LVDS images of frequency refresh rate are converted into reaching the signal of V-BY-ONE module point screen standards, include the following steps：
(1) according to LVDS image producing method parameters and V-BY-ONE module lane numbers, link each to each image signal source
RGB image signal be combined, generate original V-BY-ONE images；And by the image data successively in turn be assigned to it is each
On a link, the V-BY-ONE image datas of parallel standardized more link and corresponding V-BY-ONE are generated
Lane sequential, including field sync signal VSync, line synchronising signal HSync, data enable signal DE；
(2) according to V-BY-ONE module lane numbers, V-BY-ONE module split screen mode setting parameters, to above-mentioned standard
Each V-BY-ONE image datas and sequential carry out data array conversion, obtain each lane numbers of V-BY-ONE data formats
According to, and sequential corresponding with each lane data；
The characterisitic parameter of the clock signal includes the RGB of crop, back porch, virtual value and pulsewidth with above-mentioned each link
Signal sequence keeps synchronizing；
(3) under the control of above-mentioned sequential corresponding with lane data, each lane data are carried out at caching and synchronization
Reason, to ensure that each lane signals of screen keep synchronous completely；
(4) while above-mentioned synchronization process, the corresponding clock signal of each lane data is detected, obtains sequential ginseng
Number, including pixel clock frequency, the crop of line frequency/field frequency, back porch, virtual value, pulsewidth；
(5) according to V-BY-ONE field frequencies multiplication arrange parameter, to each lane numbers of above-mentioned time sequence parameter and V-BY-ONE
Field frequency process of frequency multiplication is carried out according to corresponding clock signal, obtains V-BY-ONE multiplication sequential and parameter；
(6) according to V-BY-ONE signal output parameters, to after synchronization process lane data and sequential carry out at multiple field frequency
Reason, and treated that parallel each lane V-BY-ONE data conversions transmit signal at the lane of V-BY-ONE by multiple field frequency；Its
In, LVDS image producing methods parameter, V-BY-ONE module lane numbers parameter, V-BY-ONE module split screen mode settings parameter,
V-BY-ONE field frequencies multiplication arrange parameter and V-BY-ONE signals output parameter are obtained all in accordance with upper-layer configured.
Preferably, above-mentioned signal conversion method, the RGB image that each link of each image signal source is obtained according to following steps are believed
Number：
(a) demodulation parameter is received according to LVDS to connect the LVDS picture signals of each link of each image signal source
Demodulation is received, the parallel demodulation data of each link are generated；
Wherein, LVDS receptions demodulation parameter includes：The LVDS termination matchings impedance value of each link receives equilibrium value, passes
Defeated delay adjusting parameter, LVDS VESA, JEIDA decodings setting, LVDS transmit clock module；
(b) the parallel demodulation data of above-mentioned each link are cached so that each link data of output are figure
As the data of row field synchronization；
(c) according to LVDS image producing method parameters, the data of above-mentioned image line field synchronization are carried out with RGB decoding parametrics
RGB is decoded, and obtains the RGB image signal of each link of each image signal source；Wherein, LVDS receives demodulation parameter and RGB decoding ginsengs
Number is obtained all in accordance with upper-layer configured.
Preferably, above-mentioned signal conversion method, it is defeated to the V-BY-ONE modules of different display Lane numbers in step (1)
The link numbers for going out image are different, specific as follows：
When being 4Lane V-BY-ONE modules by a module for screen, then original V-BY-ONE image datas are put into individually
It is exported on link, that is, exports list link data；
When being 8Lane V-BY-ONE modules by a module for screen, then original V-BY-ONE images are distributed to link in pairs
Data；
If being 16lane V-BY-ONE modules by a module for screen, original V-BY-ONE images are distributed into four link
Data；
If being 32lane V-BY-ONE modules by a module for screen, original V-BY-ONE images are distributed into eight link
Data.
Preferably, step (3) is specific as follows：Under clock signal control, each lane data-signals are first cached into several rows；
While caching, de-jitter is carried out to the sequential of input, improves the stringency and stability of its sequential；It is risen in new a line
When the beginning, under the clock signal control after debounce, each lane data are exported simultaneously, so that it is guaranteed that each road lane data synchronize.
Preferably, step (6) is specific as follows：
(6.1) local cache is carried out to input data；
(6.2) when a frame originates, memory module is written into the data after caching；
(6.3) it after the roads a Zheng Zhonggai lane data have all stored, is being write in the case where V-BY-ONE doubles timing control
It in the period for entering a frame lane data, repeats to read lane data M times with the speed of M times of writing speed, and by reading
Lane data are sequentially allocated on each lane, form parallel lane data；M one frame lane data of reading, it is arranged successively
It is listed on the data-signal of lane0~lane n, realizes the M frequencys multiplication operation of output field frequency；Wherein, M=4,8,16 or 32；
(6.4) after each lane data distribute, stringization processing is carried out to parallel lane data, each lane is parallel
Data conversion transmits signal at the lane of V-BY-ONE.
Preferably, it in step (6.3), carries out reading data respectively simultaneously using two storage units and writes the operation of data：
When one of storage unit is while being written a certain frame lane data, another storage unit is in the number for reading previous frame
According to；The two alternately read-write operation in a manner of ping-pong operation；Due to the total throughout identical two storage unit write-in and read
A storage unit can continuously carry out the multiple field frequency operation of each lane data, avoid because storage unit writes full or reading empty problem institute
Caused loss of data or operation pause.
Purpose to realize the present invention, other side according to the invention provide a kind of chromacoder, including
LVDS signal input interfaces, V-BY-ONE signal output interfaces, upper layer software (applications) control signal input interface；And it is solidificated in one
Each Lane image datas generation module of V-BY-ONE image-restoration modules in programmable logic device, V-BY-ONE, V-BY-
ONE image synchronization modules, V-BY-ONE image sequential computing module, V-BY-ONE image sequential multiplication modules and V-BY-ONE letters
Number output module；Wherein, V-BY-ONE signal output modules include at least one V-BY-ONE signal generator modules；
Wherein, programmable logic device has LVDS signal input terminals, the coupling for coupling above-mentioned LVDS signal input interfaces
Connect the V-BY-ONE signal output terminals and the above-mentioned upper layer software (applications) control signal of coupling of above-mentioned V-BY-ONE signal output interfaces
Upper layer software (applications) control signal input of input interface；
Wherein each Lane image datas generation module of V-BY-ONE image-restoration modules, V-BY-ONE, V-BY-ONE images
Synchronization module, V-BY-ONE signal output modules are sequentially connected；
Each Lane image datas generation modules of V-BY-ONE also with V-BY-ONEE image sequential computing modules and V-BY-ONE
Image sequential multiplication modules connect；V-BY-ONE image sequential computing modules are mutually connected with V-BY-ONE image sequential multiplication modules
It connects；V-BY-ONE image sequential multiplication modules are also connect with V-BY-ONE signal output modules；
V-BY-ONE image-restoration modules are according to LVDS image producing method parameters and V-BY-ONE module Lane numbers, to each
The RGB image signal of each link of image signal source is combined, and recovers original V-BY-ONE images, and is distributed into parallel
Standardized more link rgb signal and corresponding V-BY-ONE images Link clock signals (VSync, HSync,
DE)；Such as corresponding list link timing sequential, double link timing sequential, four link timing sequential, eight link
Timing sequential；
Each Lane image datas generation modules of V-BY-ONE are according to V-BY-ONE module lane numbers, V-BY-ONE module split screens
Mode setting parameter carries out data array conversion to each link RGB datas and sequential of above-mentioned standard, obtains V-
Each lane data of BY-ONE data formats；And sequential corresponding with each lane data；
Rgb signal of the characterisitic parameter (such as crop, back porch, virtual value, pulsewidth) of the clock signal with above-mentioned each link
Sequential keeps synchronizing；
V-BY-ONE image synchronization modules delay each lane data under the corresponding timing control of above-mentioned lane data
It deposits and synchronization process, to ensure that each lane signals of screen can strictly keep synchronous；
Specifically, V-BY-ONE image synchronization modules are under clock signal control, if each lane data-signals are first cached
Dry row, meanwhile, de-jitter is carried out to the sequential of input, improves the stringency and stability of its sequential；Again in new a line
When starting, under the clock signal control after debounce, each lane data are exported simultaneously, so that it is guaranteed that each road lane data are same
Step；
While V-BY-ONE image synchronization modules synchronize processing, V-BY-ONE image sequential computing modules are to coming
It is detected from the corresponding clock signal of lane data of each Lane image datas generation modules of V-BY-ONE, and obtains sequential ginseng
Number, including pixel clock frequency, the crop of line frequency/field frequency, back porch, virtual value, pulsewidth；
V-BY-ONE image sequential multiplication modules according to V-BY-ONE field frequencies double arrange parameter, to above-mentioned time sequence parameter with
And the corresponding clock signal of each lane data of the V-BY-ONE from each Lane image datas generation modules of V-BY-ONE carries out
Field frequency process of frequency multiplication obtains V-BY-ONE multiplication sequential and parameter；
V-BY-ONE signal output modules are under the control of V-BY-ONE signal output parameters, to the lane after synchronization process
Data and sequential carry out multiple field frequency processing, and carry out stringization processing to data parallel each lane, are converted into V-BY-ONE transmission
Signal.
Preferably, above-mentioned chromacoder further includes high-level interface module, LVDS signal processing modules and LVDS images
Generation module；Wherein, LVDS signal processing modules, LVDS image generating modules, V-BY-ONE image-restoration modules, V-BY-ONE
Each Lane image datas generation module, V-BY-ONE image sequential multiplication modules and V-BY-ONE signal output modules are and upper layer
Interface module connects；
Wherein, high-level interface module is used to generate all kinds of parameters according to upper-layer configured, including LVDS receive demodulation parameter,
RGB decoding parametrics, LVDS image producing methods parameter, V-BY-ONE module lane numbers, V-BY-ONE module split screen mode settings
Parameter, V-BY-ONE field frequencies multiplication arrange parameter and V-BY-ONE signal output parameters；LVDS image producing method parameter packets
Include attachable image signal source quantity, the link numbers of the image of each image signal source input；
LVDS signal processing modules are used to that the LVDS picture signals of each link to be carried out receiving demodulation and be cached, and generate image
The data of row field synchronization；LVDS image generating modules are used to carry out RGB decodings to the data of the image line field synchronization, obtain each figure
As the RGB image signal of each link of signal source.
Preferably, above-mentioned chromacoder, LVDS signal processing modules include that sequentially connected LVDS signals receive
Module and LVDS signal synchronization caching modules；LVDS signal receiving modules receive demodulation parameter to from each picture signal according to LVDS
The LVDS picture signals of each link of source access carry out reception demodulation, generate the parallel demodulation data of each link；LVDS signals
Synchronization caching module caches above-mentioned parallel demodulation data.
Preferably, above-mentioned chromacoder, V-BY-ONE signal generator modules include image data cache module, figure
As data read-write control module, memory module, V-BY-ONE image field frequencies multiplication modules, V-BY-ONE signal output sub-modules；
Wherein, V-BY-ONE images field frequency multiplication modules cache mould by image data Read-write Catrol module and image data
Block connects；Image data Read-write Catrol module is also connect with memory module；
Image data cache module carries out local cache according to the sequential of reception to each lane data received；In a frame
When starting, memory module is written in the data after caching by image data Read-write Catrol module；When the roads a Zheng Zhonggai lane data
When being all written in memory module, V-BY-ONE image field frequency multiplication modules double in V-BY-ONE under timing control, pass through
Image data Read-write Catrol module is written and read control to memory module, reads out lane data；V-BY-ONE signals
For output sub-module according to V-BY-ONE signal output parameters, the data parallel to each lane carry out stringization processing, are converted into V-BY-
ONE transmits signal.
Preferably, above-mentioned memory module includes two storage units arranged side by side, and respectively the first storage unit is deposited with second
Storage unit；
First storage unit is used to the lane data after memory buffers with the second storage unit；When a frame originates, figure
As the data after caching are written in the first storage unit data read-write control module, when the roads Zheng Zhonggai lane data are whole
After being written to the first storage unit, V-BY-ONE image field frequency multiplication modules read lane data from the first storage unit；
Image data Read-write Catrol module carries out read and write data manipulation while controlling two storage unit difference：Specifically
Ground, when a storage unit is while being written a certain frame lane data, another storage unit reads the data of previous frame；Two
Storage unit alternately read-write operation in a manner of ping-pong operation；And V-BY-ONE image field frequencies multiplication modules then press multiplication sequential
The lane data of a frame are repeatedly read, lane0 is sequentially arranged within the period that a frame is written with the control of parameter
On the data-signal of~lane3；
Since the write-in of storage unit is identical as the total throughout read, therefore image data Read-write Catrol module and V-
BY-ONE image field frequencies multiplication modules can continuously carry out the multiple field frequency operation of each lane data, avoid because storage unit is write completely
Or the problem of reading loss of data or the operation pause caused by sky.
In general, through the invention it is contemplated above technical scheme is compared with the prior art, can obtain down and show
Beneficial effect：
(1) signal conversion method and device provided by the invention, the low field frequency refresh rate that traditional images signal source is exported
The LVDS data that can not normally light V-BY-ONE modules, carry out image data dividing processing, image field frequency multiplication processing, with
Reach the point screen requirement of V-BY-ONE modules；It realizes various to light by traditional image signal source output still image
The purpose of lane numbers and the V-BY-ONE modules of split screen type, such as 4Lane modules, 8Lane modules, 16Lane modules, 32Lane
Module, 2 panes module, four split screen modules, eight split screen modules, 16 split screen modules；
(2) signal conversion method and device provided by the invention, the maximum image that can be shown according to image signal source
One width V-BY-ONE module images, can be divided into different piece by resolution ratio, and each image signal source exports respective part simultaneously
Image；I.e. according to actual point screen resolution ratio, with one or more traditional images signal source, the shown V-BY-ONE of output schemes jointly
The a certain parts of images signal of picture；
(3) signal conversion method provided by the invention, step (5) by data-signal by being transformed into standardized data
Format is handled convenient for follow-up V-BY-ONE lane data and field frequency multiplication, improves the reliability of V-BY-ONE data realization；
And eliminate factor (including image signal source quantity, each image signal source output link numbers, the image letter of image signal source
Number source connection type and transmission coding mode) influence to follow-up signal processing so that subsequent processing can be according to unified processing
Mode carries out, to simplify product design, improve output data performance；Also, due to V-BY-ONE image data amounts and data
Transmission rate is significantly larger than tradition LVDS images, therefore the parallel processing manner of standardized more link data is used to reduce data
Processing speed to be readily susceptible to apply, and may migrate to middle realization on different electronic devices, reduce cost of implementation, and ensure
The stability of realization；
(4) signal conversion method and device provided by the invention are received exterior arrangement, can be fitted by high-level interface module
The V-BY-ONE modules of different resolution are answered, and may be adapted to the LVDS picture signals of various traditional images signal source inputs, are had
Advantage simple and efficient to handle；
(5) chromacoder provided by the invention can realize that technical solution is flexible, Er Qieshi by fpga chip
Ready-made relatively low, has the characteristics that stable work in work.
Description of the drawings
Fig. 1 is the functional schematic of chromacoder provided in an embodiment of the present invention；
Fig. 2 is the LVDS signal processing module schematic diagrames of chromacoder provided in an embodiment of the present invention；
Fig. 3 is the V-BY-ONE signal output module schematic diagrames of chromacoder provided in an embodiment of the present invention；
Fig. 4 is the V-BY-ONE signal generator module schematic diagrames of chromacoder provided in an embodiment of the present invention；
Fig. 5 is the schematic diagram generated by 4 image signal source conversions for V-BY-ONE module screen test signals；
Fig. 6 is the schematic diagram generated by 16 image signal source conversions for V-BY-ONE module screen test signals.
In all the appended drawings, identical reference numeral is used for indicating identical element or structure, wherein：1- high-level interface moulds
Block, 2-LVDS signal receiving modules, 3-LVDS signal synchronization cachings module, 4-LVDS image generating modules, 5-V-BY-ONE figures
As recovery module, each Lane image datas generation modules of 6-V-BY-ONE, 7-V-BY-ONE image synchronization modules, 8-V-BY-ONE
Image sequential computing module, 9-V-BY-ONE image sequential multiplication modules, 10-V-BY-ONE signal output modules, 10-1- first
V-BY-ONE signal generator modules, the 2nd V-BY-ONE signal generator modules of 10-2-, the 3rd V-BY-ONE signals of 10-3- generate
Module, the 4th V-BY-ONE signal generator modules of 10-4-, the 5th V-BY-ONE signal generator modules of 10-5-, the 6th V- of 10-6-
BY-ONE signal generator modules, the 7th V-BY-ONE signal generator modules of 10-7-, the 8th V-BY-ONE signals of 10-8- generate mould
Block, 101- image datas cache module, 102- image data Read-write Catrols module, 103- memory modules, 104-V-BY-ONE figures
Image field frequency multiplication modules, 105-V-BY-ONE signals output sub-module, the first storage units of 103A-, the second storage units of 103B.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in the various embodiments of the present invention described below
It does not constitute a conflict with each other and can be combined with each other.
Shown in Fig. 1, it is the functional schematic for the chromacoder that inventive embodiments provide, including be solidificated in one to compile
High-level interface module 1, LVDS signal processing modules on journey logical device, LVDS image generating modules 4, V-BY-ONE images are extensive
When multiple module 5, each Lane image datas generation modules 6 of V-BY-ONE, V-BY-ONE image synchronization modules 7, V-BY-ONE images
Sequence computing module 8, V-BY-ONE image sequential multiplication modules 9 and V-BY-ONE signal output modules 10.
LVDS signal processing modules are as schematically shown in Figure 2, including sequentially connected LVDS signal receiving modules 2 and LVDS letters
Number synchronization caching module 3；
In the present embodiment, V-BY-ONE signal output modules 10 are as schematically shown in Figure 3, including 8 V-BY-ONE arranged side by side
Signal generator module；V-BY-ONE signal generator modules are as schematically shown in Figure 4, including image data cache module 101, picture number
According to Read-write Catrol module 102, memory module 103, V-BY-ONE image field frequencies multiplication modules 104, V-BY-ONE signals output
Module 105；Wherein, V-BY-ONE images field frequency multiplication modules 104 pass through image data Read-write Catrol module 102 and image data
Cache module 101 connects；Image data Read-write Catrol module 102 is also connect with memory module 103；Wherein, memory module 103 is wrapped
It includes including two storage units, respectively the first storage unit 103A and the second storage unit 103B；In embodiment, the first storage
Unit and the second storage unit are all made of DDR.
Using chromacoder provided in this embodiment, realizes and use the bright super-resolution of low resolution image signal source point
The signal conversion method of rate V-BY-ONE display modules, it is specific as follows：
(1) image can be generated according to the highest of the resolution ratio of shown V-BY-ONE modules and traditional images signal source used
Resolution ratio come determine want required for use same image signal source quantity；
When V-BY-ONE modules are 4k resolution ratio (3840 × 2160, field frequency 120Hz), and traditional images signal source used
The highest resolution that can be generated picture signal is 1920 × 1080, field frequency 30Hz；Then need 4 this image signal sources simultaneously
The parts of images signal of the different zones of V-BY-ONE images is generated, as shown in Figure 5；If used traditional images signal source is most
The resolution ratio that high energy is supported is 3840 × 2160, field frequency 30Hz, then only with an image signal source；That is the device of the invention
And method, the number of used image signal source can be according to user demand flexible configuration；
In embodiment, the resolution ratio that used image signal source can be supported reaches 1920 × 1080, field frequency 30Hz；
Before 4 image signal sources show V-BY-ONE module images, need, by the picture of the 4k resolution ratio of standard shown in fig. 5, to cut
At 4 1920 × 1080 pictures；
If desired 8k V-BY-ONE module images (7680 × 4320) are shown, then need 16 such image signal sources
To generate the module image of respective subregion, as shown in Figure 6；
Each image signal source is with identical LVDS arrange parameters (identical LVDS link numbers, LVDS coding modes, transmission
Rate) it generates respective LVDS picture signals and is sent to LVDS signal receiving modules 2；
(2) top level control signal is generated according to upper-layer configured, including LVDS receives demodulation parameter, RGB decoding parametrics, LVDS
Image producing method parameter, V-BY-ONE module lane numbers parameter, V-BY-ONE module split screen mode settings parameter, V-BY-ONE
Field frequency multiplication arrange parameter and V-BY-ONE signal output parameters；LVDS image producing method parameters include attachable image
Signal source quantity, the link numbers of the image of each image signal source input；
(3) LVDS signal receiving modules 2 receive demodulation parameter to each link's of each image signal source according to LVDS
LVDS picture signals carry out reception demodulation, generate the parallel demodulation data of each link；
Wherein, LVDS receptions demodulation parameter includes：The LVDS termination matchings impedance value of each link receives equilibrium value, passes
Defeated delay adjusting parameter, LVDS VESA, JEIDA decodings setting, LVDS transmit clock module；
(4) LVDS signals synchronization caching module 3 caches the parallel demodulation data of above-mentioned each link so that output
Each link data be image line field synchronization data；
(5) LVDS image generating modules 4 are according to LVDS image producing method parameters, with RGB decoding parametrics (6bit, 8bit,
10bit, 12bit color range be arranged) will synchronize after LVDS link signals carry out RGB decodings, obtain each link of each image signal source
RGB image signal；
(6) V-BY-ONE image-restoration modules 5 are according to LVDS image producing method parameters and V-BY-ONE module lane numbers,
The RGB data of link each to each image signal source is combined, and generates original V-BY-ONE images；And by the image data according to
Secondary being assigned on each link in turn, generates the V-BY-ONE image datas of more link of parallel standard, and therewith
Corresponding V-BY-ONE lane sequential, including VSync, HSync, DE；
Difference shows that the V-BY-ONE modules of Lane numbers, the link numbers of the distribution output V-BY-ONE images of module 5 are also different；
When being 4Lane V-BY-ONE modules by a module for screen, whole V-BY-ONE image datas are put into single link by module 5
Upper output, as list link form data export, and thus can light 8 pieces of 4lane modules simultaneously；
When being 8Lane V-BY-ONE modules by a module for screen, original V-BY-ONE images are then assigned to 2 by module 5
A link rgb signals output, i.e., double link forms data outputs, to which link1~link8 is four pairs of identical double link numbers
According to 4 pieces of 4lane modules thus can be lighted simultaneously；
When by screen V-BY-ONE modules an often row image data be (1,2,3 ..., 3838,3839,3840), then divide
The double link data modes matched are as follows：
Link1：(1、3、5、……、3835、3837、3839)
Link2：(2、4、6、……、3836、3838、3840)
When being 16lane V-BY-ONE modules by a module for screen, then original V-BY-ONE images are distributed into four by module 5
Link form data input, as follows：
Link1：(1、5、9、……、3829、3833、3837)
Link2：(2、6、10、……、3830、3834、3838)
Link3：(3、7、11、……、3831、3835、3839)
Link4：(4、8、12、……、3832、3836、3840)
When being 32lane V-BY-ONE modules by a module for screen, then original V-BY-ONE images are distributed into eight by module 5
Link form data input, as follows：
Link1：(1、9、……、3825、3833)
Link2：(2、10、……、3826、3834)
Link3：(3、11、……、3827、3835)
Link4：(4、12、……、3828、3836)
Link5：(5、13、……、3829、3837)
Link6：(6、14、……、3830、3838)
Link7：(7、15、……、3831、3839)
Link8：(8、16、……、3832、3840)；
(7) each Lane image datas generation modules of V-BY-ONE 6 are according to V-BY-ONE module lane numbers, V-BY-ONE modules
Span mode arrange parameter carries out data array conversion to each link RGB datas and sequential of above-mentioned standard, obtains
Each lane data and sequential of V-BY-ONE data formats；The module 6 exports the signal of the data of 4 lane of mixing on 8 tunnels, with
And sequential corresponding with each lane data；
The characterisitic parameter of the clock signal includes the RGB of crop, back porch, virtual value and pulsewidth with above-mentioned each link
Signal sequence keeps synchronizing；
Above-mentioned data conversion can be simultaneously and concurrently undelayed progress, for the different several classes of types of lane, different split screens
The V-BY-ONE modules of mode subtype, the lane data-signal shapes that each Lane image datas generation modules 6 of V-BY-ONE export
Formula is as follows：
When being the 4Lane not 4k resolution ratio modules of split screen by a module for screen, the lane data-signal shapes of the output of module 6
The formula single link data modes of input terminal (correspond to) is：
Lane data 1：(1、2、3、4、……、3837、3838、3839、3840)；
When being the 4k resolution ratio modules of two split screens of 4lane by a module for screen, the lane data-signal shapes of the output of module 6
The formula single link data modes of input terminal (correspond to) is：
Lane data 1：(1、2、1921、1922、……、1919、1920、3839、3840)；
For 4lane modules, module 6 can export identical 1 signal replication of lane data in 8 tunnels simultaneously, can light 8 pieces simultaneously
4lane modules.
When being the 8lane not 4k resolution ratio modules of split screen by a module for screen, the lane data-signal shapes of the output of module 6
The formula double link data modes of input terminal (correspond to) is：
Lane data 1：
(1、2、3、4、9、10、11、12、……、3833、3834、3835、3836)；
Lane data 2：
(5、6、7、8、13、14、15、16、……、3837、3838、3839、3840)；
When being the 4k resolution ratio modules of two split screens of 8lane by a module for screen, the lane data-signal shapes of the output of module 6
The formula double link data modes of input terminal (correspond to) is：
Lane data 1：(1、2、3、4、……、1917、1918、1919、1920)；
Lane data 2：(1921、1922、1923、1924、……、3837、3838、3839、3840)；
When being the 4k resolution ratio modules of tetra- split screens of 8lane by a module for screen, the lane data-signal shapes of the output of module 6
Formula (the double link data modes for corresponding to input terminal) is as follows：
Lane data 1：(1、2、961、962、3、4、963、964、……、959、960、1919、1920)；
Lane data 2：
(1921、1922、2881、2882、1923、1924、2883、2884、……、2879、2880、3839、3840)；
For in 8lane modules, module 6 can export the identical lane data 1 in 4 tunnels, 2 signal replications simultaneously, you can simultaneously
Light 4 pieces of 8lane modules.
When being the 4k resolution ratio modules of eight split screens of 16lane by a module for screen, the lane data-signals of the output of module 6
Form four link data modes of input terminal (correspond to) is：
Lane data 1：
(1、2、481、482、3、4、483、484、……、479、480、959、960)；
Lane data 2：
(961、962、1441、1442、963、964、1443、1444、……、1439、1440、1919、1920)；
Lane data 3：
(1921、1922、2401、2402、1923、1924、2403、2404、……、2399、2400、2879、2880)；
Lane data 4：
(2881、2882、3361、3362、2883、2884、3363、3364、……、3359、3360、3839、3840)；
For 16lane modules, module 6 can export identical 1~4 signal replication of lane data in 2 tunnels simultaneously, can same time point
Bright 2 pieces of 16lane modules.
When being the 4k resolution ratio modules of 16 split screens of 32lane by a module for screen, the lane data of the output of module 6
Signal form eight link data modes of input terminal (correspond to) is：
Lane data 1：
(1、2、241、242、3、4、243、244、……、237、238、437、438、239、240、479、480)；
Lane data 2：
(481、482、721、722、483、484、723、724、……、717、718、957、958、719、720、959、
960)；
Lane data 3：
(961、962、1201、1202、963、964、1203、1204、……、1137、1138、1437、1438、1139、
1200、1439、1440)；
Lane data 4：
(1441、1442、1681、1682、1443、1444、1683、1684、……、1677、1678、1917、1918、
1679、1680、1919 1920)；
Lane data 5：
(1921、1922、2161、2162、1923、1924、2163、2164、……、2157、2158、2397、2398、
2159、2160、2399、2400)；
Lane data 6：
(2401、2402、2641、2642、2403、2404、2643、2644、……、2637、2638、2877、2878、
2639、2640、2879、2880)；
Lane data 7：
(2881、2882、3121、3122、2883、2884、3123、3124、……、3117、3118、3357、3358、
3119、3120、3359、3360)；
Lane data 8：
(3361、3362、3661、3662、3363、3364、3663、3664、……、3357、3358、3837、3838、
3359、3360、3839、3840)；
For 32lane modules, module 6 can export 1~8 signal replication of lane data on 1 tunnel simultaneously, can light 1 piece simultaneously
32lane modules.
So RGB data is aligned on the Lane data signal lines of each road output so that the data of every four lane according to
Secondary alternate mixing is arranged on every circuit-switched data signal；Module for other various lane numbers and split screen module and right
In the module of 8k or 10k resolution ratio, the operating principle of the arrangement of module 6 and output lane data modes is identical as appeal.
(8) under the control of above-mentioned sequential corresponding with lane data, V-BY-ONE image synchronization modules 7 are to V-BY-ONE
Each road lane data that each Lane image datas generation module 6 exports carry out caching and synchronization process, to ensure each of a screen
Lane signals keep synchronous completely；
In order to adapt to the characteristic of V-BY-ONE modules high-resolution, high field frequency, stringent image sequential, cause module 6 defeated
The lane data-signals gone out are more, and very big per the data volume of road image, and data processing clock speed is very high, in specific electronics
When being realized on device (FPGA, ASIC or High-Speed PCB), the data-signal of each road output may be in the different zones of the device
Operation is completed, due to the difference or variation of device inside technique or external operating environment, between the operation that different zones are completed
With signal phase difference, time sequence difference, electrical differences；
To ensure the reliable and stable work of subsequent module, ensuring that each lane signals of screen strictly keep synchronous, pass through mould
Block 7 cached with it is synchronous；Each road lane data-signals are first cached several rows, together by module 7 under the control of input timing signal
When, de-jitter is carried out to the sequential of input, improves the stringency and stability of its sequential；Again in a new start of line,
In the case where stablizing the control of treated clock signal, each road lane data are exported simultaneously, ensure that each road lane data guarantor
Hold synchronization；
(9) while module 7 carries out above-mentioned synchronization process, V-BY-ONE image sequential computing module 8 is to each lane numbers
Be detected according to corresponding clock signal, and obtain time sequence parameter, including the crop of pixel clock frequency, line frequency/field frequency, after
Shoulder, virtual value, pulsewidth；
(10) V-BY-ONE images sequential multiplication modules 9 are according to V-BY-ONE field frequencies multiplication arrange parameter, to above-mentioned sequential
Parameter and the corresponding clock signal of each lane data of V-BY-ONE from module 6 carry out field frequency process of frequency multiplication, obtain V-
BY-ONE multiplication sequential and parameter；
For example top level control parameter configuration is 4 multiple field frequencys, and external image signal source is 30Hz field frequencies and its corresponding picture
Plain clock frequency and time sequence parameter, V-BY-ONE image sequential multiplication modules 9 then export the field frequency of 120H and its corresponding pixel
Clock frequency and time sequence parameter；
(11) V-BY-ONE signal output modules 10 are according to V-BY-ONE signal output parameters, to the lane after synchronization process
Data and sequential carry out multiple field frequency processing, and by multiple field frequency treated parallel each lane V-BY-ONE data conversions at V-
The lane of BY-ONE transmits signal；
Each module 10-1,2,3 ..., n multiple field frequency is carried out to wherein 1 road lane data, it is specific as follows：
Module 101 carries out local cache under the sequential of input to input data, to ensure that data can be done within the module 10
Local synchronization processing；Later when a frame originates, the data after caching are sent into module 102 under the sequential of input, and module 102 will
It is written in DDR memory modules 103A；When the roads a Zheng Zhonggai lane data are all written in module 103A, module 104
Control is written and read to the DDR of 103A, 103B by module 102 in the case where V-BY-ONE doubles timing control, is read from 103A
Lane data；
Module 102 carries out reading and data writing operation while controlling two DDR memory modules respectively, when some DDR is writing
When entering a certain frame lane data, while another DDR, in the data for reading previous frame, the two is alternately read in a manner of ping-pong operation
Write operation；And module 104 then presses the control of multiplication sequential and parameter, is being written in a frame time, repeatedly reads the lane of a frame
Data are sequentially arranged on the data-signal of lane0~lane3；In embodiment, upper-layer configured is 4 multiple field frequencys, then module
104 are redistributed to read lane data on each lane DDR memory modules with the read rate of 4 times of writing speeds, so
Operation 4 times realizes the 4 frequencys multiplication operation of output field frequency 120Hz；
Since the total throughout of write-in with the reading of DDR is identical, therefore module 102 and 104 can continuously carry out each lane numbers
According to multiple field frequency operation, be not in because DDR write it is full or the problem of read the occurred loss of data of empty problem or operation pause；Work as mould
Each lane data are then output to module 105 by block 104 simultaneously after distributing each lane data, and module 105 is according to upper layer
The V-BY-ONE signal output parameters of configuration, such as stringization coding mode, preemphasis, driving current, output bit bit wides, to each
Data parallel lane carry out the stringization processing of V-BY-ONE, are converted into the lane transmission signals of V-BY-ONE.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all within the spirits and principles of the present invention made by all any modification, equivalent and improvement etc., should all include
Within protection scope of the present invention.
Claims (6)
1. a kind of signal conversion method, which is characterized in that include the following steps：
(1) the RGB image signal of link each to each image signal source is combined, and generates original V-BY-ONE image datas；And
By being assigned on each link in turn of the V-BY-ONE image datas successively, generate parallel standardized more link's
V-BY-ONE image datas and corresponding V-BY-ONE lane sequential；
The RGB image signal of each link of each image signal source is obtained according to following steps：
(a) the LVDS picture signals of each link of each image signal source are demodulated, generates the parallel solution of each link
Adjusting data；
(b) the parallel demodulation data are cached so that each link data of output are the number of image line field synchronization
According to；
(c) RGB decodings are carried out to the data of described image row field synchronization, obtains the RGB image letter of each link of each image signal source
Number；
(2) data array conversion is carried out to standardized each V-BY-ONE image datas and sequential, obtains V-BY-
Each lane data of ONE data formats, and sequential corresponding with each lane data；
(3) under the control of sequential corresponding with each lane data, caching and synchronization process are carried out to each lane data, with true
Each lane signals for protecting point screen keep synchronizing；
(4) while above-mentioned synchronization process, the corresponding clock signal of each lane data is detected, obtains time sequence parameter；
(5) field frequency process of frequency multiplication is carried out to the corresponding clock signal of each lane data of the time sequence parameter and V-BY-ONE,
Obtain V-BY-ONE multiplication sequential and parameter；
(6) it to the lane data and sequential after synchronization process, is read simultaneously by caching, under the timing control that doubles with setting speed
It is assigned to each lane and realizes multiple field frequency processing, then treated that V-BY-ONE data parallel each lane are gone here and there by multiple field frequency
Change processing is converted into the lane transmission signals of V-BY-ONE；The step (6) is specific as follows：
(6.1) local cache is carried out to input data；
(6.2) when a frame originates, memory module is written into the data after caching；
(6.3) after the roads a Zheng Zhonggai lane data have all stored, in the case where V-BY-ONE doubles timing control in write-in one
It in the period of frame lane data, repeats to read lane data M times with the speed of M times of writing speed, and by the lane numbers of reading
According to being sequentially allocated on each lane, parallel lane data are formed；M one frame lane data of reading, are sequentially arranged in
On the data-signal of lane0~lane n, the M frequencys multiplication operation of output field frequency is realized；Wherein, M=4,8,16 or 32；
(6.4) after each lane data distribute, stringization processing is carried out to parallel lane data, by the parallel data of each lane
It is converted into the lane transmission signals of V-BY-ONE.
2. signal conversion method as described in claim 1, which is characterized in that in the step (1), to different display Lane numbers
V-BY-ONE modules, the link numbers for exporting image are different, specific as follows：
When being 4Lane V-BY-ONE modules by a module for screen, then original V-BY-ONE image datas are put into single link
Upper output exports list link data；
When being 8Lane V-BY-ONE modules by a module for screen, then original V-BY-ONE images are distributed to link numbers in pairs
According to；
If being 16lane V-BY-ONE modules by a module for screen, original V-BY-ONE images are distributed into four link data；
If being 32lane V-BY-ONE modules by a module for screen, original V-BY-ONE images are distributed into eight link data.
3. signal conversion method as described in claim 1, which is characterized in that the step (3) is specific as follows：In clock signal
Under control, each lane data-signals are first cached；While caching, de-jitter is carried out to the sequential of input, is improved at that time
The stringency and stability of sequence；In a new start of line, under the clock signal control after debounce, simultaneously by each lane data
Output.
4. signal conversion method as described in claim 1, which is characterized in that single using two storages in the step (6.3)
Member carries out reading data simultaneously and writes the operation of data respectively：The same of a certain frame lane data is written in a storage unit wherein
When, another storage unit reads the data of previous frame；The two alternately read-write operation in a manner of ping-pong operation.
5. a kind of chromacoder, which is characterized in that including LVDS signal input interfaces, V-BY-ONE signal output interfaces,
Upper layer software (applications) controls signal input interface, and the V-BY-ONE image-restoration modules being solidificated in a programmable logic device
(5), when each Lane image datas generation modules (6) of V-BY-ONE, V-BY-ONE image synchronization modules (7), V-BY-ONE images
Sequence computing module (8), V-BY-ONE image sequential multiplication modules (9) and V-BY-ONE signal output modules (10)；The V-BY-
ONE signal output modules (10) include at least one V-BY-ONE signal generator modules；Further include high-level interface module (1),
LVDS signal processing modules and LVDS image generating modules (4)；
The programmable logic device has a LVDS signal input terminals for coupling the LVDS signal input interfaces, described in coupling
The V-BY-ONE signal output terminals of V-BY-ONE signal output interfaces, and the coupling upper layer software (applications) control signal input connect
Upper layer software (applications) control signal input of mouth；
The high-level interface module (1) is used to generate all kinds of parameters according to upper-layer configured；The LVDS signal processing modules are used for
The LVDS picture signals of each link are carried out receiving demodulation and be cached, the data of image line field synchronization are generated；The LVDS images
Generation module (4) is used to carry out RGB decodings to the data of described image row field synchronization, obtains each link of each image signal source
RGB image signal；
RGB image signal of the V-BY-ONE image-restoration modules (5) for link each to each image signal source is combined,
It generates original V-BY-ONE images, and being assigned on each link in turn by the image data successively, generates parallel mark
The V-BY-ONE image datas of more link of standardization and corresponding V-BY-ONE lane sequential；
Each Lane image datas generation modules (6) of V-BY-ONE be used for the data of standardized each link and when
Sequence carries out data array conversion, obtains each lane data of V-BY-ONE data formats, and corresponding with each lane data
Sequential；The V-BY-ONE image synchronization modules (7) are for being cached and being synchronized to each lane data；
The V-BY-ONE images sequential computing module (8) is used for the corresponding clock signal of each lane data after the caching
It is detected, obtains time sequence parameter；The V-BY-ONE images sequential multiplication modules according to for the time sequence parameter and
V-BY-ONE lane sequential carries out field frequency process of frequency multiplication, obtains V-BY-ONE multiplication sequential and parameter；
The V-BY-ONE signal output modules (10) are used for the lane data and sequential after synchronization process, by caching,
It is read with setting speed under multiplication timing control and is assigned to each lane and realize multiple field frequency processing, then the number parallel to each lane
It is handled according to stringization is carried out；
The V-BY-ONE signal generator modules include image data cache module (101), image data Read-write Catrol module
(102), memory module (103), V-BY-ONE image field frequency multiplication modules (104), V-BY-ONE signal output sub-modules
(105)；
Described image data cache module (101) is used to carry out local cache to each lane data received；Described image number
Data write-in memory module (103) after being used to cache according to Read-write Catrol module (102)；The V-BY-ONE images field frequency times
Increase module (104) to be used to be written and read control to memory module (103) by image data Read-write Catrol module (102) module；
The V-BY-ONE signals output sub-module (105) carries out stringization processing for the data parallel to each lane.
6. chromacoder as claimed in claim 5, which is characterized in that the memory module (103) includes arranged side by side
One storage unit (103A) and the second storage unit (103B)；First storage unit (103A) and the second storage unit
(103B) is used to the lane data after memory buffers.
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| CN107358928B (en) * | 2017-08-21 | 2022-12-23 | 武汉精测电子集团股份有限公司 | Ultrahigh resolution graphics signal generator and starting and upgrading method thereof |
| KR102371823B1 (en) * | 2017-12-04 | 2022-03-07 | 주식회사 엘엑스세미콘 | Method for transmitting and receiving data in display device and display panel driving apparatus |
| CN108206017B (en) * | 2018-01-25 | 2020-08-11 | 广州晶序达电子科技有限公司 | Method and system for improving screen jumping of liquid crystal panel |
| WO2019153264A1 (en) * | 2018-02-09 | 2019-08-15 | 深圳开阳电子股份有限公司 | Iimage pre-processing method and device, image sensor interface, image processing method and device |
| CN111355914B (en) * | 2018-12-24 | 2021-09-21 | 珠海格力电器股份有限公司 | Video system signal generating device and method |
| CN109817129A (en) * | 2019-01-28 | 2019-05-28 | 武汉精立电子技术有限公司 | A kind of liquid crystal module detection system and method realized based on Mipi CPHY interface |
| CN111988554B (en) * | 2019-05-22 | 2022-05-27 | 瑞芯微电子股份有限公司 | Method and terminal for sampling multi-partition data of display equipment |
| CN110431616B (en) * | 2019-06-21 | 2024-04-19 | 京东方科技集团股份有限公司 | Picture frame display apparatus and display method |
| CN110570793B (en) * | 2019-08-05 | 2022-05-13 | 武汉精立电子技术有限公司 | Testing method and device adaptive to different types of display screens and terminal equipment |
| CN112492247B (en) * | 2020-11-30 | 2023-02-03 | 天津津航计算技术研究所 | Video display design method based on LVDS input |
| CN112667189B (en) * | 2020-12-28 | 2023-03-21 | 深圳市欣润京科技有限公司 | Method and system for realizing identification split screen mode by adopting display split test card |
| CN113674667A (en) * | 2021-08-09 | 2021-11-19 | Tcl华星光电技术有限公司 | Display device and mobile terminal |
| CN115190330A (en) * | 2022-07-02 | 2022-10-14 | 海的电子科技(苏州)有限公司 | Image signal processing method and device |
| CN115862506B (en) * | 2023-01-26 | 2023-05-05 | 海的电子科技(苏州)有限公司 | Dot screen method, image signal processing apparatus, and storage medium |
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