CN108898983B - Video signal extension system and method - Google Patents
Video signal extension system and method Download PDFInfo
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- CN108898983B CN108898983B CN201810765469.2A CN201810765469A CN108898983B CN 108898983 B CN108898983 B CN 108898983B CN 201810765469 A CN201810765469 A CN 201810765469A CN 108898983 B CN108898983 B CN 108898983B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
The invention discloses a video signal extension system and a method thereof, wherein the video signal extension method comprises the following steps: s1: acquiring video source data, splitting or copying the video source data according to configuration information of a liquid crystal module to be tested, and generating N-channel pixel data; s2: generating a packet effective signal and a synchronous signal according to the main Timing, and packaging the synchronous signal and one path of pixel data into a data packet; s3: synchronously converting the N data packets into N paths of high-speed serial data; s4: receiving high-speed serial data, and synchronously analyzing the N paths of high-speed serial data into N paths of pixel data according to effective data and a synchronous signal; the invention can divide or copy the video data into N paths of pixel data, package and serialize the pixel data, and transmit the pixel data to a plurality of extension signal generators synchronously at high speed and with low time delay, thereby realizing the real-time synchronous point screen test of the liquid crystal module and meeting the multi-channel test requirements of the liquid crystal modules in various resolution modes.
Description
Technical Field
The invention belongs to the technical field of signal generator design, and particularly relates to a video signal expansion system and a video signal expansion method.
Background
With the development of liquid crystal module technology, the resolution of the liquid crystal module is rapidly improved, and large-size liquid crystal modules with super-large resolutions such as 8K, 10K and the like appear in succession; with the development of the ultra-large resolution liquid crystal module, in order to realize the research, development, production and test of the liquid crystal module, new requirements are provided for the signal generator supporting the ultra-large resolution liquid crystal module.
When a liquid crystal module manufacturer carries out a point screen test on a liquid crystal module LCM with ultra-large resolution (8Kx4k 120HZ), a graphic signal generator is required to synchronously send 8-channel video signals to the liquid crystal module. Meanwhile, in order to save cost, it is desirable that One graphics signal generator can output video signals (such as DP, HDMI, V-by-One, etc.) with other resolutions (such as 4k × 2k and below) in multiple channels as much as possible. However, the design and production cost of the graphic signal generator are limited, the conventional graphic signal generator can not satisfy the requirement of synchronously outputting 8K × 4K 120HZ 8-channel video signals, and the number of output channels of video signals with other resolutions is also limited.
Disclosure of Invention
Aiming at least one defect or improvement requirement in the prior art, the invention provides a video signal expansion system and a video signal expansion method, which can divide or copy video data into N paths, package and serialize the video data, and transmit the video data to a plurality of expansion signal generators synchronously at high speed and with low time delay, thereby realizing real-time synchronous point screen test of a liquid crystal module and meeting the multi-channel test requirement of the liquid crystal module in various resolution modes.
To achieve the above object, according to one aspect of the present invention, there is provided a video signal extension system including a pixel data processing unit, a register, N data packing units, N data transmission units, and N extension signal generators respectively communicating with the data transmission units through a high-speed serial transceiver; wherein N is a natural number greater than 1;
the pixel data processing unit is used for acquiring video source data according to a test starting command of an external upper computer, splitting or copying the video source data according to configuration information of a liquid crystal module to be tested in a register and generating N-path pixel data; the configuration information comprises time sequence parameter information, channel number and video distribution mode; when the pixel data processing unit executes the copy operation, the value of N is a natural number which is larger than 1; when the pixel data processing unit performs a copy operation, N is 2nWherein n is a natural number greater than or equal to 1;
the data packaging unit is used for generating a packet effective signal and a synchronous signal according to the time sequence parameter information and packaging the synchronous signal and a path of pixel data into a data packet according to the time sequence requirement of an input interface of the data sending unit; the data packet is converted into high-speed serial data through the data sending unit, and N data sending units synchronously send N paths of high-speed serial data to corresponding expansion signal generators through a high-speed serial transceiver;
the extension signal generator is used for analyzing one path of high-speed serial data into pixel data according to the packet effective data and the synchronous signals, and N paths of pixel data can be used for realizing 2N channel point screen test of the liquid crystal module.
Preferably, in the video signal extension system, the extension signal generator includes a data receiving unit, a data analyzing unit, and a pixel data storing unit;
the data receiving unit is used for packaging the high-speed serial data generated by the data sending unit into a data packet;
the data analysis unit is used for decapsulating the data packet according to a packet effective signal to obtain a synchronous signal, and analyzing the data packet according to the synchronous signal to obtain pixel data;
the pixel data storage unit is used for storing the pixel data generated by the data analysis unit in an external memory.
Preferably, in the video signal extension system, the data transmission unit includes a data demodulation module and a data coding module;
the data demodulation module is used for demodulating the data packet generated by the data encapsulation unit into high-speed parallel data according to a link layer packet encapsulation protocol;
and the data coding module is used for coding and serializing the high-speed parallel data according to a physical layer coding protocol to generate high-speed serial data.
Preferably, in the video signal extension system, the data transmission unit and the data reception unit perform data processing and transmission and reception based on SerialLite II protocol.
Preferably, in the video signal extension system, the data receiving unit includes a data decoding module and a data conversion module;
the data decoding module is used for decoding the received high-speed serial data according to a physical layer coding protocol to generate high-speed parallel data;
and the data conversion module is used for packaging the high-speed parallel data into a data packet according to a link layer packet packaging protocol.
Preferably, in the video signal extension system, the pixel data processing unit includes a timing generation module, a data reading module, and a data splitting module;
the time sequence generation module is used for acquiring pre-configured time sequence parameter information from a register according to a test starting command and generating a main time sequence Timing according to the time sequence parameter information;
the data reading module is used for reading video source data from an external memory according to the main Timing;
the data splitting module is used for splitting or copying the video source data into N paths according to the number of channels to be detected, a video distribution mode and a main time sequence Timing.
Preferably, the video signal expansion system further includes a Double Data Rate (DDR) synchronous dram and an expansion board;
the DDR memory is connected with the data reading module and is used for storing video source data sent by the main control equipment;
the input end of the expansion board is connected with the N expansion signal generators, and the output end of the expansion board is connected with the liquid crystal module to be tested and used for storing N paths of pixel data output by the N expansion signal generators; the expansion board is provided with a plurality of signal interfaces including DP, HDMI and VBYONE to adapt to liquid crystal modules with different signal types.
According to another aspect of the present invention, there is provided a video signal extension method including the steps of:
s1: acquiring video source data, splitting or copying the video source data according to configuration information of a liquid crystal module to be detected, and generating N-channel pixel data; the configuration information comprises a main Timing, a channel number and a video distribution mode;
s2: generating a packet effective signal and a synchronous signal according to the main Timing, and packaging the synchronous signal and one path of pixel data into a data packet according to the Timing requirement of a SerialLite II protocol;
s3: synchronously converting the N data packets into N paths of high-speed serial data;
s4: and receiving the high-speed serial data, and synchronously analyzing N paths of high-speed serial data into N paths of pixel data according to the effective data and the synchronous signals, wherein the N paths of pixel data can be used for realizing the 2N channel dot screen test of the liquid crystal module.
Preferably, the video signal extension method includes the following sub-steps in step S3:
s31: demodulating the N data packets into N paths of high-speed parallel data according to a link layer packet encapsulation protocol of a SerialLite II protocol;
s32: and coding and serializing the high-speed parallel data according to a physical layer coding protocol of a SerialLite II protocol to generate N paths of high-speed serial data.
Preferably, the video signal extension method includes the following sub-steps in step S4:
s41: decoding the N paths of high-speed serial data in the step S3 according to a physical layer coding protocol of a SerialLite II protocol to generate N paths of high-speed parallel data;
s42: and encapsulating the N paths of high-speed parallel data into N data packets according to a link layer packet encapsulation protocol of a SerialLite II protocol.
S43: the N data packets are decapsulated according to a packet effective signal to obtain synchronization, and N-path pixel data are obtained through analysis from the N data packets according to the synchronization signal;
s44: the N-way pixel data is stored in the expansion board.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
(1) the video signal extension system and the method thereof provided by the invention have the advantages that a pixel processing unit in a main signal generator splits or copies video source data into N paths of pixel data according to configuration information of a liquid crystal module to be tested and encapsulates the pixel data into a data packet through a data encapsulation unit, a data sending unit demodulates, codes and serializes the data packet and then can synchronously transmit the data packet to an extension signal generator at a high speed, and the pixel processing unit, the data encapsulation unit and the data sending unit are coordinated and matched to realize the splitting/copying and the high-speed and low-delay transmission of the video data; the system has good real-time performance and can meet the requirement of multi-channel point screen test of the high-resolution liquid crystal module.
(2) The video signal extension system and the video signal extension method provided by the invention adopt the serial Lite II protocol to realize the high-speed data transmission between the main signal generator and the plurality of extension signal generators, the highest rate 6375Mbps supported by single lane, the bandwidth is high, the data error rate between protocol boards is low, the transmission between the protocol boards is reliable, and the dot screen test efficiency of the high-resolution liquid crystal module can be improved.
(3) The video signal extension system and the method provided by the invention have the advantages that the video distribution method is flexible and changeable, the high-resolution image (8k multiplied by 4k 120HZ) can be split, the splitting mode can be matched, other resolutions and frame rate images can be copied, and the video signal extension system and the video signal extension method are suitable for wide range of requirements of resolutions with different sizes; the number of the paths of the extension signal generators can be configured at will according to the number of the high-speed serial interfaces of the main signal generator and the extension signal generator and equipment requirements, the expansibility is good, and test signals with different channel numbers can be provided for the liquid crystal module.
Drawings
Fig. 1 is a logic block diagram of a video signal extension system according to an embodiment of the present invention;
fig. 2 is a logic block diagram of a pixel data processing unit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a logic block diagram of a video signal extension system according to an embodiment of the present invention; as shown in fig. 1, the video signal extension system includes a main signal generator and 4 extension signal generators communicating with the main signal generator through a high-speed serial transceiver; the main signal generator and the extension signal generator realize the processing and receiving and sending of video signals through a SerialLite II protocol; the SerialLite II protocol is a lightweight protocol supporting transmission of data packets and data streams among chips, boards and back boards in an Intel FPGA. The SerialLite II protocol provides reliable and high-speed data transmission on a serial line with low gate number and low data delay, defines a packet encapsulation mode on a link layer and a data coding mode on a physical layer, and supports single lane rate: 622 to 6375 Mbps.
Before the screen dotting test, the main control equipment sends video source data, time sequence parameters, channel numbers and video distribution modes required by the liquid crystal module to be tested to the main signal generator through the Ethernet port, the main signal generator stores the video source data in the DDR memory, and the time sequence parameter information, the channel numbers and the video distribution modes are configured in the internal register; the time sequence parameter information comprises line-field synchronous width, front-back shoulder width and the like.
After the configuration is completed, the main control equipment sends out a test starting command, the main signal generator splits or copies video source data according to time sequence parameter information, channel number and a video distribution mode to generate 4 paths of pixel data, and synchronously converts each path of pixel data into high-speed serial data;
the expansion signal generator respectively resolves one path of high-speed serial data into pixel data, the pixel data of one path is divided into 2 channels to be output, and the 4 expansion signal generators synchronously send 4 paths of 8-channel pixel data to the liquid crystal module, so that 8-channel point screen testing of the liquid crystal module is realized.
The main signal generator comprises a pixel data processing unit, a register, 4 data packaging units and 4 data sending units;
the pixel data processing unit acquires a time sequence parameter and a channel number which are configured in advance from a register according to a test starting command, generates a main time sequence Timing according to the time sequence parameter, reads video source data stored in a DDR according to the main time sequence Timing, the channel number and a video distribution mode, and splits or copies the video source data into 4 paths; in this embodiment, the pixel data processing unit includes a timing generation module, a data reading module, and a data splitting module;
the Timing generation module acquires pre-configured Timing parameter information from a register according to a test starting command sent by the main control module, and generates a main Timing according to the Timing parameter information, wherein the main Timing comprises a Horizontal Synchronization (HS) signal, a Vertical Synchronization (VS) signal and a Data Enable (DE) signal;
the data reading module reads video source data from the main board DDR according to the main Timing and stores the video source data in an internal FIFO of the main signal generator; according to the main timing, the data reading module empties the FIFO when the VS is effective, video source data are read from the DDR of the main board in advance and written into the FIFO when the FIFO is not full, the bit width of the FIFO is 512bit, and each beat of data comprises 16 pixel points.
The data splitting module splits or copies the video data into 4 paths of pixel data according to the main Timing, the number of channels and the video distribution mode; each path of pixel data comprises four pixel points;
(a) under the 8Kx4k resolution mode, splitting video source data into four paths of pixel data, wherein one path of pixel data comprises four pixel points; and dividing video source data read from the DDR into four parts according to a video distribution mode configured in a register, wherein each part comprises four pixel points.
The specific implementation method comprises the following steps: reading out the data of 16 pixel points in the internal FIFO of the main signal generator, if the data are configured to be distributed horizontally, the data splitting module reads 1/4 of 1 line of data each time and writes the data into the FIFO1, the FIFO2, the FIFO3 and the FIFO4 in sequence for buffering; after 1 line of data is written, the data in the FIFOs 1-4 are read out in turn according to the time sequence of DE to form four paths of parallel data. If the data are allocated to the Chinese character 'tian' lattice allocation, the data splitting module writes the front 1/2 of the front 1/2 field data into a FIFO1 for buffering, writes the rear 1/2 of the front 1/2 field data into a FIFO2 for buffering, writes the front 1/2 of the rear 1/2 field data into a FIFO3 for buffering, and writes the rear 1/2 of the rear 1/2 field data into a FIFO4 for buffering; after the 2-line data is written, the data in the FIFOs 1-4 are read out alternately according to the timing of DE, and the data read out in this way is in a grid form.
(b) Under other resolution modes, video source data is copied into four paths of pixel data, and one path of pixel data comprises four pixel points; the specific implementation method comprises the following steps: reading 16 pixel point data in an internal FIFO of a main signal generator, writing the data into a rear stage FIFO in 4 beats, writing 4 pixel points at a time, reading and copying the 4 pixel point data into 4 parts when DE is effective, and generating 4 paths of pixel data, wherein each path comprises four pixel points.
The data packaging unit generates a packet effective signal and a synchronous signal according to the main Timing, and packages the synchronous signal and one path of video data into a data packet according to the input interface Timing requirement of the data sending unit; generating a start encapsulation signal when the DE rises, generating an end encapsulation signal when the DE falls, and generating a packet valid signal when the DE is 1, wherein the packet valid signal is used for indicating that a data packet is valid and is transmitted to a data transmitting unit in parallel with a data packet instrument; the data encapsulation unit encapsulates the data of the four pixel points into an effective data packet with a data bit width of 128 bits according to the time sequence requirement of a data packet input interface of a SerialLite II protocol; the effective data packet with the 128-bit width comprises four pixel point data, the bit width of one pixel point is 30 bits, and in the remaining 8 bits, the bit width is set to be 1bit higher to indicate that DE is effective; when the VS signal is effective, at the beginning of a VS (low effective) falling edge, a 128-byte synchronous packet is generated through a counter, the DE effective signal is set to be low, the higher 1bit indicates that the VS is effective, and an effective data packet and the synchronous packet are packaged, so that the pixel data, the DE effective signal and the VS effective signal are packaged into a data packet.
The data transmitting unit converts the data packet generated by the data packaging unit into high-speed serial data and transmits the high-speed serial data to the extended signal generator through the high-speed serial transceiver. In this embodiment, the data transmitting unit includes a data demodulating module and a data encoding module;
the data demodulation module demodulates the data packet generated by the data encapsulation unit into high-speed parallel data according to a link layer packet encapsulation protocol defined by the serialLite II; the function of the data demodulation module can be realized by a SerialLite II IP kernel provided by Intel; the data coding module codes and serializes the high-speed parallel data according to a physical layer coding protocol defined by the serialLite II to generate high-speed serial data, and the high-speed serial data is sent to the expansion signal generator through the high-speed serial transceiver; the function of the data encoding module can be realized by a Transceiver Native PHY IP core provided by Intel.
In the embodiment, the same data packaging unit and data sending unit are instantiated into four parts, and 16 paths of pixel point data can be synchronously sent to four extension signal generators; according to the number of high-speed serial interfaces of the main signal generator and the extension signal generator and the test requirements, the number of paths of the data packaging unit and the data sending unit can be adjusted to meet the requirement that a liquid crystal module needs multi-channel test signals.
The extension signal generator comprises a data receiving unit, a data analyzing unit and a pixel data storage unit;
the data receiving unit is used for packaging the high-speed serial data generated by the data sending unit into a data packet; in this embodiment, the data receiving unit includes a data decoding module and a data conversion module;
the data decoding module receives the high-speed serial data sent by the data coding module through the high-speed serial transceiver, decodes the high-speed serial data according to a physical layer coding protocol defined by the serial Lite II and converts the high-speed serial data into high-speed parallel data; the function of the data decoding module can be realized by a Transceiver Native PHY IP kernel provided by Intel; and the data conversion module encapsulates the high-speed parallel data generated by the data decoding module into a data packet according to a link layer packet encapsulation protocol defined by the serialLite II.
The data analysis unit decapsulates the data packet according to the packet effective signal to reversely restore VS and DE effective signals, and analyzes the data packet from the effective data packet according to the DE effective signals to obtain pixel data;
the pixel data storage unit is used for buffering the pixel data generated by the data analysis unit in an internal FIFO of the expansion signal generator and then writing the pixel data into the expansion board.
The expansion board is connected with the liquid crystal module to be tested and stores four paths of pixel data output by the four expansion signal generators; the expansion board has multiple signal interfaces including DP, HDMI and VBYONE, and can adapt to liquid crystal modules of different signal types. The expansion board splits or copies one path of pixel data into two channels according to the requirements of the liquid crystal module and outputs the two channels to the liquid crystal module for point screen testing.
The embodiment also provides a video signal extension method, which comprises the following steps:
s1: acquiring video source data, splitting or copying the video source data according to configuration information of a liquid crystal module to be tested, and generating 4-path pixel data; the configuration information comprises a main Timing, a channel number and a video distribution mode; the method specifically comprises the following substeps:
s11: acquiring pre-configured time sequence parameter information from a register according to a test starting command of an external upper computer, and generating a main time sequence Timing according to the time sequence parameter information, wherein the main time sequence Timing comprises an HS signal, a VS signal and a DE signal;
s12: reading video data from an external memory according to a main Timing;
s13: and splitting or copying the video source data into 4 paths of pixel data according to the preset number of channels, a video distribution mode and a main time sequence Timing.
S2: generating a packet effective signal and a synchronous signal according to the main Timing, and packaging the synchronous signal and one path of pixel data into a data packet according to the Timing requirement of a SerialLite II protocol;
s3: synchronously converting the 4 data packets into 4 paths of high-speed serial data; the method specifically comprises the following substeps:
s31: demodulating 4 data packets into 4 paths of high-speed parallel data according to a link layer packet encapsulation protocol of a SerialLite II protocol;
s32: and coding and serializing the high-speed parallel data according to a physical layer coding protocol of a SerialLite II protocol to generate 4-path high-speed serial data.
S4: receiving high-speed serial data, and synchronously analyzing the 4-path high-speed serial data into 4-path pixel data according to the packet valid data and the synchronous signal; the method specifically comprises the following substeps:
s41: decoding the 4-path high-speed serial data in the step S3 according to a physical layer coding protocol of a SerialLite II protocol to generate 4-path high-speed parallel data; and encapsulating the 4-way high-speed parallel data into 4 data packets according to a link layer packet encapsulation protocol of a SerialLite II protocol.
S42: synchronously decapsulating 4 data packets according to the packet effective signals to reversely recover VS and DE effective signals, and analyzing the effective data packets according to the DE effective signals to obtain pixel data;
s43: the 4-way pixel data is stored in the expansion board.
The video signal expansion system and method based on SerialLite II protocol provided by the invention, a pixel processing unit in a main signal generator splits or copies video source data into N paths of pixel data according to configuration information of a liquid crystal module to be tested and packages the pixel data into a data packet through a data packaging unit, a data sending unit demodulates, codes and serializes the data packet and then can synchronously transmit the data packet to an expansion signal generator at high speed, and the pixel processing unit, the data packaging unit and the data sending unit are coordinated and matched to realize the splitting/copying of the video data and the transmission at high speed and low time delay; the system has good real-time performance and can meet the requirement of multi-channel point screen test of the high-resolution liquid crystal module.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A video signal extension system is characterized by comprising a pixel data processing unit, N data packaging units, N data sending units and N extension signal generators which are respectively communicated with the data sending units; wherein N is a natural number greater than 1;
the pixel data processing unit is used for acquiring video source data according to a test starting command of an external upper computer, splitting or copying the video source data according to configuration information of a liquid crystal module to be tested, and generating N-channel pixel data; the configuration information comprises time sequence parameter information, channel number and video distribution mode;
the data packaging unit is used for generating a packet effective signal and a synchronous signal according to the time sequence parameter information and packaging the synchronous signal and a path of pixel data into a data packet according to the time sequence requirement of an input interface of the data sending unit; the data packet is converted into high-speed serial data through the data sending unit, and N data sending units synchronously send N paths of high-speed serial data to corresponding expansion signal generators through a high-speed serial transceiver; the data sending unit comprises a data demodulation module and a data coding module;
the data demodulation module is used for demodulating the data packet generated by the data encapsulation unit into high-speed parallel data according to a link layer packet encapsulation protocol;
the data coding module is used for coding and serializing the high-speed parallel data according to a physical layer coding protocol to generate high-speed serial data;
the extension signal generator is used for analyzing one path of high-speed serial data into pixel data according to the effective signal and the synchronous signal, and N paths of pixel data can be used for realizing 2N channel point screen test of the liquid crystal module.
2. The video signal extension system of claim 1, wherein the extension signal generator includes a data receiving unit and a data parsing unit;
the data receiving unit is used for packaging the high-speed serial data generated by the data sending unit into a data packet;
the data analysis unit is used for decapsulating the data packet according to a packet valid signal to obtain a synchronous signal, and analyzing the data packet according to the synchronous signal to obtain pixel data.
3. The video signal extension system of claim 2, wherein the data transmission unit and the data reception unit perform data processing and transceiving based on SerialLite II protocol.
4. The video signal extension system according to claim 2 or 3, wherein the data receiving unit includes a data decoding module and a data conversion module;
the data decoding module is used for decoding the received high-speed serial data according to a physical layer coding protocol to generate high-speed parallel data;
and the data conversion module is used for packaging the high-speed parallel data into a data packet according to a link layer packet packaging protocol.
5. The video signal extension system according to claim 1, wherein the pixel data processing unit includes a timing generation module, a data reading module, and a data splitting module;
the time sequence generation module is used for acquiring pre-configured time sequence parameter information from a register according to a test starting command and generating a main time sequence Timing according to the time sequence parameter information;
the data reading module is used for reading video source data from an external memory according to the main Timing;
the data splitting module is used for splitting or copying the video source data into N paths according to the number of channels to be detected, a video distribution mode and a main time sequence Timing.
6. The video signal expansion system according to claim 1 or 5, further comprising a memory and an expansion board;
the memory is connected with the pixel data processing unit and used for storing the video source data sent by the main control equipment;
the input end of the expansion board is connected with the N expansion signal generators, and the output end of the expansion board is connected with the liquid crystal module to be tested and used for storing N paths of pixel data output by the N expansion signal generators; the expansion board is provided with a plurality of signal interfaces including DP, HDMI and VBYONE to adapt to liquid crystal modules with different signal types.
7. A video signal extension method, comprising the steps of:
s1: acquiring video source data, splitting or copying the video source data according to configuration information of a liquid crystal module to be detected, and generating N-channel pixel data; the configuration information comprises time sequence parameter information, channel number and video distribution mode;
s2: generating a packet effective signal and a synchronous signal according to the time sequence parameter information, and packaging the synchronous signal and a path of pixel data into a data packet;
s3: convert N data package synchronous into N way high speed serial data, specifically include:
s31: demodulating the N data packets into N paths of high-speed parallel data according to a link layer packet encapsulation protocol of a SerialLite II protocol;
s32: coding and serializing the high-speed parallel data according to a physical layer coding protocol of a SerialLite II protocol to generate N paths of high-speed serial data;
s4: and receiving the high-speed serial data, and synchronously analyzing N paths of high-speed serial data into N paths of pixel data according to the effective signal and the synchronous signal, wherein the N paths of pixel data can be used for realizing the 2N channel point screen test of the liquid crystal module.
8. The video signal extension method of claim 7, wherein the step S4 includes the sub-steps of:
s41: decoding the N paths of high-speed serial data in the step S3 according to a physical layer coding protocol of a SerialLite II protocol to generate N paths of high-speed parallel data;
s42: packaging the N paths of high-speed parallel data into N data packets according to a link layer packet packaging protocol of a SerialLite II protocol;
s43: and unpacking the N data packets according to the packet effective signals to acquire synchronization, and analyzing the N data packets according to the synchronization signals to obtain N paths of pixel data.
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