CN104809996A - Method and device for achieving data signals of various LANE numbers of MIPI (mobile industry processor interface) based on FPGA (field programmable gate array) - Google Patents
Method and device for achieving data signals of various LANE numbers of MIPI (mobile industry processor interface) based on FPGA (field programmable gate array) Download PDFInfo
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Abstract
The invention discloses a method and a device for achieving data signals of various LANE numbers of an MIPI (mobile industry processor interface) based on an FPGA (field programmable gate array). The method includes 1), receiving MIPI configuration information from an upper layer to perform configuration operation, wherein the MIPI configuration information includes the LANE numbers of an MIPI module, a module screen-splitting mode, RGB (red-green-blue) bit width, MIPI transmission control parameters and MIPI output electrical configuration; 2), converting input RGB video signals into four-channel screen-splitting video data; 3), converting the four-channel screen-splitting video data into four-channel byte data; 4), packing the four-channel byte data to form four-channel MIPI packed data; 5), allocating the four-channel MIPI packed data to each data LANE to form MIPI signals; 6), subjecting the MIPI signals of each data LANE to MIPI transmission operation; 7), subjecting the MIPI signals of each data LANE to output electrical and transmission characteristic adjustment, and then sending the MIPI signals of each data LANE to the module. The method and the device have the advantages that output of the MIPI signals of 1-LANE, 2-LANE, 3-LANE, 4-LANE, 8-LANE and 16-LANE is achieved through the FPGA to lighten the module, and the method and the device are simple to operate, high in reliability and quite low in cost.
Description
Technical field
The present invention relates to display and the field tests of MIPI liquid crystal module, refer to a kind of method and apparatus realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA particularly.
Background technology
MIPI show module (hereinafter referred to as module) be a kind of display device be widely used on various portable display device and mobile phone, this kind of module and MIPI vision signal used thereof have low in energy consumption, reliability is high, transfer rate is high, can adapt to the feature of different size resolution.
When showing the video image of medium and small resolution, the MIPI data line that vision signal can be assigned to 1 to 4 LANE gives module, and the higher data volume of video resolution is larger, and the MIPI data line LANE number that its vision signal is assigned to is also more.When showing the video image of ultra high-definition resolution, the video data volume is huge, more LANE number is needed to transmit and higher transfer rate, but due to MIPI agreement the LANE number of single standardization module limited to the restriction of the transfer rate of (1 to 4 LANE numbers) and each LANE, therefore occurred 8LANE or 16LANE MIPI module and transmission mode.
The transmission mode ultimate principle of the MIPI module of 8LANE or 16LANE is said that wanted display video image carries out split screen process (as left and right half split screen by certain mode exactly, odd even pixel split screen etc.), thus complete video image is divided into two or four split screen video data, accordingly, the MIPI module of 8LANE or 16LANE is also divided into two or four submodule group, for guaranteeing maximum transmission of video rate, each submodule group self is then the standard module of 4LANE, therefore split screen video data is transferred in each submodule group by correspondence, they are carried out merging to demonstrate normal pictures by MIPI module more afterwards.
But at present in the production of this type of MIPI module product, debugging, testing process, still use the MIPI image generation device of standard module, the view data namely needing plurality of devices to produce different split screen sends into the complete display of module simultaneously.So not only troublesome poeration, each split screen image synchronization difficulty, be easy to make mistakes, Detection results is undesirable and throughput rate is lower.
Summary of the invention
For the deficiencies in the prior art, the object of this invention is to provide a kind of signal being exported multiple MIPI data LANE number by a slice fpga chip, 1 can be realized to the method and apparatus realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA of the MIPI signal of 4LANE, 8LANE, 16LANE.
For achieving the above object, a kind of method realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA designed by the present invention, its special character is, comprises the steps:
1) receive MIPI configuration information from upper strata, be configured operation, described MIPI configuration information comprises MIPI module LANE number, module split screen mode, RGB bit wide, MIPI transmission control parameters and MIPI and exports electrical configurations;
2) according to the MIPI module LANE number in described MIPI configuration information and module split screen mode, the rgb video signal of input is converted to four road split screen video datas;
3) according to the RGB bit wide in described MIPI configuration information, four road split screen video datas are converted to four tunnel byte datas;
4) described four tunnel byte datas are packaged, form four road MIPI group bag data;
5) according to the MIPI module LANE number in described MIPI configuration information, described four road MIPI group bag data are assigned on each data LANE, form MIPI signal;
6) according to the MIPI transmission control parameters in described MIPI configuration information, MIPI transmission operation is carried out to the MIPI signal on described each data LANE;
7) according to the MIPI in described MIPI configuration information export electrical configurations to the MIPI signal on described each data LANE carry out outputs electrically and transport property adjust, then the MIPI signal on described each data LANE is sent to MIPI module displays.
Preferably, described step 2) also comprise the step of described four road split screen video data buffer memorys, to guarantee that subsequent module can synchronously operate afterwards.
Preferably, described step 2) in when described MIPI module LANE number is 1 ~ 4LANE, the rgb video signal of input is converted to the four full split screen video datas in road and exports; When described MIPI module LANE number is 8LANE, the rgb video signal of input is converted to four road 2 panes video datas and exports; When MIPI module LANE number is 16LANE, the rgb video signal of input is converted to four tunnel four split screen video datas and exports.The present invention can realize comprising the data-signal that LANE number is the MIPI module of 1,2,3,4,8,16.
Preferably, described step 3) after also comprise the step of described four tunnel byte datas being carried out to synchronous operation, the data that the interpolation bag correlation parameter avoiding preorder to operate producing causes are asynchronous.
Preferably, described step 6) in MIPI transmission operation comprise exporting according to the HS-LP sequential of the MIPI clock in described MIPI transmission control parameters and control MIPI signal on described each data LANE respectively with HS state and LP State-output.According to the regulation of MIPI DSI agreement, MIPI signal comprises HS state and LP state two kinds of transmission modes.
Preferably, described MIPI signal exports with LVDS signal electrical standard in HS state, exports with LVCOMS signal electrical standard in LP state.The present invention is based on FPGA to realize, therefore LVDS signal electrical standard is used to the HS status signal of clock, data and LP status signal adopts LVCMOS signal electrical standard, thus produce and meet the HS state of MIPI protocol specification, the signal transmission of LP state.
Preferably, described MIPI exports electrical configurations and comprises level range, drives intensity, termination matching, output impedance and carry high frequency to increase the weight of, to guarantee that module can receive the MIPI signal of the equal in quality of each LANE simultaneously, thus guarantee point screen effect.
Realize the above-mentioned device realizing the method for the data-signal of MIPI many kinds of LANE numbers based on FPGA, comprise MIPI control module, RGB data divides panel module, RGB turns MIPI module, MIPI group bag module, MIPI data LANE distribution module, transmitting synchronous control module and MIPI signal synchronous output module;
Described MIPI control module divides panel module with RGB data respectively, RGB turns MIPI module, MIPI group bag module, MIPI data LANE distribution module, transmitting synchronous control module and MIPI signal synchronous output module are connected, described RGB data divides panel module to turn MIPI module and MIPI group bag model calling by RGB, described MIPI group bag module is connected with MIPI data LANE distribution module, described MIPI data LANE distribution module is connected with MIPI signal synchronous output module by transmitting synchronous control module, and described MIPI signal synchronous output module is connected with MIPI module;
Described MIPI control module is used for MIPI configuration information, is configured operation;
Described RGB data divides panel module to be converted to four road split screen video datas for the rgb video signal just inputted;
Described RGB turns MIPI module for four road split screen video datas are converted to four tunnel byte datas;
Described MIPI group bag module is used for packaging to described four tunnel byte datas, forms four road MIPI group bag data;
Described four road MIPI group bag data are assigned on each data LANE by described MIPI data LANE distribution module, form MIPI signal;
Described transmitting synchronous control module is for carrying out MIPI transmission operation to the MIPI signal on described each data LANE;
MIPI signal on described each data LANE for carrying out output to the MIPI signal on described each data LANE electrically and transport property adjustment, and is sent to MIPI module by described MIPI signal synchronous output module.
Further, also comprise and divide panel module and the RGB RGB data synchronization module turning MIPI model calling respectively with RGB data, described RGB data synchronization module is used for described four road split screen video data buffer memorys.
Further, also comprise the MIPI data simultaneous module be connected with MIPI group bag module and MIPI data LANE distribution module respectively, described MIPI data simultaneous module is used for carrying out synchronous operation to described four tunnel byte datas.
Beneficial effect of the present invention is:
(1) the present invention realizes by the operative configuration of upper layer software (applications) the MIPI signal exporting Different L ANE number, in use can be applied directly to different MIPI module, without the need to other signal conversion equipments.
(2) the present invention not only supports the standard module of 1 to 4LANE, also supports 8LANE, 16LANE ultra high-definition MIPI module, only can input the rgb signal of a road complete picture to display, convert thereof into required 8LANE, 16LANE split screen data MIPI signal by upper-layer configured and send display.
(3) by inner synchro control, the present invention guarantees that the MIPI signal when exporting 8LANE, 16LANE split screen data-signal on each LANE all can arrive MIPI module simultaneously and guarantees that MIPI module correctly shows.
(4) the present invention is by realizing described function with fpga chip, not only working stability, reliability is high, realization is easy, and cost is lower, easy and simple to handle.
Accompanying drawing explanation
Fig. 1 the present invention is based on the block diagram that FPGA realizes the device of the data-signal of MIPI many kinds of LANE numbers.
Fig. 2 the present invention is based on the process flow diagram that FPGA realizes the method for the data-signal of MIPI many kinds of LANE numbers.
Fig. 3 is the allocation scheme schematic diagram according to MIPI DSI protocol specifies data LANE.
In figure: MIPI control module 1, RGB data divides panel module 2, and RGB data synchronization module 3, RGB turns MIPI module 4, MIPI group bag module 5, MIPI data simultaneous module 6, MIPI data LANE distribution module 7, transmitting synchronous control module 8, MIPI signal synchronous output module 9, MIPI module 10.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figure 1, a kind of device realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA provided by the present invention, comprises MIPI control module 1, RGB data divides panel module 2, RGB data synchronization module 3, RGB turn MIPI module 4, MIPI group bag module 5, MIPI data simultaneous module 6, MIPI data LANE distribution module 7, transmitting synchronous control module 8 and MIPI signal synchronous output module 9.
MIPI control module 1 divides panel module 2 with RGB data respectively, RGB turns MIPI module 4, MIPI group bag module 5, MIPI data LANE distribution module 7, transmitting synchronous control module 8 is connected with MIPI signal synchronous output module 9, RGB data is divided panel module 2 to turn MIPI module 4 by RGB data synchronization module 3 with RGB and is connected, RGB is turned MIPI module 4 and is connected with MIPI data simultaneous module 6 by MIPI group bag module 5, MIPI data simultaneous module 6 is connected with MIPI data LANE distribution module 7, MIPI data LANE distribution module 7 is connected with MIPI signal synchronous output module 9 by transmitting synchronous control module 8, MIPI signal synchronous output module 9 is connected with MIPI module 10.
MIPI control module 1, for MIPI configuration information, is configured operation.
RGB data divides panel module 2 to be converted to four road split screen video datas for the rgb video signal just inputted.
RGB data synchronization module 3 is for by four road split screen video data buffer memorys.
RGB turns MIPI module 4 for four road split screen video datas are converted to four tunnel byte datas.
MIPI group bag module 5, for packaging to four tunnel byte datas, forms four road MIPI group bag data.
MIPI data simultaneous module 6 is for carrying out synchronous operation to four tunnel byte datas.
Four road MIPI group bag data are assigned on each data LANE by MIPI data LANE distribution module 7, form MIPI signal.
Transmitting synchronous control module 8 is for carrying out MIPI transmission operation to the MIPI signal on each data LANE.
MIPI signal on each data LANE for carrying out output to the MIPI signal on each data LANE electrically and transport property adjustment, and is sent to MIPI module 10 by MIPI signal synchronous output module 9.
As shown in Figure 2, the concrete steps realizing the method for the data-signal of MIPI many kinds of LANE numbers according to said apparatus realization based on FPGA comprise:
1) MIPI control module 1 receives MIPI configuration information from the upper strata MIPI control signal on upper strata, and by MIPI configuration information feeding, RGB data divides panel module 2, RGB turns MIPI module 4, MIPI group bag module 5, MIPI data LANE distribution module 7, transmitting synchronous control module 8 and MIPI signal synchronous output module 9 are configured operation.MIPI configuration information comprise MIPI module LANE number (LANE number can be 1,2,3,4,8,16), module split screen mode (as half screen, odd even pixel split screen etc. are divided in left and right), RGB bit wide (as 6,8,10,12,16bit), MIPI transmission control parameters and MIPI export electrical configurations.
2) after configuration operation, MIPI control module 1 starts RGB data and divides panel module 2, and RGB data divides panel module 2, according to the split screen mode of the MIPI module LANE number in MIPI configuration information and MIPI module, the rgb video signal of input is converted to four road split screen video datas.
When described MIPI module LANE number is 1 ~ 4LANE, RGB data divides panel module 2 rgb video signal of input to be converted to the four full split screen video datas in road to export, by incoming video signal not split screen process directly copy four circuit-switched data and export; When described MIPI module LANE number is 8LANE, RGB data divides panel module 2 rgb video signal of input to be converted to four road 2 panes video datas outputs, namely 2 panes process is carried out, then copy two passages to export, as two split screen video datas that #1, #2 are a passage, #3, #4 are two split screen video datas of another passage; When MIPI module LANE number is 16LANE, RGB data divides panel module 2 rgb video signal of input to be converted to four tunnel four split screen video datas outputs, and namely carry out four split screen process, then 1 to 4 tunnels exported are corresponding four split screen video datas respectively.
3) RGB data divides panel module 2 that four road split screen video datas feeding RGB data synchronization modules 3 are carried out buffer memory to guarantee that subsequent module can synchronously operate.For avoiding inputted data because of transmission jitter or operation delay, RGB data synchronization module 3 is by after the frame data of its buffer memory half split screen, and RGB turns MIPI module 4 and taken out.
4) RGB turns MIPI module 4, according to the RGB bit wide in described MIPI configuration information, four road split screen video datas is converted to four tunnel byte datas.RGB turns MIPI module 4 according to the configuration of RGB bit wide, the RGB data of four road split screen video datas of input is changed into byte data and exports, when RGB bit bit wide is more than 1 byte, is then split into high low byte and exports successively.Simultaneously RGB turns MIPI module 4 and according to split screen mode configuration, can receive requirement process the module such as beginning, end, disjunction of video data, as added after split screen synchronizing information, ED the marks such as bonus point screen location of pixels before Data Start.
5) MIPI group bag module 5 to package operation to four tunnel byte datas, form four road MIPI group bag data, thus send into MIPI data simultaneous module 6 after changing into MIPI data and synchronously process, avoid operating that the interpolation bag correlation parameter that produces causes is asynchronous.
6) MIPI data LANE distribution module 7 to be distributed according to the MIPI module LANE number configuration in MIPI configuration information four road MIPI group bag data of synchronous input and is outputted to formation MIPI signal (referring to accompanying drawing 2) on each data LANE.When being configured to 4LANE, 8LANE, 16LANE module, 1,2,3,4 circuit-switched data orders of input are assigned in 1 to 4LANE, 5 to 8LANE, 9 to 12LANE, 13 to 16LANE respective signals by MIPI data LANE distribution module 7 successively; When being configured to 1LANE, 2LANE, 3LANE module, then the input of each road be assigned to each self-corresponding four LANE wherein 1,2, on 3LANE signal.
7) when the MIPI signal of each data LANE distributed is sent into transmitting synchronous control module 8 by MIPI data LANE distribution module 7, MIPI control module 1 controls configuration according to the characteristic that will export MIPI module 10 by MIPI transmission and carries out MIPI transmission operation to transmitting synchronous control module 8, and the HS-LP sequential as MIPI clock exports, the HS-LP sequential of each data Lane signal exports and synchronous, MIPI clock, data-signal phase mutually synchronization.Owing to being that FPGA realizes, therefore LVDS signal electrical standard is used to the HS status signal of clock, data and LP status signal adopts LVCMOS signal electrical standard.Thus produce HS, LP signal transmission meeting MIPI protocol specification.
8) the HS state of clock, data, the MIPI signal of LP state are sent into MIPI signal synchronous output module 9 by transmitting synchronous control module 8 respectively, the MIPI LANE signal that the HS state of each data LANE, the MIPI signal of LP state are merged into standard by MIPI signal synchronous output module 9 exports to the MIPI signal that the display of MIPI module 10, MIPI module 10 receives.Simultaneously MIPI signal synchronous output module 9 according to MIPI export electrical configurations to each data LANE signal carry out outputs electrically and transport property adjust, the i.e. characteristic of each web member of being connected with MIPI module 10 of basis or connecting line, to comprising level range, drive intensity, termination matching, output impedance, carry high frequency adds and focuses on interior various physics output characteristics and adjust, simultaneously, the output signal of different length to each data LANE according to each web member or connecting line makes different time delays, to guarantee that module can receive the MIPI signal of the equal in quality of each data LANE simultaneously, thus guarantee point screen effect.
Below be only the preferred embodiment of the present invention, it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention, can also design some improvement, these improvement also should be considered as protection scope of the present invention.
The content that this instructions is not described in detail belongs to the known prior art of professional and technical personnel in the field.
Claims (10)
1. realize a method for the data-signal of MIPI many kinds of LANE numbers based on FPGA, it is characterized in that: comprise the steps:
1) receive MIPI configuration information from upper strata, be configured operation, described MIPI configuration information comprises MIPI module LANE number, module split screen mode, RGB bit wide, MIPI transmission control parameters and MIPI and exports electrical configurations;
2) according to the MIPI module LANE number in described MIPI configuration information and module split screen mode, the rgb video signal of input is converted to four road split screen video datas;
3) according to the RGB bit wide in described MIPI configuration information, four road split screen video datas are converted to four tunnel byte datas;
4) described four tunnel byte datas are packaged, form four road MIPI group bag data;
5) according to the MIPI module LANE number in described MIPI configuration information, described four road MIPI group bag data are assigned on each data LANE, form MIPI signal;
6) according to the MIPI transmission control parameters in described MIPI configuration information, MIPI transmission operation is carried out to the MIPI signal on described each data LANE;
7) export electrical configurations according to the MIPI in described MIPI configuration information and outputs is carried out electrically and transport property adjustment to the MIPI signal on described each data LANE, then the MIPI signal on described each data LANE is sent to MIPI module (10) and shows.
2. the method realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA according to claim 1, is characterized in that: described step 2) also comprise the step of described four road split screen video data buffer memorys afterwards.
3. the method realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA according to claim 2, it is characterized in that: described step 2) in when described MIPI module LANE number is 1 ~ 4LANE, the rgb video signal of input is converted to the four full split screen video datas in road and exports; When described MIPI module LANE number is 8LANE, the rgb video signal of input is converted to four road 2 panes video datas and exports; When MIPI module LANE number is 16LANE, the rgb video signal of input is converted to four tunnel four split screen video datas and exports.
4. the method realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA according to claim 3, is characterized in that: described step 3) also comprise the step of described four tunnel byte datas being carried out to synchronous operation afterwards.
5. the method realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA according to claim 4, is characterized in that: described step 6) in MIPI transmission operation comprise exporting according to the HS-LP sequential of the MIPI clock in described MIPI transmission control parameters and control MIPI signal on described each data LANE respectively with HS state and LP State-output.
6. the method realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA according to claim 5, is characterized in that: described MIPI signal exports with LVDS signal electrical standard in HS state, exports with LVCOMS signal electrical standard in LP state.
7. the method realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA according to claim 6, is characterized in that: described MIPI exports electrical configurations and comprises level range, drives intensity, termination matching, output impedance and carry high frequency to increase the weight of.
8. realize the above-mentioned device realizing the method for the data-signal of MIPI many kinds of LANE numbers based on FPGA, it is characterized in that: comprise MIPI control module (1), RGB data divides panel module (2), RGB turns MIPI module (4), MIPI group bag module (5), MIPI data LANE distribution module (7), transmitting synchronous control module (8) and MIPI signal synchronous output module (9);
Described MIPI control module (1) divides panel module (2) respectively with RGB data, RGB turns MIPI module (4), MIPI group bag module (5), MIPI data LANE distribution module (7), transmitting synchronous control module (8) is connected with MIPI signal synchronous output module (9), described RGB data is divided panel module (2) to turn MIPI module (4) by RGB and is connected with MIPI group bag module (5), described MIPI group bag module (5) is connected with MIPI data LANE distribution module (7), described MIPI data LANE distribution module (7) is connected with MIPI signal synchronous output module (9) by transmitting synchronous control module (8), described MIPI signal synchronous output module (9) is connected with MIPI module (10),
Described MIPI control module (1), for MIPI configuration information, is configured operation;
Described RGB data divides panel module (2) to be converted to four road split screen video datas for the rgb video signal just inputted;
Described RGB turns MIPI module (4) for four road split screen video datas are converted to four tunnel byte datas;
Described MIPI group bag module (5), for packaging to described four tunnel byte datas, forms four road MIPI group bag data;
Described four road MIPI group bag data are assigned on each data LANE by described MIPI data LANE distribution module (7), form MIPI signal;
Described transmitting synchronous control module (8) is for carrying out MIPI transmission operation to the MIPI signal on described each data LANE;
MIPI signal on described each data LANE for carrying out output to the MIPI signal on described each data LANE electrically and transport property adjustment, and is sent to MIPI module (10) by described MIPI signal synchronous output module (9).
9. the device realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA according to claim 8, it is characterized in that: also comprise the RGB data synchronization module (3) dividing panel module (2) and RGB to turn MIPI module (4) to be respectively connected with RGB data, described RGB data synchronization module (3) is for by described four road split screen video data buffer memorys.
10. the device realizing the data-signal of MIPI many kinds of LANE numbers based on FPGA according to Claim 8 or described in 9, it is characterized in that: also comprise the MIPI data simultaneous module (6) be connected with MIPI group bag module (5) and MIPI data LANE distribution module (7) respectively, described MIPI data simultaneous module (6) is for carrying out synchronous operation to described four tunnel byte datas.
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