CN103581600A - Method for converting LVDS video signal into 8 LANE odd-even split screen MIPI video signals - Google Patents
Method for converting LVDS video signal into 8 LANE odd-even split screen MIPI video signals Download PDFInfo
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Abstract
The invention discloses a method for converting an LVDS video signal into 8 LANE odd-even split screen MIPI video signals. The method comprises the steps of firstly, respectively and simultaneously conducting receiving and demodulation on each link of the LVDS video signal, and generating parallel demodulation data and LVDS pixel clocks of the four links; secondly, conducting video decoding on the parallel demodulation data of the four links, and generating LVDS video source data and LVDS video source synchronizing signals of the four links; thirdly, generating RGB video clocks, dividing the LVDS video source data of the four links into odd pixel parallel data and even pixel parallel data, simultaneously reading the odd pixel parallel data, the even pixel parallel data and the synchronizing signals by the RGB video clocks, and respectively converting the odd pixel parallel data and the even pixel parallel data into RGB odd split screen video signals and RGB even split screen video signals; fourthly, simultaneously converting the RGB odd split screen video signals and the RGB even split screen video signals into a left-channel MIPI video signal and a right-channel MIPI video signal.
Description
Technical field
The present invention relates to demonstration field and the field tests of liquid crystal module, refer to that particularly a kind of LVDS vision signal is converted to 8LANE odd even split screen MIPI vision signal method.
Background technology
Liquid crystal display module (Liquid Crystal Display Module, hereinafter to be referred as liquid crystal module) is the critical component that liquid crystal display can normally show, it is by liquid crystal display screen, original paper backlight, Graphics Processing chip and the electric circuit constitute.Liquid crystal display module structure is accurate, processing procedure is complicated, manufacturing technique requirent is high, in order to guarantee yields when producing, need to produce various test video signals by special liquid crystal module testing apparatus and be input in liquid crystal module and show, strictly, comprehensively detect its display effect.Its display interface of common liquid crystals module of using on TV, display product at present and inner Graphics Processing circuit are used LVDS(Low-Voltage Differential Signaling, Low Voltage Differential Signal) signal carrys out work.And existing liquid crystal module testing device also corresponding output be that LVDS vision signal is to realize the test of module.Because common liquid crystals module production time is of a specified duration, output is large, so its module testing apparatus also uses in a large number.
Along with people constantly pursue high definition more, display effect more true to nature on mobile device, portable equipment, therefore common liquid crystals module cannot meet the need gradually.So occurred on market that a kind of novel liquid crystal module with ultrahigh resolution and very-high solution density meets people's demand.The interface of this liquid crystal module and inner Graphics Processing circuit adopt MIPI(Mobile Industry Processor Interface to move industry processor interface) signaling interface.This interface is formulated by the MIPI alliance that comprises the companies such as ARM, Samsung, Intel, object is that handle is mobile, inner each assembly of portable equipment is as nuclear interface standardizings such as camera, display screen, processors and opens each other, thereby improved performance, reduced cost and power consumption.MIPI interface can not only be supported ultrahigh resolution and refresh rate, and has farther transmission range, better Electro Magnetic Compatibility, and therefore the liquid crystal module with MIPI interface has become development trend.
Yet the testing apparatus of MIPI liquid crystal module need to be exported same MIPI test signal, but existing common liquid crystals module testing apparatus does not have this function, and common liquid crystals module also continues to produce, its testing apparatus does not enter the replacement cycle yet will be continued to use.Although module manufacturer also produces MIPI liquid crystal module, in order to protect investment, to reduce production costs, can not eliminate existing equipment, again make a big purchase expensive MIPI module Special testing device in large quantities.In order to produce cheaply MIPI liquid crystal module in enormous quantities within short-term and to guarantee its yields, just still reuse on a large scale existing common module testing apparatus.
Therefore, need a kind of technical scheme LVDS signal can be converted to the method for 8LANE odd even split screen type MIPI vision signal, common liquid crystals module testing apparatus can be tested MIPI module by this conversion equipment.
Summary of the invention
The object of the present invention is to provide a kind of LVDS vision signal to be converted to 8LANE odd even split screen MIPI vision signal method, it has feature simple to operate, that detection efficiency is high, cost is low.
For achieving the above object, the designed LVDS vision signal of the present invention is converted to 8LANE odd even split screen MIPI vision signal method, and its special character is, comprises the following steps:
Preferably, described LVDS vision signal comprises LINK1, LINK2, LINK3 and tetra-links of LINK4, described four links transmit LVDS vision signal successively according to video pixel order, the LVDS vision signal of described each link comprises LVDS receive clock and LVDS data, described LVDS data are transmitted by LVDS data/address bus, described LVDS data/address bus comprises some root holding wires, and every holding wire transmits serial code signal; Described MIPI vision signal comprises left passage MIPI vision signal and right passage MIPI vision signal, for the MIPI demonstration module of 8LANE odd even split screen type.
Preferably, before the vision signal of each link being carried out to receiving demodulation in described step 1, according to the characteristic of the LVDS vision signal that will receive, LVDS vision signal decoding parametric, synchronous mode control parameter are set; Receive the MIPI video conversion configurations parameter in LVDS vision signal, the configuration operation and the MIPI that carry out MIPI conversion process show module initialization operation; According to described LVDS vision signal decoding parametric, produce LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS video signal cable sequence control signal; According to described synchronous mode, control parameter generating LVDS synchronous mode control signal; According to described MIPI video conversion configurations parameter generating MIPI conversion initialization command and MIPI module initialization command.
Preferably, the process of in described step 1, the vision signal of each link being carried out to receiving demodulation comprises: to the serial code signal in described each link receiving be terminated respectively, demodulation, dynamic calibration, produce parallel demodulation data and LVDS pixel clock; The process of described termination comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild; The process of described demodulation comprises: described LVDS receive clock is carried out to demodulation, produce demodulation enable signal, the serial code signal of the LVDS data of each link is demodulated to separately to parallel data respectively simultaneously, and described LVDS receive clock is demodulated into described LVDS pixel clock simultaneously.
Preferably, the process of in described step 2, the parallel demodulation data of described four links being carried out to video decode comprises: with described LVDS pixel clock, the first buffer memory of the parallel demodulation data of described each link is synchronously read again, then the parallel demodulation decoding data to described four links respectively, the LVDS video source data and the LVDS video source synchronizing signal that obtain four links, described LVDS pixel clock is converted into LVDS video source pixel clock.
While preferably, receiving described LVDS video signal cable sequence control signal in described decode procedure in described LVDS video decode control signal to described four links according to LINK1, LINK2, LINK3, LINK4 ordering.
Preferably, the process that in step 3, the LVDS video source data of described four links is divided into two groups of strange pixel parallel datas, dual pixel parallel data comprises: LINK1, LINK3 in the LVDS video source data of described four links are divided into strange pixel parallel data, LINK2, LINK3 in the LVDS video source data of described four links are divided into dual pixel parallel data.
While preferably, receiving described LVDS video signal cable sequence control signal in described decode procedure in described LVDS video decode control signal to described four links according to LINK1, LINK2, LINK3, LINK4 ordering.
Preferably, the configuration operation of described execution MIPI conversion process and MIPI show that module initialization operation comprises and receive the configuration operation of carrying out MIPI conversion process after MIPI conversion initialization command, confirm to carry out again described MIPI module initialization command after configuration operation completes, and MIPI module initialization command is transferred to described 8LANE odd even split screen type MIPI with the form of MIPI order shows module, complete module initialization operation, when receiving described MIPI video conversion starting signal, send afterwards MIPI video conversion starting command.
Preferably, the process that respectively the even split screen vision signal of the strange split screen vision signal of described RGB and RGB is converted to left passage MIPI vision signal and right passage MIPI vision signal in step 4 comprises: the configuration operation and the MIPI that carry out MIPI conversion process show after module initialization operation, starts the strange split screen vision signal of the described RGB receiving and the even split screen vision signal of RGB is converted to left passage MIPI vision signal simultaneously and right passage MIPI video signal transmission shows module to described 8LANE odd even split screen type MIPI when receiving described MIPI video conversion starting command.
Beneficial effect of the present invention is:
(1) the present invention can be converted to LVDS vision signal 8LANE odd even split screen type MIPI vision signal.The present invention, by arranging, all can well be mated different qualities such as the multiple color range of LVDS vision signal, transmission means, coded systems.
(2) the LVDS vision signal of convertible 6,8,10 color ranges of the present invention, the convertible LVDS signal based on VESA and JEIDA transfer encoding, can change the LVDS transmission mode of four LINK, is applicable to the MIPI liquid crystal module of 8LANE odd even type.
(3) the present invention is before use only by manually changing toggle switch state applicable to different LVDS vision signals; Before the different MIPI liquid crystal module of application, need to receive this module running parameter by jtag interface.
(4) single FPGA(field programmable logic array for the present invention) chip just can be realized described repertoire; FPGA is a kind of programmable semicustom chip, can realize the synchronous processing of multilink video data, parallel conversion, can reach higher performance, not only working stability, realization are easily, and low price, avoided the problems such as design complexity because using various special chips to cause, poor stability, design cost height.
(5) video resolution that the present invention supports is higher, not only integrated level is high, reliable operation, antijamming capability are strong, and simple to operate, economical and practical, can not only promote the detection efficiency of MIPI liquid crystal module, reduce its equipment cost and production cost, also will further improve the universal of MIPI display device.
Accompanying drawing explanation
Fig. 1 is flow chart of the present invention;
Fig. 2 is block diagram of the present invention;
Fig. 3 a is the circuit block diagram of LVDS video reception unit and LVDS video signal decoding unit in Fig. 2;
Fig. 3 b is the circuit block diagram of odd even split screen type rgb video signal converting unit, odd even split screen type MIPI vision signal converting unit and video conversion configurations unit in Fig. 2;
Fig. 4 is the circuit diagram of odd even split screen type rgb video modular converter in Fig. 3 b;
Fig. 5 is the signal graph that LVDS vision signal is converted to rgb video signal;
In figure: 1.LVDS video reception unit, 1-1.LVDS video signal interface, 1-2.LVDS video reception termination module, the LVDS clock signal demodulation module of 1-3. tetra-LINK, the LVDS demodulated data signal module of 1-4. tetra-LINK, 1-5.LVDS demodulation dynamic calibration module;
2.LVDS video signal decoding unit, 2-1.LVDS audio video synchronization buffer module, the LVDS video signal cable order control module of 2-2. tetra-LINK, 2-3.LVDS video synchronization signal decoder module, the LVDS video data decoding module of 2-4. tetra-LINK;
3. odd even split screen type rgb video signal converting unit, 3-1.RGB video buffer module, 3-2.RGB video clock generation module, 3-3.RGB video clock output adjusting module, 3-4. odd even split screen type rgb video modular converter, the sampling of 3-4-1.LVDS video pixel, 3-4-2. synchronizing signal FIFO buffer memory, the strange pixel FIFO buffer memory of 3-4-3. video, 3-4-4. video dual pixel FIFO buffer memory, 3-4-5.RBG signal sampling, 3-5.RGB vision signal output module;
4. odd even split screen type MIPI vision signal converting unit, 4-1.MIPI register module, the left road of 4-2. MIPI vision signal modular converter, 4-3. right wing MIPI vision signal modular converter, 4-4.MIPI liquid crystal display module connector;
5. video conversion configurations unit, the manual toggle switch of 5-1., 5-2.JTAG interface, 5-3.MIPI video conversion configurations module;
6.8LANE odd even split screen type MIPI shows module.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figures 1 to 5, a kind of LVDS vision signal of the present invention is converted to 8LANE odd even split screen MIPI vision signal method, comprises the following steps:
LVDS vision signal comprises LINK1, LINK2, LINK3 and tetra-links of LINK4, four links transmit LVDS vision signal successively according to video pixel order, the LVDS vision signal of each link comprises LVDS receive clock and LVDS data, LVDS data are transmitted by LVDS data/address bus, LVDS data/address bus comprises some root holding wires, and every holding wire transmits serial code signal; MIPI vision signal comprises left passage MIPI vision signal and right passage MIPI vision signal, for the MIPI demonstration module of 8LANE odd even split screen type.
LVDS vision signal refers to take the general name of the signal that LVDS electrical characteristic be to characterize, and has the combination of the signal of string of different video pixel color range, signal transfer encoding standard, signal transmission link mode.The LVDS video signal characteristic receiving comprises: the color range of the LVDS video source pixel that receive (consisting of tri-kinds of color components of RGB) can have 6 or 8 or 10, each pixel is all according to the VESA of LVDS transmission of video or JEIDA coding standard, by stringization and be encoded into one group of homochromy component level number corresponding 3 or 4 or 5 s' data signal line forms one group of data/address bus, with the electrical form of LVDS, transmit.
According to the characteristic of the LVDS vision signal that will receive, LVDS vision signal decoding parametric, synchronous mode control parameter are set; Receive MIPI video conversion configurations parameter, the configuration operation and the MIPI that carry out MIPI conversion process show module initialization operation; According to LVDS vision signal decoding parametric, produce LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS video signal cable sequence control signal; According to synchronous mode, control parameter generating LVDS synchronous mode control signal; According to MIPI video conversion configurations parameter generating MIPI conversion initialization command and MIPI module initialization command.
LVDS vision signal decoding parametric comprises: LVDS video signal transmission coding standard has VESA and JEIDA; The pixel color component level of LVDS video source is wide 6,8,10; Synchronous mode is controlled parameter and is comprised high level effectively and Low level effective; MIPI video conversion configurations parameter comprises: the signal sequence of MIPI modular converter, transmission frequency, group pack mode, the display timing generator of MIPI liquid crystal display module, time delay Synchronization Control, initialization directive.By the manual toggle switch 5-1 in video conversion configurations unit 5, LVDS vision signal decoding parametric is set, by jtag interface 5-2, according to 8LANE odd even split screen type MIPI, shows that the type of module 6 receives MIPI video conversion configurations parameter.
Carry out the configuration operation of MIPI conversion process and MIPI and show that module initialization operation comprises that MIPI video conversion configurations module 5-3 in video conversion configurations unit 5 receives the configuration operation of carrying out MIPI conversion process after MIPI conversion initialization command, confirm to carry out again MIPI module initialization command after configuration operation completes, and MIPI module initialization command is transferred to liquid crystal module 6 with the form of MIPI order, complete module initialization operation, when receiving the MIPI video conversion starting signal transmitting from odd even split screen type rgb video signal converting unit 3, MIPI video conversion configurations module 5-3 sends MIPI video conversion starting command to odd even split screen type MIPI vision signal converting unit 4 afterwards.
MIPI video conversion configurations module 5-3 first writes reception MIPI conversion initialization command in MIPI register module 4-1 one by one, after often writing an order, read the state value of MIPI register module 4-1, to guarantee that command execution completes, when confirm MIPI vision signal modular converter 4-2 complete configure and start normal operation after write again the order of MIPI demonstration module initialization register, the form transmission 8LANE odd even split screen type MIPI that MIPI vision signal modular converter 4-2 is converted into MIPI order shows module 6, completes module initialization operation.
Before receiving LVDS vision signal, complete the configuration of decoding parametric, conversion parameter and produce corresponding control signal.
The process of in step 1, the vision signal of each link being carried out to receiving demodulation comprises: the serial code signal to LVDS data in each link receiving is terminated respectively, demodulation, dynamic calibration, produces LVDS parallel demodulation data; The process of termination comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild; The process of demodulation comprises: LVDS receive clock is carried out to demodulation, produce demodulation clock and demodulation enable signal, the serial code signal of the LVDS data of each link is demodulated to separately to parallel data respectively simultaneously, and LVDS receive clock is demodulated into LVDS pixel clock simultaneously.
LVDS vision signal receives by the LVDS video signal interface 1-1 in LVDS video reception unit 1, then by LVDS video reception termination module 1-2, is terminated.Object to LVDS vision signal termination is: guarantee that the LVDS video signal quality receiving is high, noiseless.The process of termination comprises: before receiving LVDS vision signal, carry out ESD(Electro Static Discharge static discharge) protective treatment disturbs to eliminate the strong discharge impact of moment, then carries out common-mode noise filtering processing to suppress line noise, to improve anti-electromagnetic interference capability.The distortion causing with erasure signal transmission is processed in the impedance matching that is terminated when receiving signal, and also the additional interference of further erasure signal is carried out equilibrium and the processing of postemphasising to signal, to eliminate the signal attenuation being caused because of loss simultaneously.Afterwards again to signal Hyblid Buffer Amplifier, and through the judgement of reference level, reconstruct high-quality LVDS vision signal.
The LVDS clock signal demodulation module 1-3 of four LINK is to the LVDS receive clock of the LVDS vision signal by termination through carrying out demodulation, and LVDS data are carried out demodulation through the LVDS demodulated data signal module 1-4 of four LINK.LVDS receive clock demodulating process to each link comprises: LVDS receive clock is carried out after speed buffering to frequency multiplication operation and high-frequency clock conversion process, produce with the LVDS demodulation clock of LVDS data same frequency and with LVDS receive clock with LVDS pixel clock, LVDS demodulation gating signal frequently, and output in high-frequency clock network, make them there is very low delay and jitter, very strong driving force, guarantee reliable and stable LVDS data to be carried out to demodulation.When LVDS receive clock is carried out to frequency multiplication operation, also carry out the moving calibration of clock jitter removing, think that subsequent operation generation is not affected by input jiffer, stable frequency-doubled signal.
LVDS data demodulation process is comprised: to each data independently demodulation respectively in the LVDS serial data bus of four LINK, by each LVDS data-signal its phase delay half-bit bit period after speed buffering input, make this data value that samples that LVDS demodulation clock can be correct at the center of each LVDS data bit, and according to demodulation gating signal, it is periodically blocked to bunchiness data, with LVDS pixel clock, doing string again turns and processes the parallel demodulation data that obtain this LVDS signal, each LVDS demodulating data is merged into LVDS demodulating data.The demodulation that each LVDS holding wire is all run simultaneously, makes each holding wire no matter how data all can phase mutual interference not cause demodulation mistake.Simultaneously also carry out data dithering removal calibration LVDS data being carried out to demodulation, to produce, not affected by input jiffer, reliable and stable demodulating data.Phase delay process in data input is subject to LVDS data flow phase alignment signal controlling all the time, when the phase place between demodulation clock and LVDS data has deviation, phase alignment signal is made its delay adjustment contrary with phase deviation on data delay half period basis, data center is alignd along maintenance with the sampling of demodulation clock all the time, guarantee correctly to sample data.When demodulation gating signal is blocked serial data, the bit that is subject to byte-aligned moves calibrating signal and controls, and makes it the start bit of the parallel data of cutting apart move on next serial data position.
For guaranteeing that bits per inch, according to correctness and the reliability of separating timing, carries out dynamic calibration by LVDS demodulation dynamic calibration module 1-5 to the LVDS receive clock of each link and each LVDS data respectively in demodulation,
The process of in step 2, the parallel demodulation data of four links being carried out to video decode comprises: with LVDS pixel clock to the parallel demodulation data of each link first in the LVDS audio video synchronization buffer module 2-1 in LVDS video signal decoding unit 2 buffer memory synchronously read again, then the LVDS video data decoding module of LVDS video synchronization signal decoder module 2-3 and four LINK is decoded with the operation of sequential logic to the parallel demodulation data of four links respectively, obtains LVDS video source data and the LVDS video source synchronizing signal of four links.The LVDS pixel clock of LINK1 is converted to LVDS video source pixel clock by global clock path, with this, produces LVDS video source data and synchronizing signal.
In LVDS vision signal, in transmission, for avoiding occurring, between the LVDS signal of four links, there are delay, the asynchronous situation that causes subsequent treatment mistake, need to LVDS pixel clock separately, be sampled and buffer memory respectively to the parallel demodulation data of each link, the buffer memory degree of depth is large as far as possible, so that all links have abundant data to be buffered to offset maximum delay between them, with LVDS video source pixel clock, in the mode of fifo queue, carry out synchronized sampling again, make it to become synchrodata.
When the LVDS video signal cable order control module 2-2 of four LINK receives the LVDS video signal cable sequence control signal in LVDS video decode control signal in decode procedure, to four links according to LINK1, LINK2, LINK3, LINK4 ordering.
Because LVDS video signal transmission coding standard (VESA or JEDIA standard) is all supported 6 bits, 8 bits, the coding of 10 bit pixel color ranges, its LVDS video synchronization signal is also together encoded with video pixel data, and its coding rule is separately unique, therefore according to LVDS video standard control signal and LVDS video bit wide control signal, can obtain unique LVDS decoded video data, pass through thus LVDS video source pixel clock respectively to LINK1, LINK2, LINK3, the demodulating data of LINK4 is decoded with the operation of sequential logic, recover LVDS video source synchronizing signal and the LVDS video source data signal of four LINK.
LVDS video source synchronizing signal comprises video level line synchronizing signal (Hsync), video perpendicualr field synchronizing signal (Vsync), video data useful signal (DE).Due in VESA and JEIDA coding standard, the mode of the coding of the synchronizing signal of each link with sequential identical, therefore only need the LINK1 synchronizing signal of decode after sequence also to export as LVDS video source synchronizing signal.
The process that in step 3, the LVDS video source data of four links is divided into two groups of strange pixel parallel datas, dual pixel parallel data comprises: LINK1, LINK3 in the LVDS video source data of four links are divided into strange pixel parallel data, LINK2, LINK3 in the LVDS video source data of four links are divided into dual pixel parallel data.
With the rgb video clock generating module 3-2 in the rgb video signal converting unit 3 of odd even split screen type, according to local clock signal, generate rgb video clock, the frequency of rgb video clock is two times of LVDS video source pixel clock, starts LVDS video buffer module 3-1 after rgb video clock stable.LVDS video buffer module 3-1, the LVDS video source data and LVDS video source synchronizing signal the buffer memory that receive four links, send LVDS video source data and LVDS video source synchronizing signal odd even split screen type rgb video modular converter 3-4 to and start odd even split screen type rgb video modular converter 3-4, LVDS video pixel sampling 3-4-1 in odd even split screen rgb video modular converter 3-4 synchronously samples to the LVDS video source data of LVDS video source synchronizing signal and four links with LVDS video source pixel clock respectively, by LINK1 in the LVDS video source data of four links, LINK3 is divided into strange pixel parallel data, by LINK2 in the LVDS video source data of four links, LINK3 is divided into dual pixel parallel data, strange pixel parallel data is write to the strange pixel FIFO buffer memory of video 3-4-3, dual pixel parallel data is write to video dual pixel FIFO buffer memory 3-4-4, by LVDS video source synchronizing signal, according to " Vs, Hs, DE, Vs, Hs, DE " form be copied into the parallel synchronizing signal of two-way, with LVDS video source pixel clock, be written in synchronizing signal FIFO buffer memory 3-4-2, rgb video clock while read output signal from three FIFO buffer memorys for rgb signal sampling 3-4-5, is converted into respectively the strange pixel data of RGB, RGB dual pixel data and rgb video synchronizing signal, described rgb video synchronizing signal is copied as to two-way, form the strange split screen vision signal of RGB and the even split screen vision signal of RGB with the strange pixel data of RGB, RGB dual pixel data, rgb video clock respectively.For data, because strange pixel parallel data and dual pixel parallel data are simultaneously by rgb video Clockreading, therefore RGB data are actual is alternately to export strange pixel parallel data, dual pixel parallel data, thereby complete the conversion of all data, for synchronizing signal, because RGB clock has read twice to it at each LVDS in the clock cycle, so the video sequential of RGB and LVDS is consistent; For transfer process, because DC-FIFO writes the data volume of twice a unit interval with the clock of a times, and by the data volume of one times of the Clockreading of twice, the throughput that is read-write operation equates, therefore there will not be and write completely or read empty situation, i.e. the carrying out of conversion operations energy continous-stable.
Forming after rgb video signal, receive LVDS synchronous mode control signal, whether be Low level effective, if rgb video signal is Low level effective, rgb signal is exported if detecting rgb video signal; If rgb video signal is that high level is effective, rgb signal is transferred to after Low level effective rgb signal output, during output, send MIPI video conversion starting signal.
By in the process of rgb signal output, the processing of rgb video clock being carried out with rgb video clock output adjusting module 3-3, comprise: the phase place to rgb video clock is adjusted, make its effective edge along near can the center in rgb video source data, carry out again de-jitter, when rgb signal is exported, compare effective edge of the rgb video clock after debounce is moved and the deviation between rgb video source data center, and utilize time delay to do trim process so that effective edge of rgb video clock and rgb video source data center remain alignment.
Due to rgb video data and rgb video clock synchronous, therefore the rgb video clock phase of input is postponed to half clock cycle as RGB clock signal, make it effectively along near can the center in rgb video data, thereby guarantee that follow-up conversion operations is by this clock RGB data of correctly sampling, this signal carries out de-jitter more afterwards, and exported by the high speed signal interface assembly of rgb video signal output module 3-5, to guarantee that this output clock has higher stability and good signal quality.
When starting to export RGB data and synchronizing signal, postpone to produce MIPI video conversion starting signal after some rgb video clocks, start 4 work of follow-up odd even split screen type MIPI vision signal converting unit, doing is like this in order to make odd even split screen type MIPI vision signal converting unit 4 receive at the very start normal video data, improves the reliability of MIPI conversion.
The process that simultaneously the even split screen vision signal of the strange split screen vision signal of RGB and RGB is converted to respectively to left passage MIPI vision signal and right passage MIPI vision signal in step 4 comprises: configuration operation and MIPI that MIPI video conversion configurations module 5-3 carries out MIPI conversion process show after module initialization operation, and MIPI video conversion configurations module 5-3 sends MIPI video conversion starting command after receiving MIPI video conversion starting signal.When starting to carry out MIPI conversion configurations, left road MIPI vision signal modular converter 4-2 and right wing MIPI video conversion module 4-3 are configured operation according to the MIPI register command writing, and these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show module initialization command, the order of MIPI conversion and control; After configuration completes, according to the MIPI of write register, show module initialization command, left road MIPI vision signal modular converter 4-2 is converted to these orders respectively MIPI command signal with right wing MIPI video conversion module 4-3 and is transferred to the 8LANE odd even split screen type MIPI demonstration module 6 that MIPI liquid crystal display module connector 4-4 is connected, and makes 8LANE odd even split screen type MIPI show that module 6 carries out initialization operation.When the order of MIPI video conversion and control writes MIPI register module 4-1Shi，Zuo road MIPI vision signal modular converter 4-2 and right wing MIPI video conversion module 4-3, the strange split screen vision signal of the RGB of input and the even split screen vision signal of RGB are converted to respectively to left passage MIPI vision signal simultaneously and to the 8LANE odd even split screen type MIPI being connected with MIPI liquid crystal display module connector 4-4, show module 6 demonstrations with right passage MIPI video signal transmission afterwards.
The present invention is not limited to above-mentioned execution mode; for those skilled in the art, be also considered as the protection range of patent of the present invention according to know-why of the present invention and scheme or some improvement of making, change, retouching, distortion, replacement under enlightenment of the present invention within.
The content not being described in detail in this specification, write a Chinese character in simplified form, term belongs to the known prior art of professional and technical personnel in the field.
Claims (9)
1. LVDS vision signal is converted to a 8LANE odd even split screen MIPI vision signal method, it is characterized in that: comprise the following steps:
Step 1, the vision signal of each link of LVDS vision signal is carried out respectively to receiving demodulation simultaneously, produce parallel demodulation data and the LVDS pixel clock of four links;
Step 2, the parallel demodulation data of described four links are carried out to video decode, generate LVDS video source data and the LVDS video source synchronizing signal of four links, described LVDS pixel clock is converted into LVDS video source pixel clock;
Step 3, generation rgb video clock, the frequency that makes described rgb video clock is two times of described LVDS video source pixel clock, the LVDS video source data of described four links is divided into two groups of strange pixel parallel data, dual pixel parallel datas, with described rgb video clock, read described strange pixel parallel data, dual pixel parallel data and synchronizing signal simultaneously, be converted into respectively the even split screen vision signal of the strange split screen vision signal of RGB and RGB;
Step 4, the even split screen vision signal of the strange split screen vision signal of described RGB and RGB is converted to respectively to left passage MIPI vision signal and right passage MIPI vision signal simultaneously.
2. LVDS vision signal according to claim 1 is converted to 8LANE odd even split screen MIPI vision signal method, it is characterized in that: described LVDS vision signal comprises LINK1, LINK2, LINK3 and tetra-links of LINK4, described four links transmit LVDS vision signal successively according to video pixel order, the LVDS vision signal of described each link comprises LVDS receive clock and LVDS data, described LVDS data are transmitted by LVDS data/address bus, described LVDS data/address bus comprises some root holding wires, and every holding wire transmits serial code signal; Described MIPI vision signal comprises left passage MIPI vision signal and right passage MIPI vision signal, for the MIPI demonstration module (6) of 8LANE odd even split screen type.
3. LVDS vision signal according to claim 1 is converted to the method for 8LANE odd even split screen MIPI vision signal, it is characterized in that: before the vision signal of each link being carried out to receiving demodulation in described step 1, according to the characteristic of the LVDS vision signal that will receive, LVDS vision signal decoding parametric, synchronous mode control parameter are set; Receive the MIPI video conversion configurations parameter in LVDS vision signal, the configuration operation and the MIPI that carry out MIPI conversion process show module initialization operation; According to described LVDS vision signal decoding parametric, produce LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS video signal cable sequence control signal; According to described synchronous mode, control parameter generating LVDS synchronous mode control signal; According to described MIPI video conversion configurations parameter generating MIPI conversion initialization command and MIPI module initialization command.
4. LVDS vision signal according to claim 2 is converted to 8LANE odd even split screen MIPI vision signal method, it is characterized in that: the process of in described step 1, the vision signal of each link being carried out to receiving demodulation comprises: to the serial code signal in described each link receiving be terminated respectively, demodulation, dynamic calibration, produce parallel demodulation data and LVDS pixel clock; The process of described termination comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild; The process of described demodulation comprises: described LVDS receive clock is carried out to demodulation, produce demodulation enable signal, the serial code signal of the LVDS data of each link is demodulated to separately to parallel data respectively simultaneously, and described LVDS receive clock is demodulated into described LVDS video source pixel clock simultaneously.
5. LVDS vision signal according to claim 2 is converted to 8LANE odd even split screen MIPI vision signal method, it is characterized in that: the process of in described step 2, the parallel demodulation data of described four links being carried out to video decode comprises: with described LVDS pixel clock, the first buffer memory of the parallel demodulation data of described each link is synchronously read again, then the parallel demodulation decoding data to described four links respectively, the LVDS video source data and the LVDS video source synchronizing signal that obtain four links, described LVDS pixel clock is converted into LVDS video source pixel clock.
6. LVDS vision signal according to claim 2 is converted to 8LANE odd even split screen MIPI vision signal method, it is characterized in that: the process that in step 3, the LVDS video source data of described four links is divided into two groups of strange pixel parallel datas, dual pixel parallel data comprises: LINK1, LINK3 in the LVDS video source data of described four links are divided into strange pixel parallel data, LINK2, LINK3 in the LVDS video source data of described four links are divided into dual pixel parallel data.
7. LVDS vision signal according to claim 3 is converted to 8LANE odd even split screen MIPI vision signal method, it is characterized in that: while receiving described LVDS video signal cable sequence control signal in described decode procedure in described LVDS video decode control signal to described four links according to LINK1, LINK2, LINK3, LINK4 ordering.
8. LVDS vision signal according to claim 3 is converted to 8LANE odd even split screen MIPI vision signal method, it is characterized in that: the configuration operation of described execution MIPI conversion process and MIPI show that module initialization operation comprises and receive the configuration operation of carrying out MIPI conversion process after MIPI conversion initialization command, confirm to carry out again described MIPI module initialization command after configuration operation completes, and MIPI module initialization command is transferred to described 8LANE odd even split screen type MIPI with the form of MIPI order shows module (6), complete module initialization operation, when receiving described MIPI video conversion starting signal, send afterwards MIPI video conversion starting command.
9. LVDS vision signal according to claim 8 is converted to 8LANE odd even split screen MIPI vision signal method, it is characterized in that: the process that respectively the even split screen vision signal of the strange split screen vision signal of described RGB and RGB is converted to left passage MIPI vision signal and right passage MIPI vision signal in step 4 comprises: the configuration operation and the MIPI that carry out MIPI conversion process show after module initialization operation, when receiving described MIPI video conversion starting command, start the strange split screen vision signal of the described RGB receiving and the even split screen vision signal of RGB is converted to left passage MIPI vision signal simultaneously and right passage MIPI video signal transmission shows module (6) to described 8LANE odd even split screen type MIPI.
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