CN203574773U - Device for converting LVDS video signal into 8LANE left-and-ring split screen MIPI video signal - Google Patents

Abstract

The utility model discloses a device for converting an LVDS video signal into an 8LANE left-and-ring split screen MIPI video signal. The device comprises an LVDS video signal receiving unit, which is used for receiving and demodulating the LVDS video signal and generating LVDS parallel demodulation data of four links; an LVDS video signal decoding unit, which is used for generating LVDS video source data and LVDS video source synchronization signal; a left-and-ring split screen RGB video signal conversion unit, which is used for converting the LVDS video source data of the four links and the LVDS video source synchronization signal into a left half screen RGB video signal and a right half screen RGB video signal; a left-and-ring split screen RGB video signal conversion unit, which is used for converting the left half screen RGB video signal and the right half screen RGB video signal into a left channel MIPI video signal and a right channel MIPI video signal; and a video conversion configuration unit, which is used for generating an LVDS video signal decoding signal and an LVDS synchronization signal, and for executing an configuration operation of MIPI conversion processing and an initialization operation of the MIPI display module.

Description

LVDS vision signal is converted to 8LANE left and right split screen MIPI video signal device

Technical field

The utility model relates to demonstration field and the field tests of liquid crystal module, refers to that particularly a kind of LVDS vision signal is converted to 8LANE left and right split screen MIPI video signal device.

Background technology

Liquid crystal display module (Liquid Crystal Display Module, hereinafter to be referred as liquid crystal module) is the critical component that liquid crystal display can normally show, it is by liquid crystal display screen, original paper backlight, Graphics Processing chip and the electric circuit constitute.Liquid crystal display module structure is accurate, processing procedure is complicated, manufacturing technique requirent is high, in order to guarantee yields when producing, need to produce various test video signals by special liquid crystal module testing apparatus and be input in liquid crystal module and show, strictly, comprehensively detect its display effect.Its display interface of common liquid crystals module of using on TV, display product at present and inner Graphics Processing circuit are used LVDS(Low-Voltage Differential Signaling, Low Voltage Differential Signal) signal carrys out work.And existing liquid crystal module testing device also corresponding output be that LVDS vision signal is to realize the test of module.Because common liquid crystals module production time is of a specified duration, output is large, so its module testing apparatus also uses in a large number.

Along with people constantly pursue high definition more, display effect more true to nature on mobile device, portable equipment, therefore common liquid crystals module cannot meet the need gradually.So occurred on market that a kind of novel liquid crystal module with ultrahigh resolution and very-high solution density meets people's demand.The interface of this liquid crystal module and inner Graphics Processing circuit adopt MIPI(Mobile Industry Processor Interface to move industry processor interface) signaling interface.This interface is formulated by the MIPI alliance that comprises the companies such as ARM, Samsung, Intel, object is that handle is mobile, inner each assembly of portable equipment is as nuclear interface standardizings such as camera, display screen, processors and opens each other, thereby improved performance, reduced cost and power consumption.MIPI interface can not only be supported ultrahigh resolution and refresh rate, and has farther transmission range, better Electro Magnetic Compatibility, and therefore the liquid crystal module with MIPI interface has become development trend.

Yet the testing apparatus of MIPI liquid crystal module need to be exported same MIPI test signal, but existing common liquid crystals module testing apparatus does not have this function, and common liquid crystals module also continues to produce, its testing apparatus does not enter the replacement cycle yet will be continued to use.Although module manufacturer also produces MIPI liquid crystal module, in order to protect investment, to reduce production costs, can not eliminate existing equipment, again make a big purchase expensive MIPI module Special testing device in large quantities.In order to produce cheaply MIPI liquid crystal module in enormous quantities within short-term and to guarantee its yields, just still reuse on a large scale existing common module testing apparatus.

Therefore, need a kind of conversion equipment LVDS vision signal can be converted to 8LANE left and right split screen type MIPI vision signal, common liquid crystals module testing apparatus can be tested MIPI module by this conversion equipment.This conversion equipment is not only wanted dependable performance, integrated efficient but also is wanted low price, easy and simple to handle simultaneously.

Summary of the invention

The purpose of this utility model is to provide a kind of LVDS vision signal to be converted to 8LANE left and right split screen MIPI video signal device, and it has feature simple to operate, that detection efficiency is high, cost is low.

For achieving the above object, the designed LVDS vision signal of the utility model is converted to 8LANE left and right split screen MIPI video signal device, its special character in, comprising:

LVDS video reception unit, for receiving demodulation LVDS vision signal, produces LVDS parallel demodulation data and the LVDS pixel clock of four links, the LVDS vision signal that described LVDS vision signal is four LINK;

LVDS video signal decoding unit, be used for according to LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS video signal cable sequence control signal, LVDS parallel demodulation data to described four links are carried out video decode, produce LVDS video source data and the LVDS video source synchronizing signal of four links;

Left and right split screen type rgb video signal converting unit, for the LVDS video source data of described four links and LVDS video source synchronizing signal being converted to left half screen rgb video signal and right half screen rgb video signal according to LVDS synchronous mode control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit;

Left and right split screen type MIPI vision signal converting unit, for respectively described left half screen rgb video signal and right half screen rgb video signal are converted to left passage MIPI vision signal and right passage MIPI vision signal when receive MIPI video conversion starting command from video conversion configurations unit, send 8LANE left and right split screen type MIPI to and show module, described left passage MIPI vision signal and right passage MIPI vision signal are for the MIPI demonstration module of 8LANE left and right split screen type;

Video conversion configurations unit, be used for according to the characteristic of the LVDS vision signal that will receive, LVDS vision signal decoding parametric is set, and product LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS video signal cable sequence control signal send described LVDS video signal decoding unit to; LVDS audio video synchronization pattern is set and controls parameter, produce LVDS synchronous mode control signal and send left and right split screen type rgb video signal converting unit to; Read MIPI video conversion configurations parameter left and right split screen type MIPI vision signal converting unit is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command; From described left and right split screen type rgb video signal converting unit receives MIPI video conversion starting signal, send MIPI video conversion starting command and send described left and right split screen type MIPI vision signal converting unit to.

Further, described LVDS video reception unit comprises:

LVDS video signal interface, be used for receiving LVDS vision signal, described LVDS vision signal comprises the LVDS vision signal of LINK1, LINK2, LINK3, LINK4, and the LVDS vision signal of described LINK1, LINK2LINK3, LINK4 is alternately transmitted the pixel data of LVDS video successively;

LVDS clock signal demodulation module is used for: the LVDS receive clock to described each LINK receiving carries out demodulation, produces demodulation clock and demodulation enable signal;

LVDS demodulated data signal module is used for: the demodulation clock by described each LINK becomes parallel data with demodulation enable signal to the LVDS data demodulates of this LINK, and described LVDS receive clock is demodulated into LVDS pixel clock simultaneously.

Further, described LVDS video signal decoding unit comprises:

LVDS audio video synchronization buffer module, synchronously reads for the first buffer memory of the LVDS parallel demodulation data to described four LINK again, and described LVDS pixel clock is converted to LVDS video source pixel clock;

LVDS video synchronization signal decoder module, for the LVDS parallel demodulation decoding data to described four LINK that synchronously read according to the LVDS video decode control signal receiving from described video conversion configurations unit, decode the LVDS video source synchronizing signal of four LINK;

The LVDS video data decoding module of four LINK, for the LVDS parallel demodulation decoding data to described four LINK that synchronously read according to the LVDS video decode control signal receiving from described video conversion configurations unit, decode the LVDS video source data signal of four LINK.

Further, described left and right split screen type rgb video signal converting unit comprises:

LVDS video buffer module, for receiving LVDS video source data and LVDS video source synchronizing signal the buffer memory of described four links, according to described LVDS video source synchronization signal detection, go out LVDS video line resolution value, send described LVDS video line resolution value, LVDS video source data and LVDS video source synchronizing signal to left and right split screen type rgb video modular converter and start described left and right split screen type rgb video modular converter;

Rgb video clock generating module, for generation of rgb video clock, starts described LVDS video buffer module after described rgb video clock stable;

Rgb video clock output adjusting module, for the phase place of described rgb video clock is adjusted, makes its effective edge along center that can be in rgb video source data, then carries out de-jitter, and described rgb video clock is adjusted into RGB output clock;

Left and right split screen type rgb video modular converter, for being converted to left half screen rgb video signal and right half screen rgb video signal with described rgb video clock by described LVDS video source synchronizing signal and LVDS video source data signal according to described LVDS video line resolution value;

Rgb video signal output module, be used for receiving described left half screen rgb video signal and right half screen rgb video signal output, during output, described RGB output clock is adjusted, when having described left half screen rgb video signal and the output of right half screen rgb video signal, postpone to produce MIPI video conversion starting signal and send described video conversion configurations unit to.

Further, described left and right split screen type MIPI vision signal converting unit comprises:

MIPI register module, for control configuration and the operation that left half screen MIPI vision signal modular converter and right half screen MIPI vision signal modular converter carry out MIPI conversion according to the MIPI register command writing simultaneously, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;

Left half screen MIPI vision signal modular converter, be used for receiving described left half screen rgb video signal, execution is converted to described left half screen rgb video signal configuration and the conversion operations of left passage MIPI vision signal, send the left passage MIPI vision signal after conversion to MIPI liquid crystal display module connector, when receiving the order of MIPI conversion configurations from described MIPI register module, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module, by described MIPI liquid crystal display module connector, be transferred to 8LANE left and right split screen type MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module, start conversion operations,

Right half screen MIPI vision signal modular converter is used for receiving described right half screen rgb video signal, execution is converted to described right half screen rgb video signal configuration and the conversion operations of right passage MIPI vision signal, send the right passage MIPI vision signal after conversion to MIPI liquid crystal display module connector, when receiving the order of MIPI conversion configurations from described MIPI register module, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module, by described MIPI liquid crystal display module connector, be transferred to 8LANE left and right split screen type MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module, start conversion operations,

MIPI liquid crystal display module connector, for receive described left passage MIPI vision signal and right passage MIPI vision signal simultaneously, and show that with 8LANE left and right split screen type MIPI module is connected, send described left passage MIPI vision signal and right passage MIPI vision signal to described 8LANE left and right split screen type MIPI demonstration module.

Described video conversion configurations unit comprises:

Manual toggle switch, for arranging LVDS vision signal decoding parametric;

Jtag interface, for receiving MIPI video conversion configurations parameter;

MIPI video conversion configurations module, for LVDS vision signal decoding parametric is converted to LVDS video decode control signal, read MIPI video conversion configurations parameter described left and right split screen type MIPI vision signal converting unit is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, when receiving MIPI video changeover control signal from described left and right split screen type rgb video signal converting unit, produce MIPI video conversion starting command and send described left and right split screen type MIPI vision signal converting unit to.

Further, described LVDS video reception unit also comprises:

LVDS video reception termination module, be used for the operation that is terminated of received LVDS vision signal, then send described LVDS receive clock and LVDS data to LVDS clock signal demodulation module and LVDS signal demodulation module respectively, described terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild, compensation is because of long signal distortion that Distance Transmission causes, decay, reduce transmission and disturb, guarantee received LVDS signal quality;

LVDS demodulation dynamic calibration module, for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.

Further, described LVDS video signal decoding unit also comprises LVDS video signal cable order control module, for the data arrangement order to described LINK1, LINK2, LINK3, LINK4 when receiving described LVDS video signal cable sequence control signal.

The beneficial effects of the utility model are:

(1) the utility model can convert the LVDS vision signal of four LINK to MIPI vision signal.By arranging, to different qualities such as the multiple color range of LVDS vision signal, transmission means, coded systems, all can well mate.

(2) the LVDS vision signal of convertible 6,8,10 color ranges of the utility model, the convertible LVDS signal based on VESA and JEIDA transfer encoding, can change the LVDS transmission mode of four LINK, be applicable to the MIPI liquid crystal module of 8LANE left and right split screen type.

(3) the utility model is before use only by manually changing toggle switch state applicable to different LVDS vision signals; Before the different MIPI liquid crystal module of application, need to receive this module running parameter by jtag interface.

(4) single FPGA(field programmable logic array for the utility model) chip just can be realized described repertoire; FPGA is a kind of programmable semicustom chip, can realize the synchronous processing of multilink video data, parallel conversion, can reach higher performance, not only working stability, realization are easily, and low price, avoided the problems such as design complexity because using various special chips to cause, poor stability, design cost height.

(5) video resolution that the utility model is supported is higher, not only integrated level is high, reliable operation, antijamming capability are strong, and simple to operate, economical and practical, can not only promote the detection efficiency of MIPI liquid crystal module, reduce its equipment cost and production cost, also will further improve the universal of MIPI display device.

Accompanying drawing explanation

Fig. 1 is the utility model block diagram;

Fig. 2 a is the circuit block diagram of LVDS video reception unit and LVDS video signal decoding unit in Fig. 1;

Fig. 2 b is the circuit block diagram of left and right split screen type rgb video signal converting unit, left and right split screen type MIPI vision signal converting unit and video conversion configurations unit in Fig. 1;

Fig. 3 is the circuit diagram of left and right split screen type rgb video modular converter in Fig. 2 b;

Fig. 4 is the signal graph that LVDS vision signal is converted to rgb video signal;

In figure: 1.LVDS video reception unit, 1-1.LVDS video signal interface, 1-2.LVDS video reception termination module, the LVDS clock signal demodulation module of 1-3. tetra-LINK, the LVDS demodulated data signal module of 1-4. tetra-LINK, 1-5.LVDS demodulation dynamic calibration module;

2.LVDS video signal decoding unit, 2-1.LVDS audio video synchronization buffer module, the LVDS video signal cable order control module of 2-2. tetra-LINK, 2-3.LVDS video synchronization signal decoder module, the LVDS video data decoding module of 2-4. tetra-LINK;

3. odd even split screen type rgb video signal converting unit, 3-1.RGB video buffer module, 3-2.RGB video clock generation module, 3-3.RGB video clock output adjusting module, 3-4. odd even split screen type rgb video modular converter, the sampling of 3-4-1.LVDS synchronizing signal, the sampling of 3-4-2.LVDS video pixel, 3-4-3. synchronizing signal FIFO buffer memory, the strange pixel FIFO buffer memory of 3-4-4. video, 3-4-5. video dual pixel FIFO buffer memory, 3-4-6.RBG signal sampling, 3-5.RGB vision signal output module;

4. left and right split screen type MIPI vision signal converting unit, 4-1.MIPI register module, the left road of 4-2. MIPI vision signal modular converter, 4-3. right wing MIPI vision signal modular converter, 4-4.MIPI liquid crystal display module connector;

5. video conversion configurations unit, the manual toggle switch of 5-1., 5-2.JTAG interface, 5-3.MIPI video conversion configurations module;

6.8LANE left and right split screen type MIPI shows module.

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.

As shown in Figures 1 to 4, a kind of LVDS vision signal of the utility model is converted to 8LANE left and right split screen MIPI video signal device, comprising:

LVDS video reception unit 1, LVDS video signal decoding unit 2, left and right split screen type rgb video signal converting unit 3, left and right split screen type MIPI vision signal converting unit 4 and video conversion configurations unit 5.

LVDS video reception unit 1, for receiving demodulation LVDS vision signal, produces LVDS parallel demodulation data and the LVDS pixel clock of four links, and LVDS vision signal is the LVDS vision signal of four LINK.

LVDS video reception unit 1 comprises:

LVDS video signal interface 1-1, be used for receiving LVDS vision signal, LVDS vision signal comprises LINK1, LINK2, LINK3 and tetra-links of LINK4, four links transmit LVDS vision signal successively according to video pixel order, the LVDS vision signal of each link comprises LVDS receive clock and LVDS data, LVDS data are transmitted by LVDS data/address bus, and LVDS data/address bus comprises some root holding wires, and every holding wire transmits serial code signal; MIPI vision signal comprises left passage MIPI vision signal and right passage MIPI vision signal, for the MIPI demonstration module 6 of 8LANE left and right split screen type.LVDS video signal interface 1-1, by connecting the LVDS transmission line interface of four LINK, input LVDS vision signal, interface comprises two kinds of input pads: industrial standard ox horn seat connector and Miniature high-density business connector, to guarantee that the utility model all can be suitable in industrial environment and business environment, when some connectors have the LVDS signal input of four LINK, interface can be automatically from this connector output, when two connectors have signal input, interface acquiescence is exported from Miniature high-density business connector.

LVDS video reception termination module 1-2, for by the processing that is terminated of the LVDS vision signal of four LINK that receive, guarantee that LVDS signal quality to be demodulated is high, noiseless then to send LVDS receive clock and LVDS data to the LVDS clock signal demodulation module 1-3 of four LINK and the LVDS signal demodulation module 1-4 of four LINK respectively.The process of termination comprises: before receiving LVDS signal, carry out ESD(Electro Static Discharge static discharge) protective treatment disturbs to eliminate the strong discharge impact of moment, then carries out common-mode noise filtering processing to suppress line noise, to improve anti-electromagnetic interference capability.The distortion causing with erasure signal transmission is processed in the impedance matching that is terminated when receiving signal, and also the additional interference of further erasure signal is carried out equilibrium and the processing of postemphasising to signal, to eliminate the signal attenuation being caused because of loss simultaneously.Afterwards again to signal Hyblid Buffer Amplifier, and through the judgement of reference level, reconstruct high-quality LVDS vision signal.

LVDS clock signal demodulation module 1-3 is used for: the LVDS receive clock to each LINK receiving carries out demodulation, produces demodulation clock and demodulation enable signal; Demodulating process comprises: LVDS receive clock is input to PLL(Phase Locked Loop phase-locked loop through High Speed I/O buffering) its frequency multiplication is arrived to LVDS frequency data signal, and carry out high-frequency clock conversion process, produce the LVDS demodulation clock with LVDS data same frequency, with LVDS pixel clock and the LVDS demodulation gating signal of LVDS receive clock with frequency, and output in high-frequency clock network, make them there is very low delay and jitter, very strong driving force, guarantee reliable and stable LVDS data to be carried out to demodulation.When LVDS receive clock being carried out to frequency multiplication operation with PLL, from the moving calibrating signal of clock jitter removing of LVDS demodulation dynamic calibration module 1-5, also sending into PLL simultaneously controls this operating process is carried out to anti-shake, it is produced and be not subject to that input jiffer affects, stable frequency-doubled signal, guarantee that demodulation operation can not make mistakes without interruption.

LVDS demodulated data signal module 1-4 is used for: the demodulation clock by each LINK becomes parallel data with demodulation enable signal to the LVDS data demodulates of this LINK, and LVDS receive clock is demodulated into LVDS pixel clock simultaneously.Its process comprises: to each data independently demodulation respectively in LVDS serial data bus.Each LVDS data-signal is first buffered in the high speed signal network of low delay, low jitter, postponed again data bit bit period half, make this data value that samples that LVDS demodulation clock can be correct at the center of each LVDS data bit, and according to demodulation gating signal, it is periodically blocked to bunchiness data, with LVDS pixel clock, do string again and turn and process the parallel demodulation data that obtain this LVDS signal, by trigger Buffer output to guarantee signal stabilization, reliably.The demodulation that each LVDS holding wire is all run simultaneously, makes each holding wire no matter how data all can phase mutual interference not cause demodulation mistake.

When the bit value by LVDS demodulation clock sampling LVDS data, from the data dithering removal calibrating signal of LVDS demodulation dynamic calibration module 1-5, also this operating process is carried out to anti-shake simultaneously and control, it is produced and be not subject to that input jiffer affects, reliable and stable demodulating data.

In the phase delay process of data input, be subject to all the time the LVDS data flow phase alignment signal controlling of LVDS demodulation dynamic calibration module 1-5, when the phase place between demodulation clock and LVDS data has deviation, phase alignment signal is made its delay adjustment contrary with phase deviation on data delay half period basis, data center is alignd along maintenance with the sampling of demodulation clock all the time, guarantee correctly to sample data.

When demodulation gating signal is blocked serial data, also the bit for demodulation byte-aligned that is subject to LVDS demodulation dynamic calibration module 1-5 moves calibrating signal and controls, and makes it the start bit of the parallel data of cutting apart move on next serial data position.

LVDS demodulation dynamic calibration module 1-5, for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.

LVDS video signal decoding unit 2, be used for according to LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS video signal cable sequence control signal, LVDS parallel demodulation data to four LINK are carried out video decode, the LVDS video source signal that produces four LINK, LVDS video source signal comprises LVDS video source data and LVDS video source synchronizing signal.

The LVDS video signal decoding unit 2 of four LINK, comprising:

LVDS audio video synchronization buffer module 2-1, by global clock path, convert the LVDS pixel clock of LINK1 to LVDS video source pixel clock, use the LVDS video source pixel clock of inputted LINK1, LINK2, LINK3, LINK4 that LVDS parallel demodulation data are separately write respectively to DC-FIFO(First Input First Output simultaneously, First Input First Output) after middle buffer memory, with LVDS video source pixel clock, read one by one, make it to become synchrodata, avoid between signal, postponing inconsistent caused read error in transmission.The buffer memory degree of depth is large as far as possible, so that all LINK have abundant data to be buffered to offset maximum delay between them.

The LVDS video signal cable order control module 2-2 of four LINK, for the data arrangement order to LINK1, LINK2, LINK3, LINK4 when receiving LVDS video signal cable sequence control signal.

LVDS video synchronization signal decoder module 2-3, for the LINK1 sorting being decoded and recovers LVDS video source synchronizing signal output with sequential logic mode of operation with LVDS video source pixel clock according to the VESA of the LVDS video decode control signal receiving from video conversion configurations unit 5 and JEIDA transfer encoding standard, synchronizing signal comprises: video level line synchronizing signal (Hsync), video perpendicualr field synchronizing signal (Vsync), video data useful signal (DE).

The LVDS video data decoding module 2-4 of four LINK, for according to 5 VESA of LVDS video decode control signal that receive and the pixel color component level of JEIDA transfer encoding standard and LVDS video source is wide respectively the LVDS demodulating data of LINK1, LINK2, LINK3, LINK4 is decoded with sequential logic mode of operation with LVDS video source pixel clock from video conversion configurations unit, decode the LVDS video source data signal of four LINK and export.

Left and right split screen type rgb video signal converting unit 3, for the LVDS video source data of four links and LVDS video source synchronizing signal being converted to left half screen rgb video signal and right half screen rgb video signal according to LVDS synchronous mode control signal, after converting, MIPI video conversion starting signal being sent to video conversion configurations unit 5 left and right split screen type rgb video signal converting units 3 and comprises:

LVDS video buffer module 3-1, for receiving LVDS video source data and LVDS video source synchronizing signal the buffer memory of four links, LVDS video buffer module 3-1 first inputs LVDS synchronizing signal, when first complete video line being detected and start, according to synchronizing signal DE, detect LVDS video line resolution, and when next video line starts by LVDS video line resolution, LVDS video clock, LVDS synchronizing signal with send the LVDS data of four links to left and right split screen type rgb video modular converter 3-4, send RGB conversion starting signal simultaneously.

Rgb video clock generating module 3-2, for generation of rgb video clock, starts LVDS video buffer module 3-1 after rgb video clock stable.By PLL configuration parameter, ordered pair PLL carries out reconfiguration operation during according to its dynamic recognition, the frequency of LVDS video source pixel clock is become to twice, the frequency-doubled signal producing is adjusted its phase place again and is made it to keep phase place strictly identical with LVDS video source pixel clock, (to guarantee to sample correctly, reliably LVDS data in the follow-up operation of the sequential logic in conversion process), after de-jitter, entering global clock path stable, that nothing swings, is the rgb video clock of LVDS video source pixel clock twice thereby produce frequency again.

Rgb video clock output adjusting module 3-3, for the processing that rgb video clock is carried out, due to rgb video source data signals and rgb video clock synchronous, therefore the rgb video clock phase of input is postponed to half clock cycle as RGB clock signal, make it effectively along center that can be in rgb video source data, thereby guarantee that follow-up conversion operations is by this clock RGB data of correctly sampling, this signal carries out de-jitter more afterwards, and exported by high speed signal Buffer Unit, to guarantee that this output clock has higher stability and good signal quality.

Left and right split screen type rgb video modular converter 3-4, left and right split screen type rgb video modular converter 3-4 receives RGB conversion starting signal, LVDS synchronizing signal sampling 3-4-1, LVDS video pixel sampling 3-4-2 in odd even split screen rgb video modular converter 3-4 synchronously sample to the LVDS video source data of LVDS video source synchronizing signal and four links with LVDS video source pixel clock respectively, and are written in corresponding FIFO buffer memory.To LVDS video source synchronizing signal, according to the form of " Vs, Hs, DE, Vs, Hs, DE ", be copied into the parallel synchronizing signal of two-way, with LVDS video source pixel clock, be written in synchronizing signal FIFO buffer memory 3-4-3; LVDS video source data forms parallel data according to " LINK1, LINK2, LINK3, LINK4 " form simultaneously, according to the capable resolution of inputted LVDS, according to LVDS video line resolution value, with LVDS video source pixel clock, every row LVDS video source signal is divided into the sampling of front hemistich parallel data, rear hemistich parallel data and alternately writes successively buffer memory in front hemistich pixel FIFO buffer memory 3-4-4, rear hemistich pixel FIFO buffer memory 3-4-5.After first complete line has been inputted, its front hemistich parallel data, rear hemistich parallel data and synchronizing signal be buffer memory all.

Rgb signal sampling 3-4-6 reads front hemistich parallel data, rear hemistich parallel data and synchronizing signal with rgb video clock simultaneously, is converted into respectively left half screen rgb video data, right half screen rgb video data and rgb video synchronizing signal; Described rgb video synchronizing signal is copied as to two-way, form left half screen rgb video signal and right half screen rgb video signal with left half screen rgb video data, right half screen rgb video data, rgb video clock respectively; When next video line starts, LVDS synchronizing signal and the data of this row continue to be written in corresponding buffer memory on the one hand, produce on the other hand RGB sampling commencing signal, make rgb video clock from corresponding FIFO buffer memory, read left half screen RGB data, right half screen RGB data and synchronizing signal simultaneously; Because read rgb video clock is the twice of write LVDS video source pixel clock, and the bit wide of the data that write and synchronizing signal is read twice, thus the throughput of reading and writing operation equate, the carrying out of conversion operations energy continous-stable.

Rgb video signal output module 3-5, be used for receiving RGB output clock, rgb video source data signals and rgb video synchronizing signal, effective edge of contrast RGB output clock and the phase place between rgb video source data center, utilize time delay to do trim process so that effective edge of RGB output clock and rgb video source data center-aligned, by rgb video source data signals and the output of rgb video synchronizing signal, when having rgb video source data signals and the output of rgb video synchronizing signal, postpone to produce MIPI video conversion starting signal and send video conversion configurations unit 5 to.

Left and right split screen type MIPI vision signal converting unit 4, for respectively left half screen rgb video signal and right half screen rgb video signal are converted to left passage MIPI vision signal and right passage MIPI vision signal when receive MIPI video conversion starting command from video conversion configurations unit 5, send 8LANE left and right split screen type MIPI to and show module 6, left passage MIPI vision signal and right passage MIPI vision signal are for the MIPI demonstration module of 8LANE left and right split screen type.

Left and right split screen type MIPI vision signal converting unit 4, comprising:

MIPI register module 4-1, for control configuration and the operation that left road MIPI vision signal modular converter 4-2 and right wing MIPI vision signal modular converter 4-3 carry out MIPI conversion according to the MIPI register command writing simultaneously, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;

Left road MIPI vision signal modular converter 4-2, be used for receiving left half screen rgb video signal, execution is converted to left half screen rgb video signal configuration and the conversion operations of left passage MIPI vision signal, send the left passage MIPI vision signal after conversion to MIPI liquid crystal display module connector 4-4, when receiving the order of MIPI conversion configurations from MIPI register module 4-1, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from MIPI register module 4-1, by MIPI liquid crystal display module connector 4-4, be transferred to 8LANE left and right split screen type MIPI and show module 6, when receiving MIPI conversion starting command from MIPI register module 4-1, start conversion operations,

Right wing MIPI vision signal modular converter 4-3, be used for receiving right half screen rgb video signal, execution is converted to right half screen rgb video signal configuration and the conversion operations of right passage MIPI vision signal, send the right passage MIPI vision signal after conversion to MIPI liquid crystal display module connector 4-4, when receiving the order of MIPI conversion configurations from MIPI register module 4-1, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from MIPI register module 4-1, by MIPI liquid crystal display module connector 4-4, be transferred to 8LANE left and right split screen type MIPI and show module 6, when receiving MIPI conversion starting command from MIPI register module 4-1, start conversion operations,

MIPI liquid crystal display module connector 4-4, for receive left passage MIPI vision signal and right passage MIPI vision signal simultaneously, and show that with 8LANE left and right split screen type MIPI module 6 is connected, send left passage MIPI vision signal and right passage MIPI vision signal to 8LANE left and right split screen type MIPI demonstration module 6.

Video conversion configurations unit 5, for according to receive the characteristic of LVDS vision signal, LVDS vision signal decoding parametric is set, and product LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS video signal cable sequence control signal send LVDS video signal decoding unit 2 to; LVDS audio video synchronization pattern is set and controls parameter, produce LVDS synchronous mode control signal and send left and right split screen type rgb video signal converting unit 3 to; Read MIPI video conversion configurations parameter left and right split screen type MIPI vision signal converting unit 4 is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command; From left and right split screen type rgb video signal converting unit 3 receives MIPI video conversion starting signal, send MIPI video conversion starting command and send left and right split screen type MIPI vision signal converting unit 4 to.

Video conversion configurations unit 5, comprising:

Manual toggle switch 5-1, for arranging LVDS vision signal decoding parametric;

Jtag interface 5-2, for receiving MIPI video conversion configurations parameter;

MIPI video conversion configurations module 5-3, for LVDS vision signal decoding parametric is converted to LVDS video decode control signal, read MIPI video conversion configurations parameter left and right split screen type MIPI vision signal converting unit 4 is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, when produce MIPI video conversion starting command from left and right split screen type rgb video signal converting unit 3 receives MIPI video changeover control signals, send left and right split screen type MIPI vision signal converting unit 4 to.

Before powering on, the configuration of LVDS video decode and conversion is first manually set to toggle switch 5-1, after powering on, by MIPI video conversion configurations module 5-3, according to its dial-up state, produce LVDS video decode control signal and LVDS video changeover control signal, from jtag interface 5-2, read MIPI video conversion configurations parameter afterwards, and its mode with register command is written in left and right split screen MIPI vision signal converting unit 4 one by one, first write the order of MIPI conversion configurations, when confirming that writing MIPI after left and right split screen type MIPI vision signal converting unit 4 completes configuration beginning normal work shows module initialization command again, after often writing an order, read the state value of its register, to guarantee that command execution completes, ought receive that afterwards MIPI video changeover control signal changes starting command by MIPI and write register, make MIPI video conversion operations start to carry out.

Each functional module of the present utility model all can realize by FPGA, for MIPI video conversion configurations module, 5-3 also can realize its function with common MCU, also can be by realize respectively the conversion of single MIPI signal with two special-purpose MIPI bridging chips for left and right split screen MIPI vision signal converting unit 4.

Claims (8)

1. LVDS vision signal is converted to a 8LANE left and right split screen MIPI video signal device, it is characterized in that: comprising:

LVDS video reception unit (1), for receiving demodulation LVDS vision signal, produces LVDS parallel demodulation data and the LVDS pixel clock of four links, the LVDS vision signal that described LVDS vision signal is four LINK;

LVDS video signal decoding unit (2), be used for according to LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS video signal cable sequence control signal, LVDS parallel demodulation data to described four links are carried out video decode, the LVDS video source data and the LVDS video source synchronizing signal that produce four links, be converted to LVDS video source pixel clock by described LVDS pixel clock;

Left and right split screen type rgb video signal converting unit (3), for the LVDS video source data of described four links and LVDS video source synchronizing signal being converted to left half screen rgb video signal and right half screen rgb video signal according to LVDS synchronous mode control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit (5);

Left and right split screen type MIPI vision signal converting unit (4), for respectively described left half screen rgb video signal and right half screen rgb video signal are converted to left passage MIPI vision signal and right passage MIPI vision signal when receive MIPI video conversion starting command from video conversion configurations unit (5), send 8LANE left and right split screen type MIPI to and show module (6), described left passage MIPI vision signal and right passage MIPI vision signal are for the MIPI demonstration module of 8LANE left and right split screen type;

Video conversion configurations unit (5), for according to receive the characteristic of LVDS vision signal, LVDS vision signal decoding parametric is set, and product LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS video signal cable sequence control signal send described LVDS video signal decoding unit (2) to; LVDS audio video synchronization pattern is set and controls parameter, produce LVDS synchronous mode control signal and send left and right split screen type rgb video signal converting unit (3) to; Read MIPI video conversion configurations parameter left and right split screen type MIPI vision signal converting unit (4) is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command; From described left and right split screen type rgb video signal converting unit (3) receives MIPI video conversion starting signal, send MIPI video conversion starting command and send described left and right split screen type MIPI vision signal converting unit (4) to.

2. LVDS vision signal according to claim 1 is converted to 8LANE left and right split screen MIPI video signal device, it is characterized in that: described LVDS video reception unit (1) comprising:

LVDS video signal interface (1-1), be used for receiving LVDS vision signal, described LVDS vision signal comprises the LVDS vision signal of LINK1, LINK2, LINK3, LINK4, and the LVDS vision signal of described LINK1, LINK2LINK3, LINK4 is alternately transmitted the pixel data of LVDS video successively;

The LVDS clock signal demodulation module (1-3) of four LINK for: the LVDS receive clock to described each LINK receiving carries out demodulation, produces demodulation clock and demodulation enable signal;

The LVDS demodulated data signal module (1-4) of four LINK for: the demodulation clock by described each LINK becomes parallel data with demodulation enable signal to the LVDS data demodulates of this LINK, and described LVDS receive clock is demodulated into described LVDS pixel clock simultaneously.

3. LVDS vision signal according to claim 1 is converted to 8LANE left and right split screen MIPI video signal device, it is characterized in that: described LVDS video signal decoding unit (2) comprising:

LVDS audio video synchronization buffer module (2-1), synchronously reads for the first buffer memory of the LVDS parallel demodulation data to described four LINK again;

LVDS video synchronization signal decoder module (2-3), for the LVDS parallel demodulation decoding data to described four LINK that synchronously read according to the LVDS video decode control signal receiving from described video conversion configurations unit (5), decode the LVDS video source synchronizing signal of four LINK;

LVDS video data decoding module (2-4), for the LVDS parallel demodulation decoding data to described four LINK that synchronously read according to the LVDS video decode control signal receiving from described video conversion configurations unit (5), decode the LVDS video source data signal of four LINK.

4. LVDS vision signal according to claim 1 is converted to 8LANE left and right split screen MIPI video signal device, it is characterized in that: described left and right split screen type rgb video signal converting unit (3) comprising:

LVDS video buffer module (3-1), for receiving LVDS video source data and LVDS video source synchronizing signal the buffer memory of described four links, according to described LVDS video source synchronization signal detection, go out LVDS video line resolution value, described LVDS video line resolution value, LVDS video source data and LVDS video source synchronizing signal are sent to left and right split screen type rgb video modular converter (3-4) and start described left and right split screen type rgb video modular converter (3-4);

Rgb video clock generating module (3-2), for generation of rgb video clock, starts described LVDS video buffer module (3-1) after described rgb video clock stable;

Rgb video clock output adjusting module (3-3), for the phase place of described rgb video clock is adjusted, make its effective edge along center that can be in rgb video source data, then carry out de-jitter, and described rgb video clock is adjusted into RGB output clock;

Left and right split screen type rgb video modular converter (3-4), for being converted to left half screen rgb video signal and right half screen rgb video signal with described rgb video clock by described LVDS video source synchronizing signal and LVDS video source data signal according to described LVDS video line resolution value;

Rgb video signal output module (3-5), be used for receiving described left half screen rgb video signal and right half screen rgb video signal output, during output, described RGB output clock is adjusted, when having described left half screen rgb video signal and the output of right half screen rgb video signal, postpone to produce MIPI video conversion starting signal and send described video conversion configurations unit (5) to.

5. LVDS vision signal according to claim 1 is converted to 8LANE left and right split screen MIPI video signal device, it is characterized in that: described left and right split screen type MIPI vision signal converting unit (4) comprising:

MIPI register module (4-1), for control configuration and the operation that left road MIPI vision signal modular converter (4-2) and right wing MIPI vision signal modular converter (4-3) carry out MIPI conversion according to the MIPI register command writing simultaneously, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;

Left half screen MIPI vision signal modular converter (4-2), be used for receiving described left half screen rgb video signal, execution is converted to described left half screen rgb video signal configuration and the conversion operations of left passage MIPI vision signal, send the left passage MIPI vision signal after conversion to MIPI liquid crystal display module connector (4-4), when receiving the order of MIPI conversion configurations from described MIPI register module (4-1), complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module (4-1), by described MIPI liquid crystal display module connector (4-4), be transferred to 8LANE left and right split screen type MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module (4-1), start conversion operations,

Right half screen MIPI vision signal modular converter (4-3) is for receiving described right half screen rgb video signal, execution is converted to described right half screen rgb video signal configuration and the conversion operations of right passage MIPI vision signal, send the right passage MIPI vision signal after conversion to MIPI liquid crystal display module connector (4-4), when receiving the order of MIPI conversion configurations from described MIPI register module (4-1), complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module (4-1), by described MIPI liquid crystal display module connector (4-4), be transferred to 8LANE left and right split screen type MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module (4-1), start conversion operations,

MIPI liquid crystal display module connector (4-4), for receive described left passage MIPI vision signal and right passage MIPI vision signal simultaneously, and show that with 8LANE left and right split screen type MIPI module (6) is connected, send described left passage MIPI vision signal and right passage MIPI vision signal to described 8LANE left and right split screen type MIPI demonstration module (6).

6. LVDS vision signal according to claim 1 is converted to 8LANE left and right split screen MIPI video signal device, it is characterized in that: described video conversion configurations unit (5) comprising:

Manual toggle switch (5-1), for arranging LVDS vision signal decoding parametric;

Jtag interface (5-2), for receiving MIPI video conversion configurations parameter;

MIPI video conversion configurations module (5-3), for LVDS vision signal decoding parametric is converted to LVDS video decode control signal, read MIPI video conversion configurations parameter described left and right split screen type MIPI vision signal converting unit (4) is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, when receiving MIPI video changeover control signal from described left and right split screen type rgb video signal converting unit (3), produce MIPI video conversion starting command and send described left and right split screen type MIPI vision signal converting unit (4) to.

7. LVDS vision signal according to claim 2 is converted to 8LANE left and right split screen MIPI video signal device, it is characterized in that: described LVDS video reception unit (1) also comprises:

LVDS video reception termination module (1-2), be used for the operation that is terminated of received LVDS vision signal, then send described LVDS receive clock and LVDS data to LVDS clock signal demodulation module (1-3) and LVDS signal demodulation module (1-4) respectively, described terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild, compensation is because of long signal distortion that Distance Transmission causes, decay, reduce transmission and disturb, guarantee received LVDS signal quality;

LVDS demodulation dynamic calibration module (1-5), for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.

8. LVDS vision signal according to claim 3 is converted to 8LANE left and right split screen MIPI video signal device, it is characterized in that: described LVDS video signal decoding unit (2) also comprises LVDS video signal cable order control module (2-2), for the data arrangement order to described LINK1, LINK2, LINK3, LINK4 when receiving described LVDS video signal cable sequence control signal.

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