CN203504677U - Device for converting LVDS video signal into MIPI video signal - Google Patents
Device for converting LVDS video signal into MIPI video signal Download PDFInfo
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- CN203504677U CN203504677U CN201320596043.1U CN201320596043U CN203504677U CN 203504677 U CN203504677 U CN 203504677U CN 201320596043 U CN201320596043 U CN 201320596043U CN 203504677 U CN203504677 U CN 203504677U
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Abstract
The utility model discloses a device for converting an LVDS video signal into an MIPI video signal. The device comprises an LVDS video signal receiving unit, an LVDS video signal decoding unit, an RGB video signal converting unit, an MIPI video signal converting unit and a video conversion configuration unit, wherein the LVDS video signal receiving unit is used for receiving and demodulating the LVDS video signal and generating LVDS parallel demodulation data and an LVDS pixel clock; the LVDS video signal decoding unit is used for carrying out video decoding on the LVDS parallel demodulation data according to an LVDS video decoding control signal and generating LVDS video source data and an LVDS video source synchronizing signal; the RGB video signal converting unit is used for converting the LVDS video source data and the LVDS video source synchronizing signal into an RGB video signal according to an LVDS video converting control signal; the MIPI video signal converting unit is used for converting the RGB video signal to the MIPI video signal; and the video conversion configuration unit is used for setting LVDS video signal decoding parameters according to the characteristic of the LVDS video signal to be received, generating the LVDS video decoding control signal, sending the LVDS video decoding control signal to the LVDS video signal decoding unit, setting LVDS video signal converting parameters, generating the LVDS video converting control signal and sending the LVDS video converting control signal to the RGB video signal converting unit.
Description
Technical field
The utility model relates to demonstration field and the field tests of liquid crystal module, refers to that particularly a kind of LVDS vision signal is converted to MIPI video signal device.
Background technology
Liquid crystal display module (Liquid Crystal Display Module, hereinafter to be referred as liquid crystal module) is the critical component that liquid crystal display can normally show, it is by liquid crystal display screen, original paper backlight, Graphics Processing chip and the electric circuit constitute.Liquid crystal display module structure is accurate, processing procedure is complicated, manufacturing technique requirent is high, in order to guarantee yields when producing, need to produce various test video signals by special liquid crystal module testing apparatus and be input in liquid crystal module and show, strictly, comprehensively detect its display effect.Its display interface of common liquid crystals module of using on TV, display product at present and inner Graphics Processing circuit are used LVDS(Low-Voltage Differential Signaling, Low Voltage Differential Signal) signal carrys out work.And existing liquid crystal module testing device also corresponding output be that LVDS vision signal is to realize the test of module.Because common liquid crystals module production time is of a specified duration, output is large, so its module testing apparatus also uses in a large number.
Along with people constantly pursue high definition more, display effect more true to nature on mobile device, portable equipment, therefore common liquid crystals module cannot meet the need gradually.So occurred on market that a kind of novel liquid crystal module with ultrahigh resolution and very-high solution density meets people's demand.The interface of this liquid crystal module and inner Graphics Processing circuit adopt MIPI(Mobile Industry Processor Interface to move industry processor interface) signaling interface.This interface is formulated by the MIPI alliance that comprises the companies such as ARM, Samsung, Intel, object is that handle is mobile, inner each assembly of portable equipment is as nuclear interface standardizings such as camera, display screen, processors and opens each other, thereby improved performance, reduced cost and power consumption.MIPI interface can not only be supported ultrahigh resolution and refresh rate, and has farther transmission range, better Electro Magnetic Compatibility, and therefore the liquid crystal module with MIPI interface has become development trend.
Yet the testing apparatus of MIPI liquid crystal module need to be exported same MIPI test signal, but existing common liquid crystals module testing apparatus does not have this function, and common liquid crystals module also continues to produce, its testing apparatus does not enter the replacement cycle yet will be continued to use.Although module manufacturer also produces MIPI liquid crystal module, in order to protect investment, to reduce production costs, can not eliminate existing equipment, again make a big purchase expensive MIPI module Special testing device in large quantities.In order to produce cheaply MIPI liquid crystal module in enormous quantities within short-term and to guarantee its yields, just still reuse on a large scale existing common module testing apparatus.
Therefore, need a kind of conversion equipment LVDS vision signal can be converted to MIPI vision signal, common liquid crystals module testing apparatus can be tested MIPI module by this conversion equipment.This conversion equipment is not only wanted dependable performance, integrated efficient but also is wanted low price, easy and simple to handle simultaneously.
Summary of the invention
The purpose of this utility model is to provide a kind of LVDS vision signal to be converted to MIPI video signal device, and it has feature simple to operate, that detection efficiency is high, cost is low.
For achieving the above object, the designed LVDS vision signal of the utility model is converted to MIPI video signal device, its special character in, comprising:
LVDS video reception unit, for receiving demodulation LVDS vision signal, produces LVDS parallel demodulation data and LVDS pixel clock;
LVDS video signal decoding unit, be used for according to LVDS video decode control signal, described LVDS parallel demodulation data are carried out to video decode, produce LVDS video source data and LVDS video source synchronizing signal, described LVDS pixel clock is converted to LVDS video source pixel clock;
Rgb video signal converting unit, for described LVDS video source data and LVDS video source synchronizing signal being converted to rgb video signal according to LVDS video changeover control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit;
MIPI vision signal converting unit, sends MIPI demonstration module to for described rgb video signal being converted to MIPI vision signal when receive MIPI video conversion starting command from video conversion configurations unit;
Video conversion configurations unit, for according to the characteristic of the LVDS vision signal that will receive, arranges LVDS vision signal decoding parametric, produces LVDS video decode control signal, sends described LVDS video signal decoding unit to; LVDS video conversion parameter is set, produces LVDS video changeover control signal, send described rgb video signal converting unit to; Read MIPI video conversion configurations parameter MIPI vision signal converting unit is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command; From described rgb video signal converting unit receives MIPI video conversion starting signal, send MIPI video conversion starting command and send described MIPI vision signal converting unit to.
Further, described LVDS video reception unit comprises:
LVDS video signal interface, for receiving LVDS vision signal, described LVDS vision signal comprises the LVDS vision signal of single LINK, two LINK, four LINK;
LVDS clock signal demodulation module is used for: the LVDS receive clock to described each LINK receiving carries out demodulation, produces demodulation clock and demodulation enable signal;
LVDS demodulated data signal module is used for: the demodulation clock by described each LINK becomes parallel data with demodulation enable signal to the LVDS data demodulates of this LINK, and described LVDS receive clock is demodulated into LVDS pixel clock simultaneously.
Further, described LVDS video signal decoding unit comprises:
LVDS audio video synchronization buffer module, for described LVDS pixel clock is converted to LVDS video source pixel clock, synchronously reads the first buffer memory of the LVDS parallel demodulation data of described each LINK again;
LVDS video synchronization signal decoder module, for the LVDS parallel demodulation decoding data to described each LINK synchronously reading according to the LVDS video decode control signal receiving from described video conversion configurations unit, decodes LVDS video source synchronizing signal;
LVDS video data decoding module, for the LVDS parallel demodulation decoding data to each LINK synchronously reading according to the LVDS video decode control signal receiving from described video conversion configurations unit, decodes the LVDS video source data signal of each LINK.
Further, described rgb video signal converting unit comprises:
Rgb video signal self-adaptive control module, produces the rgb video clock configuration signal matching according to described LVDS video changeover control signal, together with LVDS video source pixel clock, send rgb video clock adaptive configuration module to, according to described LVDS video changeover control signal, produce RGB modulus of conversion block selection signal together with the LVDS video source data signal of each LINK, LVDS video source synchronizing signal sends single-link pattern rgb video modular converter to together with rgb video clock, dual link pattern rgb video modular converter, four link mode rgb video modular converters, left and right span mode rgb video modular converter, odd even span mode rgb video modular converter, detect LVDS video synchronization signal calculated level resolution value, send horizontal resolution value to described single-link pattern rgb video modular converter,
Rgb video clock adaptive configuration module, for producing configurable clock generator and enable signal according to described rgb video clock configuration signal, sends described rgb video clock generating module to together with described LVDS video source pixel clock;
Rgb video clock generating module, sends described rgb video signal self-adaptive control module and rgb video clock output adjusting module to for produce described rgb video clock according to configurable clock generator and enable signal;
Rgb video clock output adjusting module, for the phase place of described rgb video clock is adjusted, make its effective edge along center that can be in rgb video source data, then carry out de-jitter, and described rgb video clock is adjusted into RGB output clock sends rgb video signal output module to;
Single-link pattern rgb video modular converter, sends described rgb video signal output module to for the LVDS video source synchronizing signal of single LINK and LVDS video source data are converted to rgb video signal;
Dual link pattern rgb video modular converter, sends rgb video signal output module to for the LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to rgb video signal;
Four link mode rgb video modular converters, send rgb video signal output module to for the LVDS video source synchronizing signal of four LINK and LVDS video source data are converted to rgb video signal;
Left and right span mode rgb video modular converter, for being converted to left half screen rgb video signal by the LVDS video source synchronizing signal of four LINK and LVDS video source data, right half screen rgb video signal sends rgb video signal output module to;
Odd even span mode rgb video modular converter, for being converted to strange pixel rgb video signal by the LVDS video source synchronizing signal of four LINK and LVDS video source data, dual pixel rgb video signal sends rgb video signal output module to;
Rgb video signal output module is used for: according to RGB modulus of conversion block selection signal, select corresponding rgb video signal to send described MIPI vision signal converting unit to together with described RGB output clock.
Further, described MIPI vision signal converting unit comprises:
MIPI register module, for control configuration and the operation that left road MIPI vision signal modular converter and right wing MIPI vision signal modular converter carry out MIPI conversion according to the MIPI register command writing simultaneously, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;
Left road MIPI vision signal modular converter, be used for receiving described rgb video signal, execution is converted to described rgb video signal configuration and the conversion operations of left passage MIPI vision signal, send the left passage MIPI vision signal after conversion to MIPI liquid crystal display module connector, when receiving the order of MIPI conversion configurations from described MIPI register module, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module, by described MIPI liquid crystal display module connector, be transferred to MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module, start conversion operations,
Right wing MIPI vision signal modular converter is used for receiving described rgb video signal, execution is converted to described rgb video signal configuration and the conversion operations of right passage MIPI vision signal, send the right passage MIPI vision signal after conversion to MIPI liquid crystal display module connector, when receiving the order of MIPI conversion configurations from described MIPI register module, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module, by described MIPI liquid crystal display module connector, be transferred to MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module, start conversion operations,
MIPI liquid crystal display module connector, for receive described left passage MIPI vision signal and right passage MIPI vision signal simultaneously, and show that with MIPI module is connected, send described left passage MIPI vision signal and right passage MIPI vision signal to described MIPI demonstration module.
Further, described video conversion configurations unit comprises:
Manual toggle switch, for arranging LVDS vision signal decoding parametric and LVDS video conversion parameter;
Jtag interface, for receiving MIPI video conversion configurations parameter;
MIPI video conversion configurations module, for being converted to LVDS video decode control signal, LVDS vision signal decoding parametric sends described LVDS video signal decoding unit to, LVDS video conversion parameter is converted to LVDS video changeover control signal, send described rgb video signal converting unit to, read MIPI video conversion configurations parameter described MIPI vision signal converting unit is sent to the order of MIPI conversion configurations, MIPI shows module initialization command, when receiving MIPI video conversion starting signal from described rgb video signal converting unit, produce MIPI video conversion starting command and send described MIPI vision signal converting unit to.
Further, described LVDS video reception unit also comprises:
LVDS video reception termination module, be used for the operation that is terminated of received LVDS vision signal, then send described LVDS receive clock and LVDS data to LVDS clock signal demodulation module and LVDS signal demodulation module respectively, described terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild, compensation is because of long signal distortion that Distance Transmission causes, decay, reduce transmission and disturb, guarantee received LVDS signal quality;
LVDS demodulation dynamic calibration module, for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.
Further, described LVDS video signal decoding unit also comprises LVDS vision signal order module, for the data of described two link LINK1 and LINK2 being exchanged when receiving described LVDS odd even pixel reverse control signal, while receiving described LVDS video signal cable sequence control signal to described four links according to LINK1, LINK2, LINK3, LINK4 ordering.
The beneficial effects of the utility model are:
(1) the utility model can be converted to LVDS vision signal MIPI vision signal.The utility model, by arranging, all can well mate different qualities such as the multiple color range of LVDS vision signal, transmission means, coded systems; To dissimilar MIPI liquid crystal module, all can change out the desired MIPI vision signal of display mode with it.
(2) the LVDS vision signal of convertible 6,8,10 color ranges of the utility model, the convertible LVDS signal based on VESA and JEIDA transfer encoding, can change the LVDS transmission mode of single LINK, two LINK, four LINK, the MIPI signal of changing has single whole screen display mode, left and right split screen display mode, odd even split screen display mode, shows that module, 8LANE left and right split screen type MIPI show that module and 8LANE odd even split screen type MIPI show module respectively applicable to the single whole screen type MIPI of 4LANE.
(3) the utility model is before use only by manually changing toggle switch state applicable to different LVDS vision signals; Before the different MIPI liquid crystal module of application, need to receive this module running parameter by jtag interface.
(4) single FPGA(field programmable logic array for the utility model) chip just can be realized described repertoire; FPGA is a kind of programmable semicustom chip, can realize the synchronous processing of multilink video data, parallel conversion, can reach higher performance, not only working stability, realization are easily, and low price, avoided the problems such as design complexity because using various special chips to cause, poor stability, design cost height.
(5) video resolution that the utility model is supported is higher, not only integrated level is high, reliable operation, antijamming capability are strong, and simple to operate, economical and practical, can not only promote the detection efficiency of MIPI liquid crystal module, reduce its equipment cost and production cost, also will further improve the universal of MIPI display device.
Accompanying drawing explanation
Fig. 1 is the utility model block diagram;
Fig. 2 a is the circuit block diagram of LVDS video reception unit and LVDS video signal decoding unit in Fig. 1;
Fig. 2 b is the circuit block diagram of rgb video signal converting unit in Fig. 1, MIPI vision signal converting unit and video conversion configurations unit;
In figure: 1.LVDS video reception unit, 1-1.LVDS video signal interface, 1-2.LVDS video reception termination module, the LVDS clock signal demodulation module of 1-3. tetra-LINK, the LVDS demodulated data signal module of 1-4. tetra-LINK, 1-5.LVDS demodulation dynamic calibration module;
2.LVDS video signal decoding unit, 2-1.LVDS audio video synchronization buffer module, the LVDS video signal cable order control module of 2-2. tetra-LINK, 2-3.LVDS video synchronization signal decoder module, the LVDS video data decoding module of 2-4. tetra-LINK;
3.RGB vision signal converting unit, 3-1.RGB video signal self-adaptive control module, 3-2.RGB video clock adaptive configuration module, 3-3RGB. video clock generation module, 3-4.RGB video clock output adjusting module, 3-5. single-link pattern rgb video modular converter, 3-6. dual link pattern rgb video modular converter, 3-7. tetra-link mode rgb video modular converters, 3-8. left and right span mode rgb video modular converter, 3-9. odd even span mode rgb video modular converter, 3-10.RGB vision signal output module;
4.MIPI vision signal converting unit, 4-1.MIPI register module, the left road of 4-2. MIPI vision signal modular converter, 4-3. right wing MIPI vision signal modular converter, 4-4.MIPI liquid crystal display module connector;
5. video conversion configurations unit, the manual toggle switch of 5-1., 5-2.JTAG interface, 5-3.MIPI video conversion configurations module;
6.MIPI shows module.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Shown in a, Fig. 2 b, a kind of LVDS vision signal of the utility model is converted to MIPI video signal device, comprising as shown in Figure 1, Figure 2:
LVDS video reception unit 1, LVDS video signal decoding unit 2, rgb video signal converting unit 3, MIPI vision signal converting unit 4 and video conversion configurations unit 5.
LVDS video reception unit 1, for receiving demodulation LVDS vision signal, produces LVDS parallel demodulation data and LVDS pixel clock.
LVDS video reception unit 1 comprises:
LVDS video signal interface 1-1, be used for receiving LVDS vision signal, LVDS vision signal comprises the LVDS vision signal of single LINK, two LINK, four LINK, the LVDS vision signal of single LINK is that LINK1 transmits all video pixels, the LVDS vision signal of two LINK, comprise LINK1, bis-links of LINK2, transmit respectively odd even video pixel; The LVDS vision signal of four LINK, comprises four links, according to transmitting successively at LINK1, LINK2, LINK3, LINK4 of video pixel order; MIPI vision signal comprises that the MIPI of the single whole screen type of 4LANE, 8LANE left and right split screen type and 8LANE odd even split screen type shows module, when the MIPI vision signal that will change is exported to the MIPI demonstration module of the single whole screen type of 4LANE, LVDS vision signal is transmitted with single, double, four LINK modes; When the MIPI vision signal that will change is exported to the MIPI liquid crystal display module of 8LANE left and right split screen type, 8LANE odd even split screen type, LVDS vision signal is only transmitted in four LINK modes.The LVDS vision signal of each link comprises LVDS receive clock and LVDS data, and LVDS data are transmitted by LVDS data/address bus, and LVDS data/address bus comprises some root holding wires, and every holding wire transmits serial code signal.LVDS video signal interface 1-1, by connecting LVDS transmission line interface, input LVDS vision signal, interface comprises two kinds of input pads: industrial standard ox horn seat connector and Miniature high-density business connector, to guarantee that the utility model all can be suitable in industrial environment and business environment, when some connectors have the input of LVDS signal, interface can be automatically from this connector output, and when two connectors have signal input, interface acquiescence is exported from Miniature high-density business connector.
LVDS video reception termination module 1-2, for the operation that is terminated of received LVDS vision signal, then sends LVDS receive clock and LVDS data to LVDS clock signal demodulation module 1-3 and LVDS signal demodulation module 1-4 respectively.Terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild, compensation is because of long signal distortion that Distance Transmission causes, decay, reduce transmission and disturb, guarantee received LVDS signal quality.The process of termination comprises: before receiving LVDS signal, carry out ESD(Electro Static Discharge static discharge) protective treatment disturbs to eliminate the strong discharge impact of moment, then carries out common-mode noise filtering processing to suppress line noise, to improve anti-electromagnetic interference capability.The distortion causing with erasure signal transmission is processed in the impedance matching that is terminated when receiving signal, and also the additional interference of further erasure signal is carried out equilibrium and the processing of postemphasising to signal, to eliminate the signal attenuation being caused because of loss simultaneously.Afterwards again to signal Hyblid Buffer Amplifier, and through the judgement of reference level, reconstruct high-quality LVDS vision signal.
LVDS clock signal demodulation module 1-3 is used for: the LVDS receive clock to each LINK receiving carries out demodulation, produces demodulation clock and demodulation enable signal; Demodulating process comprises: LVDS receive clock is input to PLL(Phase Locked Loop phase-locked loop through High Speed I/O buffering) its frequency multiplication is arrived to LVDS frequency data signal, and carry out high-frequency clock conversion process, produce the LVDS demodulation clock with LVDS data same frequency, with LVDS pixel clock and the LVDS demodulation gating signal of LVDS receive clock with frequency, and output in high-frequency clock network, make them there is very low delay and jitter, very strong driving force, guarantee reliable and stable LVDS data to be carried out to demodulation.When LVDS receive clock being carried out to frequency multiplication operation with PLL, from the moving calibrating signal of clock jitter removing of LVDS demodulation dynamic calibration module 1-5, also sending into PLL simultaneously controls this operating process is carried out to anti-shake, it is produced and be not subject to that input jiffer affects, stable frequency-doubled signal, guarantee that demodulation operation can not make mistakes without interruption.
LVDS demodulated data signal module 1-4 is used for: the demodulation clock by each LINK becomes parallel data with demodulation enable signal to the LVDS data demodulates of this LINK, and LVDS receive clock is demodulated into LVDS pixel clock simultaneously.Its process comprises: to each data independently demodulation respectively in LVDS serial data bus.Each LVDS data-signal is first buffered in the high speed signal network of low delay, low jitter, postponed again data bit bit period half, make this data value that samples that LVDS demodulation clock can be correct at the center of each LVDS data bit, and according to demodulation gating signal, it is periodically blocked to bunchiness data, with LVDS video source pixel clock, do string again and turn and process the parallel demodulation data that obtain this LVDS signal, by trigger Buffer output to guarantee signal stabilization, reliably.The demodulation that each LVDS holding wire is all run simultaneously, makes each holding wire no matter how data all can phase mutual interference not cause demodulation mistake.
When the bit value by LVDS demodulation clock sampling LVDS data, from the data dithering removal calibrating signal of LVDS demodulation dynamic calibration module 1-5, also this operating process is carried out to anti-shake simultaneously and control, it is produced and be not subject to that input jiffer affects, reliable and stable demodulating data.
In the phase delay process of data input, be subject to all the time the LVDS data flow phase alignment signal controlling of LVDS demodulation dynamic calibration module 1-5, when the phase place between demodulation clock and LVDS data has deviation, phase alignment signal is made its delay adjustment contrary with phase deviation on data delay half period basis, data center is alignd along maintenance with the sampling of demodulation clock all the time, guarantee correctly to sample data.
When demodulation gating signal is blocked serial data, also the bit for demodulation byte-aligned that is subject to LVDS demodulation dynamic calibration module 1-5 moves calibrating signal and controls, and makes it the start bit of the parallel data of cutting apart move on next serial data position.
LVDS demodulation dynamic calibration module 1-5, for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.
LVDS video signal decoding unit 2, for according to LVDS video decode control signal, carries out video decode to LVDS parallel demodulation data, produces LVDS video source data and LVDS video source synchronizing signal.
LVDS video signal decoding unit 2, comprising:
LVDS audio video synchronization buffer module 2-1, by global clock path, convert the LVDS pixel clock of LINK1 to LVDS video source pixel clock, use the LVDS pixel clock of each inputted LINK that LVDS parallel demodulation data are separately write respectively to DC-FIFO(First Input First Output simultaneously, First Input First Output) after middle buffer memory, with LVDS video source pixel clock, read one by one, make it to become synchrodata, avoid between signal, postponing inconsistent caused read error in transmission.The buffer memory degree of depth is large as far as possible, so that all LINK have abundant data to be buffered to offset maximum delay between them.
LVDS vision signal order module 2-2, for the data of two link LINK1 and LINK2 being exchanged when receiving LVDS odd even pixel reverse control signal, while receiving LVDS video signal cable sequence control signal to four links according to LINK1, LINK2, LINK3, LINK4 ordering.
LVDS video synchronization signal decoder module 2-3, for according to the LVDS parallel demodulation decoding data of the 5 LVDS video decode control signals that receive to each LINK synchronously reading from video conversion configurations unit, decodes LVDS video source synchronizing signal; According to the VESA in LVDS video decode control signal and JEIDA transfer encoding standard, the LINK1 after sorting is decoded and recovers LVDS video source synchronizing signal output with sequential logic mode of operation with LVDS video source pixel clock, synchronizing signal comprises: video level line synchronizing signal (Hsync), video perpendicualr field synchronizing signal (Vsync), video data useful signal (DE).
LVDS video data decoding module 2-4, for according to the LVDS parallel demodulation decoding data of the 5 LVDS video decode control signals that receive to each LINK synchronously reading from video conversion configurations unit, decodes the LVDS video source data signal of each LINK.
Rgb video signal converting unit 3, for according to LVDS video changeover control signal, LVDS video source data and LVDS video source synchronizing signal being converted to rgb video signal, sends MIPI video conversion starting signal to video conversion configurations unit 5 after converting.
Rgb video signal converting unit 3, comprising:
Rgb video signal self-adaptive control module 3-1, according to LVDS video changeover control signal produce the list match/bis-/the rgb video clock configuration signal of tetra-LINK patterns, together with LVDS video source pixel clock, send rgb video clock adaptive configuration module 3-2 to, according to LVDS video changeover control signal, produce RGB modulus of conversion block selection signal together with the LVDS video source data signal of each LINK, LVDS video source synchronizing signal sends single-link pattern rgb video modular converter 3-5 to together with rgb video clock, dual link pattern rgb video modular converter 3-6, four link mode rgb video modular converter 3-7, left and right span mode rgb video modular converter 3-8, odd even span mode rgb video modular converter 3-9, detect LVDS video synchronization signal calculated level resolution value, send horizontal resolution value to single-link pattern rgb video modular converter 3-5,
Rgb video clock adaptive configuration module 3-2, for according to produced list/bis-/the rgb video clock configuration signal of tetra-LINK patterns, by local clock signal produce corresponding single/bis-/configuration parameter and the configuration enable signal of tetra-LINK patterns, clock generating module is carried out to dynamic recognition operation, make rgb video clock generating module 3-3 automatically produce needed rgb video clock signal, single when being configured to/bis-/during tetra-LINK patterns, LVDS video source pixel clock is converted into the rgb video pixel clock (hereinafter to be referred as RGB clock) of its same frequency/bis-frequency multiplication/quadruple, in four LINK patterns, when rgb video signal is changed by left and right split screen or odd even span mode, LVDS video source pixel clock is converted into the rgb video pixel clock of its two frequency multiplication.
Rgb video clock generating module 3-3, for sending rgb video signal self-adaptive control module 3-1 and rgb video clock output adjusting module 3-4 to according to configurable clock generator and enable signal generation rgb video clock.By PLL configuration parameter, ordered pair PLL carries out reconfiguration operation during according to its dynamic recognition, make it LVDS pixel clock carry out corresponding frequency multiplication operation, produce frequency-doubled signal adjust again its phase place and make it to keep phase place strictly identical with LVDS pixel clock, (to guarantee to sample correctly, reliably LVDS data in the follow-up operation of the sequential logic in conversion process), after de-jitter, enter again global clock path stable, that nothing swings, thereby produce rgb video clock.
Rgb video clock output adjusting module 3-4, due to rgb video source data signals and rgb video clock synchronous, therefore the rgb video clock phase of input is postponed to half clock cycle as RGB clock signal, make it effectively along center that can be in rgb video source data, thereby guarantee that follow-up conversion operations is by this clock RGB data of correctly sampling, this signal carries out de-jitter more afterwards, and output it to rgb video signal output module 3-10 by high speed signal Buffer Unit, to guarantee that this output clock has higher stability and good signal quality.
With RGB clock, LVDS video source synchronizing signal is become to rgb video synchronizing signal and data with data transaction; When MIPI liquid crystal display module is the whole screen type of 4LANE, according to LINK translative mode control signal, carry out separately the video conversion of the mono-LINK of LVDS, two LINK, four LINK patterns; When showing that module is 8LANE split screen type, MIPI carries out separately the video conversion of left and right span mode and odd even span mode according to changeover control signal.
Single-link pattern rgb video modular converter 3-5, sends rgb video signal output module 3-10 to for the LVDS video source synchronizing signal of single LINK and LVDS video source data are converted to rgb video signal;
Dual link pattern rgb video modular converter 3-6, sends rgb video signal output module 3-10 to for the LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to rgb video signal;
Four link mode rgb video modular converter 3-7, send rgb video signal output module 3-10 to for the LVDS video source synchronizing signal of four LINK and LVDS video source data are converted to rgb video signal;
Left and right span mode rgb video modular converter 3-8, for being converted to left half screen rgb video signal by the LVDS video source synchronizing signal of four LINK and LVDS video source data, right half screen rgb video signal sends rgb video signal output module 3-10 to, the video transfer process of carrying out left and right span mode is: left and right span mode rgb video modular converter 3-8 by the LVDS data of four LINK according to " LINK1, LINK2, LINK3, LINK4 " form composition parallel data, according to inputted LVDS synchronizing signal, determine when first complete video line is initial, according to row resolution value drawn in aforementioned, with LVDS clock by front, the LINK parallel data sampling of rear hemistich also writes respectively a left side, in right half screen DC-FIFO, buffer memory is also read separately data cached simultaneously and is separated into left half screen RGB data by the rgb video clock of two frequencys multiplication on the other hand, right half screen RGB data and synchronizing signal, form left half screen rgb video signal and right half screen rgb video signal, because the throughput of data and synchronizing signal read-write operation is equal, therefore the carrying out of conversion operations energy continous-stable.
Odd even span mode rgb video modular converter 3-9, for being converted to strange pixel rgb video signal by the LVDS video source synchronizing signal of four LINK and LVDS video source data, dual pixel rgb video signal sends rgb video signal output module 3-10 to; The video transfer process of carrying out odd even span mode is: odd even span mode rgb video modular converter 3-9 first detects the LINK of two strange pixels and two dual pixels in the LVDS of four LINK data, again LVDS synchronizing signal being formed respectively to parallel data with strange, even each two LINK data processes according to the two LINK pattern conversion regimes in aforementioned, thereby the rgb video data and the RGB synchronizing signal that produce separately strange pixel, dual pixel, form strange pixel rgb video signal and dual pixel rgb video signal.
Rgb video signal output module 3-10 is used for: according to RGB modulus of conversion block selection signal, select corresponding rgb video signal to send MIPI vision signal converting unit 4 to together with RGB output clock.When producing synchronous mode and control to video synchronization signal reverse operating; Effective edge of contrast RGB output clock and the phase place between the sampling center of RGB data, and by signal lag assembly, respectively output clock and data are done to fine delay and process to eliminate phase difference between the two, guarantee that output clock is effectively along the sampling center in data all the time.
MIPI vision signal converting unit 4, sends MIPI demonstration module 6 to for rgb video signal being converted to MIPI vision signal when receive MIPI video conversion starting command from video conversion configurations unit 5;
MIPI vision signal converting unit 4, comprising:
MIPI register module 4-1, for control configuration and the operation that left road MIPI vision signal modular converter 4-2 and right wing MIPI vision signal modular converter 4-3 carry out MIPI conversion according to the MIPI register command writing simultaneously, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;
Left road MIPI vision signal modular converter 4-2, be used for receiving rgb video signal, execution is converted to rgb video signal configuration and the conversion operations of left passage MIPI vision signal, send the left passage MIPI vision signal after conversion to MIPI liquid crystal display module connector 4-4, when receiving the order of MIPI conversion configurations from MIPI register module 4-1, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from MIPI register module 4-1, by MIPI liquid crystal display module connector 4-4, be transferred to MIPI and show module, when receiving MIPI conversion starting command from MIPI register module 4-1, start conversion operations,
Right wing MIPI vision signal modular converter 4-3, be used for receiving rgb video signal, execution is converted to rgb video signal configuration and the conversion operations of right passage MIPI vision signal, send the right passage MIPI vision signal after conversion to MIPI liquid crystal display module connector 4-4, when receiving the order of MIPI conversion configurations from MIPI register module 4-1, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from MIPI register module 4-1, by MIPI liquid crystal display module connector 4-4, be transferred to MIPI and show module, when receiving MIPI conversion starting command from MIPI register module 4-1, start conversion operations,
When modulus of conversion block selection signal is single, double, four LINK pattern, its RGB data and synchronizing signal (whole screen signal) is copied into two-way and exports to MIPI vision signal converting unit 4; When selecting left and right split screen translative mode, left and right half screen data and synchronizing signal are exported respectively left half screen rgb video signal, right half screen rgb video signal Gei Zuo road MIPI vision signal modular converter 4-2 and right wing MIPI vision signal modular converter 4-3; When selecting odd even split screen translative mode, strange pixel parallel data, dual pixel parallel data and synchronizing signal are exported respectively the strange split screen vision signal of RGB and the even split screen vision signal of RGB to MIPI vision signal converting unit 4.
MIPI liquid crystal display module connector 4-4, for receive left passage MIPI vision signal and right passage MIPI vision signal simultaneously, and show that with MIPI module 6 is connected, send left passage MIPI vision signal and right passage MIPI vision signal to MIPI demonstration module 6.
Video conversion configurations unit 5, for according to the characteristic of the LVDS vision signal that will receive, arranges LVDS vision signal decoding parametric, produces LVDS video decode control signal, sends LVDS video signal decoding unit 2 to; LVDS video conversion parameter is set, produces LVDS video changeover control signal, send rgb video signal converting unit 3 to; Read MIPI video conversion configurations parameter MIPI vision signal converting unit 4 is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command; From rgb video signal converting unit 3 receives MIPI video conversion starting signal, send MIPI video conversion starting command and send MIPI vision signal converting unit 4 to.
Video conversion configurations unit 5, comprising:
Manual toggle switch 5-1, for arranging LVDS vision signal decoding parametric and LVDS video conversion parameter;
Jtag interface 5-2, for receiving MIPI video conversion configurations parameter;
MIPI video conversion configurations module 5-3, for being converted to LVDS video decode control signal, LVDS vision signal decoding parametric sends LVDS video signal decoding unit 2 to, LVDS video conversion parameter is converted to LVDS video changeover control signal, send rgb video signal converting unit 3 to, read MIPI video conversion configurations parameter MIPI vision signal converting unit 4 is sent to the order of MIPI conversion configurations, MIPI shows module initialization command, when produce MIPI video conversion starting command from rgb video signal converting unit 3 receives MIPI video conversion starting signal, send MIPI vision signal converting unit 4 to.
Before powering on, the configuration of LVDS video decode and conversion is first manually set to toggle switch 5-1, after powering on, by MIPI video conversion configurations module 5-3, according to its dial-up state, produce LVDS video decode control signal and LVDS video changeover control signal, from jtag interface 5-2, read MIPI video conversion configurations parameter afterwards, and its mode with register command is written in MIPI vision signal converting unit 4 one by one, first write the order of MIPI conversion configurations, when confirming that writing MIPI after MIPI vision signal converting unit 4 completes configuration beginning normal work shows module initialization command again, after often writing an order, read the state value of its register, to guarantee that command execution completes, ought receive that afterwards MIPI video changeover control signal changes starting command by MIPI and write register, make MIPI video conversion operations start to carry out.
Each functional module of the present utility model all can realize by FPGA, for MIPI video conversion configurations module, 5-3 also can realize its function with common MCU, also can be by realize respectively the conversion of single MIPI signal with two special-purpose MIPI bridging chips for MIPI vision signal converting unit 4.
The utility model is not limited to above-mentioned execution mode; for those skilled in the art, be also considered as the protection range of the utility model patent according to know-why of the present utility model and scheme or some improvement of making, change, retouching, distortion, replacement under enlightenment of the present utility model within.
The content not being described in detail in this specification, write a Chinese character in simplified form, term belongs to the known prior art of professional and technical personnel in the field.
Claims (8)
1. LVDS vision signal is converted to a MIPI video signal device, it is characterized in that: comprising:
LVDS video reception unit (1), for receiving demodulation LVDS vision signal, produces LVDS parallel demodulation data and LVDS pixel clock;
LVDS video signal decoding unit (2), for according to LVDS video decode control signal, carries out video decode to described LVDS parallel demodulation data, produces LVDS video source data and LVDS video source synchronizing signal;
Rgb video signal converting unit (3), for described LVDS video source data and LVDS video source synchronizing signal being converted to rgb video signal according to LVDS video changeover control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit (5);
MIPI vision signal converting unit (4), sends MIPI demonstration module (6) to for described rgb video signal being converted to MIPI vision signal when receive MIPI video conversion starting command from video conversion configurations unit (5);
Video conversion configurations unit (5), for according to the characteristic of the LVDS vision signal that will receive, arranges LVDS vision signal decoding parametric, produces LVDS video decode control signal, sends described LVDS video signal decoding unit (2) to; LVDS video conversion parameter is set, produces LVDS video changeover control signal, send described rgb video signal converting unit (3) to; Read MIPI video conversion configurations parameter MIPI vision signal converting unit (4) is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command; From described rgb video signal converting unit (3) receives MIPI video conversion starting signal, send MIPI video conversion starting command and send described MIPI vision signal converting unit (4) to.
2. LVDS vision signal according to claim 1 is converted to MIPI video signal device, it is characterized in that: described LVDS video reception unit (1) comprising:
LVDS video signal interface (1-1), for receiving LVDS vision signal, described LVDS vision signal comprises the LVDS vision signal of single LINK, two LINK, four LINK;
LVDS clock signal demodulation module (1-3) for: the LVDS receive clock to described each LINK receiving carries out demodulation, produces demodulation clock and demodulation enable signal;
LVDS demodulated data signal module (1-4) for: the demodulation clock by described each LINK becomes parallel data with demodulation enable signal to the LVDS data demodulates of this LINK, and described LVDS receive clock is demodulated into LVDS pixel clock simultaneously.
3. LVDS vision signal according to claim 1 is converted to MIPI video signal device, it is characterized in that: described LVDS video signal decoding unit (2) comprising:
LVDS audio video synchronization buffer module (2-1), for described LVDS pixel clock is converted to LVDS video source pixel clock, synchronously reads the first buffer memory of the LVDS parallel demodulation data of described each LINK again;
LVDS video synchronization signal decoder module (2-3), for the LVDS parallel demodulation decoding data to described each LINK synchronously reading according to the LVDS video decode control signal receiving from described video conversion configurations unit (5), decode LVDS video source synchronizing signal;
LVDS video data decoding module (2-4), for the LVDS parallel demodulation decoding data to each LINK synchronously reading according to the LVDS video decode control signal receiving from described video conversion configurations unit (5), decode the LVDS video source data signal of each LINK.
4. LVDS vision signal according to claim 1 is converted to MIPI video signal device, it is characterized in that: described rgb video signal converting unit (3) comprising:
Rgb video signal self-adaptive control module (3-1), produces the rgb video clock configuration signal matching according to described LVDS video changeover control signal, together with LVDS video source pixel clock, send rgb video clock adaptive configuration module (3-2) to, according to described LVDS video changeover control signal, produce RGB modulus of conversion block selection signal together with the LVDS video source data signal of each LINK, LVDS video source synchronizing signal sends single-link pattern rgb video modular converter (3-5) to together with rgb video clock, dual link pattern rgb video modular converter (3-6), four link mode rgb video modular converters (3-7), left and right span mode rgb video modular converter (3-8), odd even span mode rgb video modular converter (3-9), detect LVDS video synchronization signal calculated level resolution value, send horizontal resolution value to described single-link pattern rgb video modular converter (3-5),
Rgb video clock adaptive configuration module (3-2), for producing configurable clock generator and enable signal according to described rgb video clock configuration signal, sends described rgb video clock generating module (3-3) to together with described LVDS video source pixel clock;
Rgb video clock generating module (3-3), sends described rgb video signal self-adaptive control module (3-1) and rgb video clock output adjusting module (3-4) to for produce described rgb video clock according to configurable clock generator and enable signal;
Rgb video clock output adjusting module (3-4), for the phase place of described rgb video clock is adjusted, make its effective edge along center that can be in rgb video source data, carry out again de-jitter, and described rgb video clock is adjusted into RGB output clock sends rgb video signal output module (3-10) to;
Single-link pattern rgb video modular converter (3-5), sends rgb video signal output module (3-10) to for the LVDS video source synchronizing signal of single LINK and LVDS video source data are converted to rgb video signal;
Dual link pattern rgb video modular converter (3-6), sends rgb video signal output module (3-10) to for the LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to rgb video signal;
Four link mode rgb video modular converters (3-7), send rgb video signal output module (3-10) to for the LVDS video source synchronizing signal of four LINK and LVDS video source data are converted to rgb video signal;
Left and right span mode rgb video modular converter (3-8), for being converted to left half screen rgb video signal by the LVDS video source synchronizing signal of four LINK and LVDS video source data, right half screen rgb video signal sends rgb video signal output module (3-10) to;
Odd even span mode rgb video modular converter (3-9), for being converted to strange pixel rgb video signal by the LVDS video source synchronizing signal of four LINK and LVDS video source data, dual pixel rgb video signal sends rgb video signal output module (3-10) to;
Rgb video signal output module (3-10) for: according to RGB modulus of conversion block selection signal, select corresponding rgb video signal to send described MIPI vision signal converting unit (4) to together with described RGB output clock.
5. LVDS vision signal according to claim 1 is converted to MIPI video signal device, it is characterized in that: described MIPI vision signal converting unit (4) comprising:
MIPI register module (4-1), for control configuration and the operation that left road MIPI vision signal modular converter (4-2) and right wing MIPI vision signal modular converter (4-3) carry out MIPI conversion according to the MIPI register command writing simultaneously, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;
Left road MIPI vision signal modular converter (4-2), be used for receiving described rgb video signal, execution is converted to described rgb video signal configuration and the conversion operations of left passage MIPI vision signal, send the left passage MIPI vision signal after conversion to MIPI liquid crystal display module connector (4-4), when receiving the order of MIPI conversion configurations from described MIPI register module (4-1), complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module (4-1), by described MIPI liquid crystal display module connector (4-4), be transferred to MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module (4-1), start conversion operations,
Right wing MIPI vision signal modular converter (4-3) is for receiving described rgb video signal, execution is converted to described rgb video signal configuration and the conversion operations of right passage MIPI vision signal, send the right passage MIPI vision signal after conversion to MIPI liquid crystal display module connector (4-4), when receiving the order of MIPI conversion configurations from described MIPI register module (4-1), complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module (4-1), by described MIPI liquid crystal display module connector (4-4), be transferred to MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module (4-1), start conversion operations,
MIPI liquid crystal display module connector (4-4), for receive described left passage MIPI vision signal and right passage MIPI vision signal simultaneously, and show that with MIPI module (6) is connected, send described left passage MIPI vision signal and right passage MIPI vision signal to described MIPI demonstration module (6).
6. LVDS vision signal according to claim 3 is converted to MIPI video signal device, it is characterized in that: described video conversion configurations unit (5) comprising:
Manual toggle switch (5-1), for arranging LVDS vision signal decoding parametric and LVDS video conversion parameter;
Jtag interface (5-2), for receiving MIPI video conversion configurations parameter;
MIPI video conversion configurations module (5-3), for being converted to LVDS video decode control signal, LVDS vision signal decoding parametric sends described LVDS video signal decoding unit (2) to, LVDS video conversion parameter is converted to LVDS video changeover control signal, send described rgb video signal converting unit (3) to, read MIPI video conversion configurations parameter described MIPI vision signal converting unit (4) is sent to the order of MIPI conversion configurations, MIPI shows module initialization command, when receiving MIPI video conversion starting signal from described rgb video signal converting unit (3), produce MIPI video conversion starting command and send described MIPI vision signal converting unit (4) to.
7. LVDS vision signal according to claim 2 is converted to MIPI video signal device, it is characterized in that: described LVDS video reception unit (1) also comprises:
LVDS video reception termination module (1-2), be used for the operation that is terminated of received LVDS vision signal, then send described LVDS receive clock and LVDS data to LVDS clock signal demodulation module (1-3) and LVDS signal demodulation module (1-4) respectively, described terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild, compensation is because of long signal distortion that Distance Transmission causes, decay, reduce transmission and disturb, guarantee received LVDS signal quality;
LVDS demodulation dynamic calibration module (1-5), for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.
8. LVDS vision signal according to claim 3 is converted to MIPI video signal device, it is characterized in that: described LVDS video signal decoding unit (2) also comprises LVDS vision signal order module (2-2), for the data of described two link LINK1 and LINK2 being exchanged when receiving described LVDS odd even pixel reverse control signal, while receiving described LVDS video signal cable sequence control signal to described four links according to LINK1, LINK2, LINK3, LINK4 ordering.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104836975A (en) * | 2015-05-26 | 2015-08-12 | 武汉精测电子技术股份有限公司 | Method and device capable of enhancing signal output capacity of video converter board |
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| CN104836975A (en) * | 2015-05-26 | 2015-08-12 | 武汉精测电子技术股份有限公司 | Method and device capable of enhancing signal output capacity of video converter board |
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| CN105049773A (en) * | 2015-06-29 | 2015-11-11 | 武汉精测电子技术股份有限公司 | Method of transforming LVDS video signal into DP video signal and system of transforming LVDS video signal into DP video signal |
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