CN203691524U - Device for converting double LINKLVDS video signals to MIPI video signals - Google Patents

Abstract

The utility model discloses a device for converting double LINK LVDS video signals to MIPI video signals, comprising a reception unit of double LINK LVDS video signals for receiving and demodulating the LVDS video signals of double LINK and generating parallel demodulation data and a pixel clock, a double LINK LVDS video signal decoding unit for performing video decoding on parallel demodulation data of the double LINK and generating double LINK LVDS video source signals comprising video source data and video source synchronization signals, an RGB video signal conversion unit for converting the double LINK video source signals to the RGB video signals comprising RGB video source data, synchronization signals and an RGB video clock, an MIPI video signal conversion unit for converting the RGB video signals to the MIPI video signals and transmitting the MIPI video signals to an MIPI display module, a video conversion configuration unit for generating LVDS video signal decoding signals, LVDS synchronization mode control signals, and executing configuration operation of the MIPI conversion processing and initialization operation of the MIPI display module.

Description

Two LINKLVDS vision signal conversion MIPI video signal devices

Technical field

The utility model relates to demonstration field and the field tests of liquid crystal module, refers to particularly a kind of two LINKLVDS vision signal conversion MIPI video signal device.

Background technology

Liquid crystal display module (Liquid Crystal Display Module, hereinafter to be referred as liquid crystal module) is the critical component that liquid crystal display can normally show, it is by liquid crystal display screen, original paper backlight, Graphics Processing chip and the electric circuit constitute.Liquid crystal display module structure precision, processing procedure complexity, manufacturing technique requirent are high, in order to guarantee yields in the time producing, need to produce various test video signals by special liquid crystal module testing apparatus and be input in liquid crystal module and show, strictly, comprehensively detect its display effect.Its display interface of common liquid crystals module of using on TV, display product at present and inner Graphics Processing circuit use LVDS(Low-Voltage Differential Signaling, Low Voltage Differential Signal) signal carrys out work.And existing liquid crystal module testing device also corresponding output be that LVDS vision signal is to realize the test of module.Because common liquid crystals module production time is of a specified duration, output is large, therefore its module testing apparatus also uses in a large number.

Along with people constantly pursue high definition more, display effect more true to nature on mobile device, portable equipment, therefore common liquid crystals module cannot meet the need gradually.So occurred on market that a kind of novel liquid crystal module with ultrahigh resolution and very-high solution density meets people's demand.The interface of this liquid crystal module and inner Graphics Processing circuit adopt MIPI(Mobile Industry Processor Interface to move industry processor interface) signaling interface.This interface is formulated by the MIPI alliance including the companies such as ARM, Samsung, Intel, object is that handle is mobile, the inner each assembly of portable equipment is as nuclear interface standardizings such as camera, display screen, processors and opens each other, thereby improve performance, reduced cost and power consumption.MIPI interface can not only be supported ultrahigh resolution and refresh rate, and has farther transmission range, and better Electro Magnetic Compatibility, has therefore become development trend with the liquid crystal module of MIPI interface.

But the testing apparatus of MIPI liquid crystal module need to be exported same MIPI test signal, but existing common liquid crystals module testing apparatus does not have this function, and common liquid crystals module also continue produce, its testing apparatus do not enter yet the replacement cycle will continue use.Although module manufacturer also produces MIPI liquid crystal module, in order to protect investment, to reduce production costs, can not eliminate existing equipment, again make a big purchase expensive MIPI module Special testing device in large quantities.In order to produce cheaply MIPI liquid crystal module in enormous quantities within short-term and to ensure its yields, just still reuse on a large scale existing common module testing apparatus.

Therefore, need a kind of conversion equipment to convert the LVDS signal of two LINK to MIPI signal, common liquid crystals module testing apparatus can be tested MIPI module by this conversion equipment.This conversion equipment is not only wanted dependable performance, integrated efficient but also is wanted low price, easy and simple to handle simultaneously.

Summary of the invention

The purpose of this utility model is to provide a kind of two LINKLVDS vision signal conversion MIPI video signal device, and it has feature simple to operate, that detection efficiency is high, cost is low.

For achieving the above object, two LINKLVDS vision signal conversion MIPI video signal devices that the utility model is designed, its special character is, comprising:

The LVDS video reception unit of two LINK, for the LVDS vision signal of the two LINK of receiving demodulation, produces LVDS parallel demodulation data and the LVDS pixel clock of two LINK;

The LVDS video signal decoding unit of two LINK, for described LVDS pixel clock is converted to LVDS video source pixel clock, and according to LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal, LVDS parallel demodulation data to described couple of LINK are carried out video decode, the LVDS video source signal that produces two LINK, described LVDS video source signal comprises LVDS video source data and LVDS video source synchronizing signal;

Rgb video signal converting unit, for converting the LVDS video source signal of described couple of LINK to rgb video signal according to LVDS synchronous mode control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit, described rgb video signal comprises rgb video source data, rgb video synchronizing signal and rgb video clock;

MIPI vision signal converting unit, described rgb video signal is converted to MIPI vision signal when receiving MIPI video to change starting command from video conversion configurations unit and sends MIPI demonstration module to, described MIPI vision signal shows module for the MIPI of 4LANE type;

Video conversion configurations unit, be used for according to the characteristic of the LVDS vision signal of two LINK that will receive, LVDS vision signal decoding parametric is set, and generation LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal send the LVDS video signal decoding unit of described couple of LINK to; LVDS audio video synchronization pattern control parameter is set, produces LVDS synchronous mode control signal and send rgb video signal converting unit to; Read MIPI video conversion configurations parameter MIPI vision signal converting unit is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, send described MIPI vision signal converting unit to when send MIPI video conversion starting command from described rgb video signal converting unit receives MIPI video conversion starting signal.

Further, the LVDS video reception unit of described couple of LINK comprises:

LVDS video signal interface, for receiving the LVDS vision signal of two LINK, the LVDS vision signal of described couple of LINK comprises the LVDS vision signal of LINK1 and LINK2, the LVDS vision signal of described LINK1, LINK2 is transmitted respectively strange, the dual pixel data of LVDS video, the LVDS vision signal of described each LINK comprises respectively LVDS receive clock and LVDS data, described LVDS data are transmitted by LVDS data/address bus, described LVDS data/address bus comprises some holding wires, and every holding wire transmits serial code signal; Described MIPI vision signal shows module for the MIPI of 4LANE type;

The LVDS clock signal demodulation module of two LINK is used for: the LVDS receive clock to the described each LINK receiving carries out demodulation, produces demodulation clock and demodulation enable signal;

The LVDS demodulated data signal module of two LINK is used for: be demodulated to separately respectively parallel data by the demodulation clock of described each LINK and the signal of the LVDS data/address bus of demodulation enable signal to this LINK, parallel data after demodulation is formed to the parallel demodulation data of this LINK, described LVDS receive clock is demodulated into described LVDS pixel clock simultaneously.

Further, the LVDS video signal decoding unit of described couple of LINK comprises:

LVDS audio video synchronization buffer module, synchronously reads for the first buffer memory of the LVDS parallel demodulation data to described couple of LINK again, and described LVDS pixel clock is converted to LVDS video source pixel clock;

LVDS video synchronization signal decoder module, for the LVDS parallel demodulation decoding data to the described couple of LINK synchronously reading according to the LVDS video decode control signal receiving from described video conversion configurations unit, decode the LVDS video source synchronizing signal of two LINK;

The LVDS video data decoding module of two LINK, for the LVDS parallel demodulation decoding data to the described couple of LINK synchronously reading according to the LVDS video decode control signal receiving from described video conversion configurations unit, decode the LVDS video source data signal of two LINK.

Further, described rgb video signal converting unit comprises:

Rgb video clock generating module, for generation of rgb video clock;

Rgb video modular converter, for converting the LVDS video source synchronizing signal of described couple of LINK and LVDS video source data signal to rgb video synchronizing signal and rgb video source data signals with described rgb video clock;

Rgb video clock output adjusting module, for the phase place of described rgb video clock is adjusted, makes its effective edge along can be in the center of rgb video source data, then carries out de-jitter, and described rgb video clock is adjusted into RGB output clock;

Rgb video signal output module, be used for receiving described RGB output clock, rgb video source data signals and rgb video synchronizing signal, contrast the phase place between effective edge and the described rgb video source data center of described RGB output clock, utilize time delay to do trim process so that effective edge of described RGB output clock and rgb video source data center-aligned, by described rgb video source data signals and the output of rgb video synchronizing signal, in the time having described rgb video source data signals and the output of rgb video synchronizing signal, postpone to produce MIPI video conversion starting signal and send described video conversion configurations unit to.

Further, described MIPI vision signal converting unit comprises:

MIPI register module, for carry out configuration and the operation of MIPI conversion according to the MIPI register command control MIPI vision signal modular converter writing, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;

MIPI vision signal modular converter, be used for receiving described rgb video signal, carry out configuration and the conversion operations of described rgb video signal conversion MIPI signal, in the time receiving the order of MIPI conversion configurations from described MIPI register module, complete corresponding configuration, conversion operations, when receive MIPI demonstration module initialization command from described MIPI register module, be transferred to MIPI by MIPI liquid crystal display module connector and show module, when receive MIPI conversion starting command from described MIPI register module, start conversion operations;

MIPI liquid crystal display module connector, for receiving described MIPI vision signal, and shows that with MIPI module is connected, and sends described MIPI vision signal to described MIPI and shows module.

Further, described video conversion configurations unit comprises:

Manually toggle switch, for arranging LVDS vision signal decoding parametric;

Jtag interface, for receiving MIPI video conversion configurations parameter;

MIPI video conversion configurations module, for LVDS vision signal decoding parametric is converted to LVDS video decode control signal, read MIPI video conversion configurations parameter described MIPI vision signal converting unit is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, when receiving MIPI video changeover control signal from described rgb video signal converting unit, produce MIPI video conversion starting command and send described MIPI vision signal converting unit to.

Further, the LVDS video reception unit of described couple of LINK also comprises:

LVDS video reception termination module, be used for the operation that is terminated of received LVDS vision signal, then send described LVDS receive clock and LVDS data to the LVDS clock signal demodulation module of two LINK and the LVDS signal demodulation module of two LINK respectively, described terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild, compensation is because of long signal distortion that Distance Transmission causes, decay, reduce transmission and disturb, guarantee received LVDS signal quality;

LVDS demodulation dynamic calibration module, for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.

Further, the LVDS video signal decoding unit of described couple of LINK also comprises the LVDS odd even vision signal control module of two LINK, while oppositely control, the data of LINK1, LINK2 is exchanged for containing odd even pixel when the LVDS vision signal of two LINK of reception.

The beneficial effects of the utility model are:

(1) the utility model can convert the LVDS vision signal of two LINK to MIPI vision signal.By arranging, the different qualities such as multiple color range to LVDS vision signal, transmission means, coded system all can well mate.

(2) the LVDS vision signal of convertible 6,8,10 color ranges of the utility model, the convertible LVDS signal based on VESA and JEIDA transfer encoding, can change the LVDS transmission mode of two LINK, is applicable to the MIPI liquid crystal module of 4LANE type.

(3) the utility model is before use only by manually changing toggle switch state applicable to different LVDS vision signals; Before the different MIPI liquid crystal module of application, need to receive this module running parameter by jtag interface.

(4) single FPGA(field programmable logic array for the utility model) chip just can realize described repertoire; FPGA is a kind of programmable semicustom chip, can realize the synchronous processing of multilink video data, parallel conversion, can reach higher performance, not only working stability, realization are easily, and low price, avoid the problems such as design complexity because using various special chips to cause, poor stability, design cost height.

(5) video resolution that the utility model is supported is higher, not only integrated level is high, reliable operation, antijamming capability are strong, and simple to operate, economical and practical, can not only promote the detection efficiency of MIPI liquid crystal module, reduce its equipment cost and production cost, also will further improve the universal of MIPI display device.

Brief description of the drawings

Fig. 1 is the utility model block diagram;

Fig. 2 a is the circuit block diagram of LVDS video reception unit and LVDS video signal decoding unit in Fig. 1;

Fig. 2 b is the circuit block diagram of rgb video signal converting unit in Fig. 1, MIPI vision signal converting unit and video conversion configurations unit;

Fig. 3 is the circuit diagram of rgb video modular converter in Fig. 2 b;

Fig. 4 is the signal graph that the LVDS vision signal of two LINK is converted to rgb video signal;

In figure: 1. the LVDS video reception unit of couple LINK, 1-1.LVDS video signal interface, 1-2.LVDS video reception termination module, the LVDS clock signal demodulation module of the two LINK of 1-3., the LVDS demodulated data signal module of the two LINK of 1-4., 1-5.LVDS demodulation dynamic calibration module;

2. the LVDS video signal decoding unit of couple LINK, 2-1.LVDS audio video synchronization buffer module, the LVDS odd even vision signal control module of the two LINK of 2-2., 2-3.LVDS video synchronization signal decoder module, the LVDS video data decoding module of the two LINK of 2-4.;

3.RGB vision signal converting unit, 3-1.RGB video clock generation module, 3-2.RGB video conversion module, 3-2-1.LVDS signal sampling, 3-2-2.DC-FIFO buffer memory, 3-2-3.RGB signal sampling, 3-3.RGB video clock output adjusting module, 3-4.RGB vision signal output module;

4.MIPI vision signal converting unit, 4-1.MIPI register module, 4-2.MIPI vision signal modular converter, 4-3.MIPI liquid crystal display module connector;

5. video conversion configurations unit, the manual toggle switch of 5-1., 5-2.JTAG interface, 5-3.MIPI video conversion configurations module;

6.MIPI shows module.

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.

As shown in Figures 1 to 4, a kind of two LINKLVDS vision signal conversion MIPI video signal devices of the utility model, comprising:

The LVDS video reception unit 1 of two LINK, the LVDS video signal decoding unit 2 of two LINK, rgb video signal converting unit 3, MIPI vision signal converting unit 4 and video conversion configurations unit 5.

The LVDS video reception unit 1 of two LINK, for the LVDS vision signal of the two LINK of receiving demodulation, produces LVDS parallel demodulation data and the LVDS video source pixel clock of two LINK;

The LVDS video reception unit 1 of two LINK comprises:

LVDS video signal interface 1-1, for receiving the LVDS vision signal of two LINK, the LVDS vision signal of two LINK comprises the LVDS vision signal of LINK1 and LINK2, the LVDS vision signal of LINK1, LINK2 is transmitted respectively strange, the dual pixel data of LVDS video, the LVDS vision signal of each LINK comprises respectively LVDS receive clock and LVDS data, LVDS data are transmitted by LVDS data/address bus, and LVDS data/address bus comprises some holding wires, and every holding wire transmits serial code signal; MIPI vision signal shows module for the MIPI of 4LANE type.LVDS video signal interface 1-1 inputs LVDS vision signal by the LVDS transmission line interface that connects two LINK, interface comprises two kinds of input pads: industrial standard ox horn seat connector and Miniature high-density business connector, to guarantee that the present invention all can be suitable in industrial environment and business environment, in the time that some connectors have the LVDS signal input of two LINK, interface can be automatically from this connector output, in the time that two connectors have signal input, interface acquiescence is exported from Miniature high-density business connector.

LVDS video reception termination module 1-2, for processing that the LVDS vision signal of the two LINK that receive is terminated, guarantee that LVDS signal quality to be demodulated is high, noiseless, then send LVDS receive clock and LVDS data to the LVDS clock signal demodulation module 1-3 of two LINK and the LVDS signal demodulation module 1-4 of two LINK respectively.The process of termination comprises: before the LVDS signal that receives two LINK, carry out ESD(Electro Static Discharge static discharge) protective treatment disturbs with the strong discharge impact of eliminating moment, then carries out common-mode noise filtering processing to suppress line noise, to improve anti-electromagnetic interference capability.The impedance matching that is terminated in the time receiving signal is processed and is transmitted with erasure signal the distortion causing, also the additional interference of further erasure signal is carried out equilibrium and the processing of postemphasising to signal, to eliminate the signal attenuation being caused because of loss simultaneously.Afterwards again to signal Hyblid Buffer Amplifier, and reconstruct the LVDS vision signal of high-quality couple of LINK through the judgement of reference level.

LVDS clock signal demodulation module 1-3 is used for: the LVDS receive clock of the each LINK after terminated operation is carried out respectively to demodulation, produce LVDS pixel clock, demodulation clock and demodulation enable signal the LVDS data of this LINK are carried out to demodulation; Demodulating process comprises: LVDS receive clock is input to PLL(Phase Locked Loop phase-locked loop through High Speed I/O buffering) its frequency multiplication is arrived to LVDS frequency data signal, and carry out high-frequency clock conversion process, produce the LVDS demodulation clock with LVDS data same frequency, with LVDS pixel clock and the LVDS demodulation gating signal of LVDS receive clock with frequency, and output in high-frequency clock network, make them there is very low delay and jitter, very strong driving force, guarantee reliable and stable LVDS data to be carried out to demodulation.In the time LVDS receive clock being carried out to frequency multiplication operation with PLL, also send into PLL from the moving calibrating signal of clock jitter removing of LVDS demodulation dynamic calibration module 1-5 controls this operating process is carried out to anti-shake simultaneously, it is produced and be not subject to that input jiffer affects, stable frequency-doubled signal, guarantee that demodulation operation can not make mistakes without interruption.

LVDS demodulated data signal module 1-4 is used for: be demodulated to separately respectively LVDS parallel data demodulating data by the demodulation clock of each LINK and the signal of the LVDS data/address bus of demodulation enable signal to this LINK, its process comprises: to each serial data independently demodulation respectively in LVDS data/address bus.Each LVDS data-signal is first buffered to low delay, in the high speed signal network of low jitter, postponed again data bit bit period half, make this data value that samples that LVDS demodulation clock can be correct at the center of each LVDS data bit, and according to demodulation gating signal, it is periodically blocked to bunchiness data, doing string with LVDS video source pixel clock again turns and processes the parallel demodulation data that obtain this LVDS signal, each LVDS demodulating data is merged into the LVDS parallel demodulation data of this LINK, by trigger Buffer output to guarantee signal stabilization, reliably.The demodulation that each LVDS holding wire is all run simultaneously, makes each holding wire no matter how data all can phase mutual interference not cause demodulation mistake.

In the time of the bit value by LVDS demodulation clock sampling LVDS data, also this operating process is carried out to anti-shake from the data dithering removal calibrating signal of LVDS demodulation dynamic calibration module 1-5 simultaneously and control, it is produced and be not subject to that input jiffer affects, reliable and stable demodulating data.

All the time be subject to the LVDS data flow phase alignment signal controlling of LVDS demodulation dynamic calibration module 1-5 in the phase delay process of data input, in the time that the phase place between demodulation clock and LVDS data has deviation, phase alignment signal is made its delay adjustment contrary with phase deviation on data delay half period basis, data center is alignd along maintenance with the sampling of demodulation clock all the time, guarantee correctly to sample data.

When demodulation gating signal is blocked serial data, also the bit for demodulation byte-aligned that is subject to LVDS demodulation dynamic calibration module 1-5 moves calibrating signal control, makes it the start bit of the parallel data of cutting apart move on next serial data position.

LVDS demodulation dynamic calibration module 1-5, for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.

The LVDS video signal decoding unit 2 of two LINK is for according to LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal, LVDS parallel demodulation data to described couple of LINK are carried out video decode, the LVDS video source signal that produces two LINK, LVDS video source signal comprises LVDS video source data and LVDS video source synchronizing signal.

The LVDS video signal decoding unit 2 of two LINK, comprising:

LVDS audio video synchronization buffer module 2-1, convert the LVDS pixel clock of LINK1 to LVDS video source pixel clock by global clock path, use the LVDS video source pixel clock of inputted LINK1, LINK2 that LVDS parallel demodulation data are separately write respectively to DC-FIFO(First Input First Output simultaneously, First Input First Output) in after buffer memory, read one by one with LVDS video source pixel clock, make it to become synchrodata, avoid between signal, postponing inconsistent caused read error in transmission.The buffer memory degree of depth is large as far as possible, so that all LINK have abundant data to be buffered to offset maximum delay between them.

The LVDS odd even vision signal control module 2-2 of two LINK, to the data of LINK1, LINK2 exchanges while oppositely control for containing odd even pixel when the LVDS vision signal of two LINK receiving.

LVDS video synchronization signal decoder module 2-3, for the LINK1 LVDS video source pixel clock sorting being decoded and recovered LVDS video source synchronizing signal output with sequential logic mode of operation according to the VESA of the LVDS video decode control signal receiving from video conversion configurations unit 5 and JEIDA transfer encoding standard, synchronizing signal comprises: video level line synchronizing signal (Hsync), video perpendicualr field synchronizing signal (Vsync), video data useful signal (DE).

The LVDS video data decoding module 2-4 of two LINK, for according to the VESA of LVDS video decode control signal that receives from video conversion configurations unit 5 with the pixel color component level of JEIDA transfer encoding standard and LVDS video source is wide respectively the LVDS demodulating data LVDS video source pixel clock of LINK1, LINK2 is decoded with sequential logic mode of operation, recover the LVDS video source data signal of two LINK and export.

Rgb video signal converting unit 3, for converting the LVDS video source signal of two LINK to rgb video signal according to LVDS synchronous mode control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit 5, rgb video signal comprises rgb video source data, rgb video synchronizing signal and rgb video clock.

Rgb video signal converting unit 3 comprises:

Rgb video clock generating module 3-1, for generation of rgb video clock.By PLL configuration parameter, ordered pair PLL carries out reconfiguration operation during according to its dynamic recognition, the frequency of LVDS video source pixel clock is become to twice, the frequency-doubled signal producing is adjusted its phase place again and is made it to keep phase place strictly identical with LVDS pixel clock, (to guarantee to sample correctly, reliably LVDS data in the follow-up operation of the sequential logic in conversion process), after de-jitter, entering global clock path stable, that nothing swings, is the rgb video clock of LVDS video source pixel clock twice thereby produce frequency again.

Rgb video modular converter 3-2, for converting rgb video source data signals and rgb video synchronizing signal with rgb video clock to by the LVDS video source synchronizing signal of two LINK with LVDS video source data signal.Rgb video modular converter 3-2 is combined into the LVDS data of the LVDS video source synchronizing signal of two LINK and synchronous LINK1, LINK2 the parallel data of a link according to the form of " LINK1-data, synchronizing signal, LINK2-data, synchronizing signal ", in LVDS signal sampling 3-2-1, sample with LVDS video source pixel clock, and write buffer memory in DC-FIFO buffer memory 3-2-2; Rgb signal sampling 3-2-3 reads parallel data with rgb video clock, and isolates rgb video source data and rgb video synchronizing signal, thereby completes conversion process.For data, because LINK1, LINK2 transmit respectively very, even data (being determined by odd even reverse control signal), therefore RGB data are actual is that alternately to export LINK1,2(strange-even) data, thereby complete the conversion of all data, for synchronizing signal, because RGB clock has read twice to it within each LVDS clock cycle, therefore the video sequential of RGB and LVDS is consistent; For transfer process, because DC-FIFO writes the data volume of twice with the clock of a times a unit interval, and by the data volume of one times of the Clockreading of twice, the throughput that is read-write operation equates, therefore there will not be and write completely or read empty situation, i.e. the carrying out of conversion operations energy continous-stable.

Rgb video clock output adjusting module 3-3, due to rgb video source data signals and rgb video clock synchronous, therefore the rgb video clock phase of input is postponed to half clock cycle as RGB clock signal, effectively edge can be in the center of rgb video source data to make it, thereby guarantee that follow-up conversion operations is by this clock RGB data of correctly sampling, this signal carries out de-jitter more afterwards, and exported by high speed signal Buffer Unit, to guarantee that this output clock has higher stability and good signal quality.

Rgb video signal output module 3-4, be used for receiving RGB output clock, rgb video source data signals and rgb video synchronizing signal, phase place between effective edge and the rgb video source data center of contrast RGB output clock, utilize time delay to do trim process so that effective edge of RGB output clock and rgb video source data center-aligned, by rgb video source data signals and the output of rgb video synchronizing signal, in the time having rgb video source data signals and the output of rgb video synchronizing signal, postpone to produce MIPI video conversion starting signal and send video conversion configurations unit 5 to.

MIPI vision signal converting unit 4, send MIPI demonstration module 6 to for rgb video signal being converted to MIPI vision signal when receiving MIPI video to change starting command from video conversion configurations unit 5, MIPI vision signal shows module 6 for the MIPI of 4LANE type.

MIPI vision signal converting unit 4, comprising:

MIPI register module 4-1, for carry out configuration and the operation of MIPI conversion according to the MIPI register command control MIPI vision signal modular converter 4-2 writing, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;

MIPI vision signal modular converter 4-2, be used for receiving rgb video signal, carry out configuration and the conversion operations of rgb video signal being changed to MIPI vision signal, in the time receiving the order of MIPI conversion configurations from MIPI register module 4-1, complete corresponding configuration, conversion operations, when receive MIPI demonstration module initialization command from MIPI register module 4-1, be transferred to MIPI by MIPI liquid crystal display module connector 4-3 and show module 6, when receive MIPI conversion starting command from MIPI register module 4-1, start conversion operations;

MIPI liquid crystal display module connector 4-3, for receiving MIPI vision signal, and shows that with MIPI module 6 is connected, and sends MIPI vision signal to MIPI and shows module 6.

Video conversion configurations unit 5, be used for according to the characteristic of the LVDS vision signal of two LINK that will receive, LVDS vision signal decoding parametric is set, and generation LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal send the LVDS video signal decoding unit 2 of two LINK to; LVDS audio video synchronization pattern control parameter is set, produces LVDS synchronous mode control signal and send rgb video signal converting unit 3 to; Read MIPI video conversion configurations parameter MIPI vision signal converting unit 4 is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command; From rgb video signal converting unit 3 receives MIPI video conversion starting signal, send MIPI video conversion starting command and send MIPI vision signal converting unit 4 to.

Video conversion configurations unit 5, comprising:

Manually toggle switch 5-1, for arranging LVDS vision signal decoding parametric;

Jtag interface 5-2, for receiving MIPI video conversion configurations parameter;

MIPI video conversion configurations module 5-3, for LVDS vision signal decoding parametric is converted to LVDS video decode control signal, read MIPI video conversion configurations parameter MIPI vision signal converting unit 4 is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, when receiving MIPI video changeover control signal from rgb video signal converting unit 3, produce MIPI video conversion starting command and send MIPI vision signal converting unit 4 to.

Before powering on, the configuration of LVDS video decode and conversion is first manually set to toggle switch 5-1, after powering on, produce LVDS video decode control signal and LVDS video changeover control signal by MIPI video conversion configurations module 5-3 according to its dial-up state, read MIPI video conversion configurations parameter from jtag interface 5-2 afterwards, and its mode with register command is written in MIPI vision signal converting unit 4 one by one, first write the order of MIPI conversion configurations, when confirming that writing MIPI after MIPI vision signal converting unit 4 completes configuration beginning normal work shows module initialization command again, when often writing the state value that reads its register after an order, to guarantee that command execution completes, ought receive that afterwards MIPI video changeover control signal changes starting command by MIPI and write register, make MIPI video conversion operations start to carry out.

Each functional module of the present utility model all can realize by FPGA, for MIPI video conversion configurations module, 5-3 also can realize its function with common MCU, also can be by realize respectively the conversion of single MIPI signal with two special MIPI bridging chips for MIPI vision signal converting unit 4.

The utility model is not limited to above-mentioned execution mode; for those skilled in the art, be also considered as the protection range of the utility model patent according to know-why of the present utility model and scheme or some improvement of making, change, retouching, distortion, replacement under enlightenment of the present utility model within.

The content that is not described in detail in this specification, write a Chinese character in simplified form, term belongs to the known prior art of professional and technical personnel in the field.

Claims (8)

1. two LINKLVDS vision signal conversion MIPI video signal devices, is characterized in that: comprising:

The LVDS video reception unit (1) of two LINK, for the LVDS vision signal of the two LINK of receiving demodulation, produces LVDS parallel demodulation data and the LVDS pixel clock of two LINK;

The LVDS video signal decoding unit (2) of two LINK, for described LVDS pixel clock is converted to LVDS video source pixel clock, and according to LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal, LVDS parallel demodulation data to described couple of LINK are carried out video decode, the LVDS video source signal that produces two LINK, described LVDS video source signal comprises LVDS video source data and LVDS video source synchronizing signal;

Rgb video signal converting unit (3), for converting the LVDS video source signal of described couple of LINK to rgb video signal according to LVDS synchronous mode control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit (5), described rgb video signal comprises rgb video source data, rgb video synchronizing signal and rgb video clock;

MIPI vision signal converting unit (4), send MIPI demonstration module (6) to for described rgb video signal being converted to MIPI vision signal when receiving MIPI video to change starting command from video conversion configurations unit (5), described MIPI vision signal shows module (6) for the MIPI of 4LANE type;

Video conversion configurations unit (5), be used for according to the characteristic of the LVDS vision signal of two LINK that will receive, LVDS vision signal decoding parametric is set, and generation LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal send the LVDS video signal decoding unit (2) of described couple of LINK to; LVDS audio video synchronization pattern control parameter is set, produces LVDS synchronous mode control signal and send rgb video signal converting unit (3) to; Read MIPI video conversion configurations parameter MIPI vision signal converting unit (4) is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, from described rgb video signal converting unit (3) receives MIPI video conversion starting signal, send MIPI video conversion starting command and send described MIPI vision signal converting unit (4) to.

2. according to claim 1 pair of LINKLVDS vision signal conversion MIPI video signal device, is characterized in that: the LVDS video reception unit (1) of described couple of LINK comprising:

LVDS video signal interface (1-1), for receiving the LVDS vision signal of two LINK, the LVDS vision signal of described couple of LINK comprises the LVDS vision signal of LINK1 and LINK2, the LVDS vision signal of described LINK1, LINK2 is transmitted respectively strange, the dual pixel data of LVDS video, the LVDS vision signal of described each LINK comprises respectively LVDS receive clock and LVDS data, described LVDS data are transmitted by LVDS data/address bus, described LVDS data/address bus comprises some holding wires, and every holding wire transmits serial code signal; Described MIPI vision signal shows module for the MIPI of 4LANE type;

The LVDS clock signal demodulation module (1-3) of two LINK for: the LVDS receive clock of described each LINK receiving is carried out to demodulation, produces demodulation clock and demodulation enable signal;

The LVDS demodulated data signal module (1-4) of two LINK for: be demodulated to separately respectively LVDS parallel data demodulating data by the demodulation clock of described each LINK and the signal of the LVDS data/address bus of demodulation enable signal to this LINK, described LVDS receive clock is demodulated into described LVDS video source pixel clock simultaneously.

3. according to claim 1 pair of LINKLVDS vision signal conversion MIPI video signal device, is characterized in that: the LVDS video signal decoding unit (2) of described couple of LINK comprising:

LVDS audio video synchronization buffer module (2-1), synchronously reads for the first buffer memory of the LVDS parallel demodulation data to described couple of LINK again;

LVDS video synchronization signal decoder module (2-3), for the LVDS parallel demodulation decoding data to the described couple of LINK synchronously reading according to the LVDS video decode control signal receiving from described video conversion configurations unit (5), decode the LVDS video source synchronizing signal of two LINK;

The LVDS video data decoding module (2-4) of two LINK, for the LVDS parallel demodulation decoding data to the described couple of LINK synchronously reading according to the LVDS video decode control signal receiving from described video conversion configurations unit (5), decode the LVDS video source data signal of two LINK.

4. according to claim 1 pair of LINKLVDS vision signal conversion MIPI video signal device, is characterized in that: described rgb video signal converting unit (3) comprising:

Rgb video clock generating module (3-1), for generation of rgb video clock;

Rgb video modular converter (3-2), for converting the LVDS video source synchronizing signal of described couple of LINK and LVDS video source data signal to rgb video synchronizing signal and rgb video source data signals with described rgb video clock;

Rgb video clock output adjusting module (3-3), for the phase place of described rgb video clock is adjusted, make its effective edge along can be in the center of rgb video source data, then carry out de-jitter, and described rgb video clock is adjusted into RGB output clock;

Rgb video signal output module (3-4), be used for receiving described RGB output clock, rgb video source data signals and rgb video synchronizing signal, contrast the phase place between effective edge and the described rgb video source data center of described RGB output clock, utilize time delay to do trim process so that effective edge of described RGB output clock and rgb video source data center-aligned, by described rgb video source data signals and the output of rgb video synchronizing signal, in the time having described rgb video source data signals and the output of rgb video synchronizing signal, postpone to produce MIPI video conversion starting signal and send described video conversion configurations unit (5) to.

5. according to claim 1 pair of LINKLVDS vision signal conversion MIPI video signal device, is characterized in that: described MIPI vision signal converting unit (4) comprising:

MIPI register module (4-1), for carry out configuration and the operation of MIPI conversion according to the MIPI register command control MIPI vision signal modular converter (4-2) writing, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;

MIPI vision signal modular converter (4-2), be used for receiving described rgb video signal, carry out configuration and the conversion operations of described rgb video signal conversion MIPI vision signal, in the time receiving the order of MIPI conversion configurations from described MIPI register module (4-1), complete corresponding configuration, conversion operations, when receive MIPI demonstration module initialization command from described MIPI register module (4-1), be transferred to MIPI by MIPI liquid crystal display module connector (4-3) and show module (6), when receive MIPI conversion starting command from described MIPI register module (4-1), start conversion operations,

MIPI liquid crystal display module connector (4-3), for receiving described MIPI vision signal, and shows that with MIPI module (6) is connected, and sends described MIPI vision signal to described MIPI and shows module (6).

6. according to claim 1 pair of LINKLVDS vision signal conversion MIPI video signal device, is characterized in that: described video conversion configurations unit (5) comprising:

Manually toggle switch (5-1), for arranging LVDS vision signal decoding parametric;

Jtag interface (5-2), for receiving MIPI video conversion configurations parameter;

MIPI video conversion configurations module (5-3), for LVDS vision signal decoding parametric is converted to LVDS video decode control signal, read MIPI video conversion configurations parameter described MIPI vision signal converting unit (4) is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, when receiving MIPI video changeover control signal from described rgb video signal converting unit (3), produce MIPI video conversion starting command and send described MIPI vision signal converting unit (4) to.

7. according to claim 2 pair of LINKLVDS vision signal conversion MIPI video signal device, is characterized in that: the LVDS video reception unit (1) of described couple of LINK also comprises:

LVDS video reception termination module (1-2), the LVDS vision signal that is used for the received two LINK operation that is terminated, then send described LVDS receive clock and LVDS data to the LVDS clock signal demodulation module (1-3) of two LINK and the LVDS signal demodulation module (1-4) of two LINK respectively, described terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization with postemphasis, signal buffering and reconstruction, compensation is because of long signal distortion that Distance Transmission causes, decay, reducing transmission disturbs, guarantee received LVDS signal quality,

LVDS demodulation dynamic calibration module (1-5), for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.

8. according to claim 3 pair of LINKLVDS vision signal conversion MIPI video signal device, it is characterized in that: the LVDS video signal decoding unit (2) of described couple of LINK also comprises the LVDS odd even vision signal control module (2-2) of two LINK, while oppositely control for containing odd even pixel when the LVDS vision signal of two LINK of reception, the data of LINK1, LINK2 are exchanged.

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