CN106231227B - Apparatus for transmitting and converting image signal - Google Patents
Apparatus for transmitting and converting image signal Download PDFInfo
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- CN106231227B CN106231227B CN201610639887.8A CN201610639887A CN106231227B CN 106231227 B CN106231227 B CN 106231227B CN 201610639887 A CN201610639887 A CN 201610639887A CN 106231227 B CN106231227 B CN 106231227B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0125—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level one of the standards being a high definition standard
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
The invention discloses a device for transmitting and converting image signals, which is used for providing image signals required by testing for a display module, and comprises: the device comprises a source image signal sending end, a source image signal receiving end and a source image signal converting end, wherein the source image signal sending end is used for receiving a source image signal and converting the source image signal into an optical signal; the image signal conversion end is used for receiving the optical signal and converting the optical signal into an image signal format which can be identified by the display module; and the configuration signal transmission link is used for transmitting the configuration signal issued by the upper computer for the source image signal sending end and the image signal conversion end. The invention can overcome the signal attenuation distortion and asynchronous signal delay caused by various electromagnetic interferences and/or temperature changes, stably and reliably transmit the source image signal in a long distance, or stably and reliably convert the source image signal into an image signal format which can be recognized by the display module.
Description
Technical Field
The invention belongs to the technical field of image signal processing, and particularly relates to a device for transmitting a source image signal and converting the source image signal into an image signal format which can be recognized by a display module.
Background
With the development of display technologies, large-sized display devices with ultra-high definition 4K resolution (3840 × 2160) have become popular, large-sized display devices with very-high definition 8K resolution (7680 × 4320) and 10K resolution (10240 × 4320) are also in mass production, and in order to achieve the ultra-high resolution display performance and ensure the reliability of use, these display device modules mostly adopt new video interface technologies such as V-BY-ONE, DP, and MIPI to receive image signals.
The DP1.3(Display Port 1.3) protocol standard is a DP interface standard specification recently introduced BY VESA organization, and the protocol can support 5K resolution (5120 × 2880), and each data LANE can reach 8.1Gbps data transmission rate, and the V-BY-ONE protocol can support 8K, 10K resolution. The display modules of the novel display interfaces such as V-BY-ONE and DP1.3 are mainly used for detecting BY displaying static images. At present, some large-scale module manufacturers start to produce display modules with V-BY-ONE and DP1.3 interfaces, and in consideration of reducing production cost of a production line and improving market competitiveness of products, the manufacturers of these modules still want to continue to use image signal sources such as LVDS (Low-Voltage Differential Signaling) and TTL (Transistor-Transistor logic) which are abundant on the production line for point-to-screen testing of V-BY-ONE and DP1.3 modules, but these LVDS and TTL image signal sources far cannot satisfy the maximum resolutions of V-BY-ONE and DP1.3, and even a high-specification LVDS/TTL image signal source which can support multiple link transmission modes cannot support the maximum resolutions of V-BY-ONE and DP 1.3. On the other hand, the electrical environment of the display module production line is severe, various serious electromagnetic interferences exist, and different temperature change tests exist, and due to the fact that the grid LVDS/TTL image signal source is far away from the display module to be tested, signal transmission is easily affected by adverse factors such as electromagnetic interference, attenuation distortion, asynchronous signal delay and the like, image test signals can be caused to change, so that various different drawing conditions exist in the point screen test, and the point screen test of the grid LVDS/TTL module can not be normally performed.
Therefore, a signal conversion device capable of converting image signals such as LVDS and TTL into image signals such as LVDS, TTL, DP, MIPI or V-BY-ONE in various complex environments needs to be researched, and the signal conversion device can fully utilize a large number of LVDS/TTL image signal sources existing in a module production line, so that a common LVDS/TTL image signal source can test modules with interface standards such as LVDS, TTL, DP, MIPI or V-BY-ONE through the signal conversion device.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a device for transmitting and converting image signals, which can overcome the defects of signal attenuation distortion and asynchronous signal delay caused by various electromagnetic interference and/or temperature changes, stably and reliably transmit source image signals for a long distance, or stably and reliably convert the source image signals into image signal formats which can be identified by a display module.
In order to achieve the above object, the present invention provides an apparatus for transmitting and converting an image signal for providing an image signal required for a test to a display module, the apparatus comprising:
the device comprises a source image signal sending end, a source image signal receiving end and a source image signal converting end, wherein the source image signal sending end is used for receiving a source image signal and converting the source image signal into an optical signal;
the image signal conversion end is used for receiving the optical signal and converting the optical signal into an image signal format which can be identified by the display module;
and the configuration signal transmission link is used for transmitting the configuration signal issued by the upper computer for the source image signal sending end and the image signal conversion end.
As a further optional technical solution, in the above scheme, the source image signal sending end includes:
the image input protection module is used for receiving the source image signal and eliminating electromagnetic interference and/or surge clutter attached to the source image signal;
the first programmable logic device is used for restoring the source image signal output by the image input protection module into a frame image data packet according to the configuration signal;
and the electro-optical conversion module is used for converting the frame image data packet into an optical signal.
As a further optional technical solution, in the above solution, the configuration signal includes a temperature control signal; the source image signal transmitting end further comprises:
and the first constant temperature control module is used for transmitting the temperature control signal issued by the upper computer to the electro-optical conversion module through the configuration signal transmission link.
As a further optional technical solution, in the above scheme, the configuration signal includes source image signal link data arrangement information and a source image signal transmission protocol; the first programmable logic device is provided with:
the frame image restoration and segmentation unit is used for restoring the source image signal output by the image input protection module into a frame image according to the source image signal link data arrangement information and the source image signal transmission protocol, and segmenting the frame image into frame image data of a plurality of data areas;
and the image lossless compression unit is used for performing lossless compression operation on the frame of image data to generate a compressed file, and performing packet packing operation on the compressed file to generate the frame of image data packet.
As a further optional technical solution, in the above solution, the configuration signal further includes a transmission clock control signal and/or a working power control signal; the first programmable logic device is also provided with:
and the transmission clock monitoring module is used for transmitting the transmission clock control signal and/or the working power supply control signal issued by the upper computer to the first programmable logic device through the configuration signal transmission link.
As a further optional technical solution, in the above solution, the image signal conversion end includes:
the photoelectric conversion module is used for receiving the optical signal and converting the optical signal into a frame image data packet;
and the second programmable logic device is used for sequentially carrying out unpacking operation and decompressing operation on the frame image data packet to restore the frame image data packet into frame image data, and converting the frame image data into an image signal format which can be identified by the display module according to the configuration signal.
As a further optional technical solution, in the above solution, the configuration signal includes a temperature control signal; the image signal conversion terminal further includes:
and the second constant temperature control module is used for transmitting the temperature control signal issued by the upper computer to the photoelectric conversion module through the configuration signal transmission link.
As a further optional technical solution, in the above solution, the configuration signal includes a conversion configuration signal; the second programmable logic device is provided with:
the image decompression unit is used for carrying out unpacking operation on the frame image data packet to restore the frame image data packet into a compressed file and carrying out decompression operation on the compressed file to restore the frame image data packet;
the image signal conversion unit is used for converting the frame image data into an image signal format which can be identified by the display module according to the conversion configuration signal.
As a further optional technical solution, in the above solution, the configuration signal further includes a conversion clock control signal and/or a working power supply control signal; the second programmable logic device is also provided with:
and the conversion clock monitoring module is used for transmitting the conversion clock control signal and/or the working power supply control signal transmitted by the upper computer to the second programmable logic device through the configuration signal transmission link.
As a further optional technical solution, in the above solution, the apparatus further includes a first electromagnetic shielding layer, a second electromagnetic shielding layer, and a third electromagnetic shielding layer, the source image signal transmitting end is disposed in the first electromagnetic shielding layer, the image signal converting end is disposed in the second electromagnetic shielding layer, and the configuration signal transmission link is disposed in the third electromagnetic shielding layer.
The invention has the following advantages:
1) the invention converts the source image signal into the optical signal at the source image signal sending end, and converts the optical signal into the image signal format which can be recognized by the display module at the image signal conversion end, thereby avoiding the interference of electromagnetism and white noise in the transmission process of image data, and further realizing the reliable remote transmission of the source image signal under various complex environments or stably and reliably converting the source image signal into the image signal format which can be recognized by the display module;
2) the invention can stably and reliably convert the source image signal into the image signal format which can be identified by the display module in the complex environment, and carries out real-time clock calibration, working power supply calibration and constant temperature control on the high-speed transmission and conversion processes of the image signal so as to ensure that the data transmission and conversion clock always keeps high precision, thereby ensuring that the transmission and conversion processes of the image signal are carried out without errors and interference.
Drawings
FIG. 1 is a schematic diagram of an embodiment of LVDS LINK data transmission according to the present invention;
FIG. 2 illustrates an embodiment of an error correction encoding operation of the present invention;
FIG. 3 illustrates an embodiment of an interleaving operation of the present invention;
FIG. 4 illustrates an embodiment of the present invention of image packet transmission serialization processing;
fig. 5 shows a method flow for transmitting and converting image signals according to the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
It should be noted that, since the image encoding technologies of the interface standards such as LVDS, TTL, DP, MIPI or V-BY-ONE are all the prior art, the present embodiment only takes the signal transmission and conversion process of converting the LVDS image signal into the DP1.3 image signal as an example for description.
The apparatus for transmitting and converting an image signal disclosed in this embodiment includes an LVDS image signal transmitting terminal for receiving an LVDS image signal and converting the LVDS image signal into an optical signal, a DP1.3 image signal converting terminal for receiving the optical signal and converting the optical signal into a DP1.3 image signal, a single-mode optical fiber for transmitting the optical signal, and a configuration signal transmission cable electrically connecting the LVDS image signal transmitting terminal and the DP1.3 image signal converting terminal.
In the above embodiment, the source image signal sending end includes an image input protection module, a first FPGA chip, an electro-optical conversion module, and a first constant temperature control module. The first FPGA chip is provided with an LVDS image receiving unit, a frame image restoration and segmentation unit, an image lossless compression unit and an error correction coding processing unit; the LVDS image receiving unit comprises an LVDS image clock recovery module and an LVDS LINK (LINK) image data extraction module; the frame image restoration and segmentation unit comprises a frame image restoration and segmentation module and an image data caching and comparing module; the image lossless compression unit comprises a parallel lossless compression module and a compressed data packet packing module; the error correction coding processing unit comprises an image data transmission coding module, a high-precision image transmission clock generating module, a transmission clock monitoring module and an image transmission synchronous serialization module; the electro-optical conversion module comprises an electro-optical conversion sub-module, a DWDM optical multiplexer and a first optical signal amplification sub-module. It should be noted that, in this embodiment, the FPGA chip is only one preferred scheme, and the FPGA chip may also be replaced by programmable logic devices such as APAL, GAL, and CPLD.
In the above embodiment, the image signal conversion terminal includes a photoelectric conversion module, a second FPGA chip, a second constant temperature control module, and a DP1.3 interface protection module. The photoelectric conversion module comprises a second optical signal amplification sub-module, a DWDM optical demultiplexer and a photoelectric conversion sub-module; the second FPGA chip is provided with an image decoding unit, an image decompression unit and a DP1.3 image signal generation unit; the DP1.3 image signal generating unit comprises a DP1.3 image restoration module, an image data storage control module, a high-speed DDR storage module, a DP1.3 data generation module, a DP1.3 image group packet coding module, a DP1.3 transmission clock generation module, a DP1.3 conversion clock monitoring module, a DP1.3 image transmission module and a DP1.3 signal transmission parameter/impedance adjustment module.
In the above embodiment, the configuration signal transmission cable is configured to transmit the configuration signal issued by the upper computer to the source image signal sending end and the image signal conversion end, and transmit the transmission clock state and the operating power state of the first programmable logic device, the temperature state of the electro-optical conversion module, the conversion clock state and the operating power state of the second programmable logic device, and the temperature state of the electro-optical conversion module to the upper computer in real time. The configuration signal includes LVDS link data arrangement information, an LVDS transmission protocol, a DP1.3 conversion configuration signal, an LVDS transmission clock control signal, a DP1.3 conversion clock control signal, a working power control signal of the first programmable logic device, a temperature control signal of the electro-optical conversion module, a working power control signal of the second programmable logic device, and a temperature control signal of the photoelectric conversion module.
The above embodiment is further described in detail with reference to the flow steps shown in fig. 5:
in the above embodiment, since the distance between the position of the LVDS image signal source machine on the display module production line and the position of the DP1.3 module to be tested is relatively long, in order to meet the point screen test of the DP1.3 module, a plurality of sets of LVDS LINK cables need to be used to connect the LVDS image signal source machine and the DP1.3 module, and the connecting cables are not only numerous, but also have long wiring. On the other hand, due to the complex operating environment of the display module production line and the frequent electromagnetic interference, the problems of serious signal interference, asynchronous signal delay and the like of the image signals in the process of transmitting the image signals from the LVDS image signal source machine to the DP1.3 module can be caused. In order to avoid the problems of signal interference and asynchronous transmission delay, the present embodiment will be used as a source image signal sending end and an image signal converting end to be respectively placed in 2 shielding boxes. Before the device starts to implement actions, the shielding box provided with the source image signal transmitting end needs to be close to an LVDS image signal source machine station as much as possible, the shielding box provided with the image signal converting end needs to be close to a DP1.3 module as much as possible, and an electromagnetic shielding layer is additionally arranged on a configuration signal transmission cable for connecting the source image signal transmitting end and the image signal converting end, so that the influence of various interference factors from the input and output connecting ends on the transmission of image data is further reduced.
In the above embodiment, since the maximum DP1.3 resolution is 5120 × 2880, the image data size is very large due to high resolution, and in order to enable the LVDS image signal source machine to output the LVDS image signal normally and reliably, and meanwhile, in order to reduce the problems of transmission synchronization and external interference, the transmission rate of each set of LVDS LINK cables needs to be reduced, in this embodiment, the transmission rate of the LVDS LINK cables is reduced through the following two measures: 1) the method includes the steps that LVDS image signals are transmitted in a multi-LINK mode, for example, LVDS image signals are transmitted in four-LINK and eight-LINK modes, namely, image data are distributed to a plurality of groups of data LINKs to be transmitted, and each group of LINKs is provided with 5 LVDS signal lines for transmitting bits of the image data, as shown in FIG. 1; 2) in this embodiment, the LVDS video signal source machine is configured to reduce the blanking area to 10 bits of data, if it is assumed that the blanking area of each line occupies 100 bits of data under normal display.
In the above embodiment, the image input protection module receives a multi-LINK LVDS image signal and an LVDS transmission clock signal sent by the LVDS image signal source machine, the LVDS image input protection module eliminates electromagnetic interference and a surge clutter attached to the multi-LINK LVDS image signal and the LVDS transmission clock signal, introduces the electromagnetic interference and the surge clutter to the ground through the shielding box, sends the multi-LINK LVDS image signal to the LVDS LINK image data extraction module, and sends the LVDS transmission clock signal to the LVDS image clock recovery module.
In the above embodiment, the LVDS transmission clock signal is subjected to debounce by the PLL phase-locked loop in the LVDS image clock recovery module, then subjected to 7-fold frequency processing according to the LVDS transmission protocol to generate the LVDS image clock signal, and subjected to voltage stabilization processing to generate the pixel clock signal. The LVDS image clock recovery module synchronously samples input multi-LINK LVDS image signals according to the LVDS image clock signals to convert the multi-LINK LVDS image signals into local synchronous circuit signals, samples and extracts bit values of image pixels on each LINK and sends the bit values to the frame image restoration and segmentation module in a local synchronous bus data mode. The frame image restoration and division module restores the input bit data of the image pixels into image pixel signals with 30bit width under the control of the pixel clock signal, restores the image pixel signals with 30bit width into frame images according to LVDS link data arrangement information and an LVDS transmission protocol, and simultaneously, divides the frame images into frame image data of 900 data areas with 30 rows and 30 columns.
In the above embodiment, the image data caching and comparing module respectively caches the frame image data of 900 data regions of two adjacent frame images, respectively compares the frame image data of 900 data regions of one frame image with the frame image data of 900 data regions of the previous frame image to obtain frame image data of data regions where the one frame image and the previous frame image have differences, and sends the frame image data of the data regions where the differences are different to the parallel lossless compression module to perform lossless compression operation, so as to generate a compressed file. For example, when the frame image data of 900 data regions of the 1 st frame image is stored, since there is no previous frame image, all the frame image data of 900 data regions of the 1 st frame image are sent to the parallel lossless compression module to perform lossless compression operation to generate a compressed file; when the frame image data of 900 data areas of the 5 th frame image is stored, comparing the frame image data of 900 data areas of the 5 th frame image with the frame image data of 900 data areas of the 4 th frame image respectively to obtain 15 data areas with difference between the 5 th frame image and the 4 th frame image, and sending the frame image data of the 15 data areas with difference into a parallel lossless compression module to perform lossless compression operation to generate a compressed file.
In the above embodiment, the parallel lossless compression module performs parallel lossless compression on the frame image data of the 15 data areas with the difference to generate 15 compressed data files, and then performs overall second lossless compression on the 15 compressed data files to generate 1 second compressed file, that is, the same part in the 15 compressed data files is compressed again, while the data of the different parts of the 15 data areas with the difference is maintained, and the image compression ratio is maximized and the data amount is minimized through two times of lossless compression.
In the above embodiment, the secondary compressed file is buffered and then sent to a compressed data packaging module to perform packaging operation to generate a frame image data packet, and a packet header is added before the compressed data, where the packet header includes: the data packing method comprises a packet starting identification code (to indicate the start of each data packet), a packet type (data indicating the nature of the packet data, such as a compressed data indicating a 1 st frame complete image, b compressed data indicating difference of certain image areas in a subsequent frame, c compressed data indicating completely different image areas in the subsequent frame, d compressed data indicating completely same image of a current frame and a previous frame in the subsequent frame), a packet sequence number (a few packets currently), an image area number in the packet data (indicating which image areas are compressed into the packet data with difference), a packet data length and a packet header check word, wherein each packet is further provided with a data check word and a packet ending identification code after the compressed data, and after the packet packing operation is completed, a compressed data packing module converts the frame image data packet into a data packet with 128bit width. It should be noted that, if the image data caching and comparing module finds that the current frame is completely the same as the previous frame through comparison, the image data parallel lossless compression module is notified not to perform compression operation, and the compressed data packet packing module will only generate a packet header without containing compressed data (the packet header type is filled in d).
In the above embodiment, the image data transmission encoding module receives the frame image data packet and divides the frame image data packet into 16 sub-frame image data packets, wherein each 8 bits of the 15 data region data in the frame image data packet are encoded into a group of sub-frame image data packets, for example, bits 7 to 0 of the 15 data region data in the frame image data packet are the 1 st group, bits 15 to 8 are the 2 nd group, … …, and bits 127 to bit120 are the 16 th group; then, the image data transmission coding module performs error correction coding operation on the 16 groups of sub-frame image data packets simultaneously to generate 16 groups of error correction sub-frame image data packets corresponding to the 16 groups of sub-frame image data packets one by one. As shown in fig. 2, in this embodiment, the bit width of the 15 data area data in the 16 sets of error correction subframe image data packets is 16 bits, and the bit width of the error correction coding part and the frame image data packet part of the 15 data area data in each set of error correction subframe image data packets is 8 bits, where the lower 8 bits are the frame image data packet part and the higher 8 bits are the error correction coding part.
In the above embodiment, the image data transmission encoding module is further configured to perform an interleaving operation on the 16 sets of error correction sub-frame image data packets: the image data transmission coding module is provided with 8 data storage matrixes for interleaving operation, and writes bit0, bit1, … … and bit7 of frame image data packet parts of 15 data area data in a 1 st group of error correction subframe image data packets into a data storage matrix 0, a data storage matrix 1, … … and a 0 th row in a data storage matrix 7 in a one-to-one correspondence manner respectively to form interleaved data D0; writing bit0, bit1, … … and bit7 of a frame image data packet part of 15 data area data in the group 2 error correction sub-frame image data packet into a 1 st row in a data storage matrix 0, a data storage matrix 1, a data storage matrix … … and a data storage matrix 7 in a one-to-one correspondence manner respectively to form interleaved data D1; … …, respectively; writing bit0, bit1, … … and bit7 of a frame image data packet part of 15 data area data in a 16 th group of error correction sub-frame image data packets into a 15 th row in a data storage matrix 0, a data storage matrix 1, a data storage matrix … … and a data storage matrix 7 in a one-to-one correspondence mode respectively to form interleaved data D15; writing bit0, bit1, … … and bit7 of the error correction coding part of the 15 data area data in the 1 st group of error correction sub-frame image data packets into the 16 th row of the data storage matrix 0, the data storage matrix 1, … … and the data storage matrix 7 in a one-to-one correspondence manner respectively to form interleaved data D16; writing bit0, bit1, … … and bit7 of the error correction coding part of the 15 data area data in the group 2 error correction sub-frame image data packet into the 17 th row of the data storage matrix 0, the data storage matrix 1, … … and the data storage matrix 7 in a one-to-one correspondence manner respectively to form interleaved data D17; … …, respectively; respectively writing bit0, bit1, … … and bit7 of the error correction coding part of the 15 data area data in the 16 th group of error correction sub-frame image data packets into the 31 st row in the data storage matrix 0, the data storage matrix 1, … … and the data storage matrix 7 in a one-to-one correspondence manner to form interleaved data D31. As shown in fig. 3, after the data of 16 sets of error-correction sub-frame image data packets are written into the data storage matrix in the above-mentioned manner, the data storage matrix 0, the data storage matrix 1, … …, and the row of the frame image data packet portion and the row of the error-correction coding portion in the data storage matrix 7 are cyclically shifted from top to bottom, for example, the two portions of data in the data storage matrix 1 are shifted from top to bottom by 2 rows, the two portions of data in the data storage matrix 2 are shifted from top to bottom by 4 rows, and so on, the next data storage matrix is shifted by two more rows than the last data storage matrix, when the data storage matrix 7 is reached, the two portions of data are cyclically shifted from top to bottom by 14 rows, when these operations are completed, each row of data is output as 8-way interleaved frame image data packets by the vertical row synchronized with 8 data storage matrices, each row of data is output by the data storage matrix, the image data transmission encoding module writes in the corresponding bit level of the next set of error correction sub-frame image data packets.
In the above embodiment, the image data transmission encoding module further performs scrambling operation on the 8 channels of interleaved frame image data packets respectively to generate 8 channels of scrambling sequence data packets with different scrambling sequences, where 0 and 1 in the 8 channels of scrambling sequence data packets can be uniformly distributed, and EMI noise can be effectively suppressed.
In the above embodiment, the LVDS image clock recovery module sends the pixel clock signal to the high-precision image transmission clock generation module, and the high-precision image transmission clock generation module converts the pixel clock signal into the high-precision transmission clock signal after frequency multiplication and debouncing by the PLL; and the image transmission synchronous serialization module is used for respectively serializing the 8 paths of scrambling code sequence data packets through the high-precision transmission clock signal. As shown in fig. 4, the image transmission synchronization serialization module retransmits the transmission synchronization sequence and the transmission start sequence after transmitting the transmission scrambled data for a period of time.
In the above embodiment, the transmission clock monitoring module monitors the high-precision transmission clock signal of the high-precision image transmission clock generation module and the working current and voltage thereof in real time; when the transmission clock monitoring module monitors that the high-precision transmission clock signal has frequency, phase deviation or large jitter, the transmission clock monitoring module performs reverse fine adjustment control on parameters of the high-precision image transmission clock generation module in time so that the clock signal keeps a high-precision stable state; meanwhile, when the transmission clock monitoring module monitors that the current and the voltage of the high-precision image transmission clock generating module are abnormal (such as current, voltage drop, fluctuation, larger or smaller), the current and voltage supply amount of the high-precision image transmission clock generating module is increased or decreased in a reverse direction immediately.
In the above embodiment, the electro-optical conversion sub-module receives 8 paths of serialized image data, and converts the 8 paths of serialized image data into optical signals respectively by using 8 SFP photonic modules (Small Form-factor plug Small Pluggable optical modules) integrated in the electro-optical conversion sub-module. Then 8 optical signals are sent to a DWDM optical multiplexer (denseWavelength Division Multiplexing) for optical Multiplexing, that is, 8 optical signals are combined in one optical fiber for transmission, each optical signal adopts optical signals with different wavelengths for transmission, then the first optical signal amplification sub-module performs optical amplification processing on the multiplexed signals, and then the amplified optical signals are sent to one end of a single mode optical fiber.
In the foregoing embodiment, the other end of the single-mode optical fiber of the second optical signal amplification sub-module receives the optical signal, and performs optical amplification processing on the optical signal again, then the DWDM optical demultiplexer demultiplexes the amplified optical signal into 8 optical signals, and the optical-to-electrical conversion sub-module receives the 8 optical signals, and converts the 8 optical signals into 8 serial electrical signals by using 8 SFP photonic modules integrated in the optical-to-electrical conversion sub-module.
In the above embodiment, the image decoding unit deserializes the 8 paths of serial electrical signals, removes the transmission start sequence alignment data, and descrambles and deinterleaves to make the 8 paths of serial electrical signals become frame image data packets, and the image decompressing unit removes the header of the frame image data packet, decompresses, and restores the frame image data in the data area of the frame image.
In the above embodiment, the DP1.3 image signal conversion configuration signal includes a DP1.3 timing parameter, the DP1.3 image restoration module reads the frame image data according to the DP1.3 timing parameter to obtain a DP1.3 image timing and a DP1.3 image data, the DP1.3 image timing and the DP1.3 image data are cached in the high-speed DDR memory module by the image data storage control module, the DP1.3 data generation module distributes the DP image timing and the DP image data to a plurality of DP LANE channels according to a DP1.3 protocol, the DP1.3 image packetizing and encoding module packetizes and scrambles the DP1.3 image data, and sends the DP1.3 image data to the DP1.3 image transmission module to convert the DP1.3 image data into a LANE signal of DP 1.3; the DP1.3 transmission clock generating module generates a high-precision 100Mhz precision clock according to the DP1.3 time sequence parameters, and generates a more precise DP1.3 transmission clock of 8.1GHz after frequency multiplication and jitter removal processing; then the DP1.3 image transmission module serializes the multiple paths of DP1.3LANE signals according to a DP1.3 transmission clock to obtain multiple LANE DP1.3 image signals (serial DP1.38.1Gbps signals) which are in one-to-one correspondence with the multiple paths of DP1.3LANE signals, and the DP1.3 signal transmission parameter/impedance adjustment module adjusts the impedance, pre-emphasis and driving current of the multiple LANE DP1.3 image signals; the DP1.3 interface protection module protects the output multi-LANE DP1.3 image signals, and avoids the influence of external interference pair and instantaneous discharge on each internal device.
In the above embodiment, the DP1.3 switching clock monitoring module performs real-time monitoring and calibration on the reference clock of the DP1.3 transmission clock generating module, and the working current and voltage thereof.
In the above embodiment, the first constant temperature control module is responsible for monitoring the temperatures of the first FPGA chip and the electro-optical conversion module, and uploading the temperature information of the first FPGA chip and the electro-optical conversion module to the upper computer in real time through the configuration signal transmission cable, once the temperature of the first FPGA chip or the electro-optical conversion module exceeds 26 ℃, the upper computer sends a cooling command to the source image signal sending terminal through the configuration signal transmission cable, and the source image signal sending terminal adopts measures such as cooling and a fan to cool, so as to ensure that each device is not influenced by too high temperature.
In the above embodiment, the second constant temperature control module is responsible for monitoring the temperatures of the second FPGA chip and the photoelectric conversion module, and uploading the temperature information of the second FPGA chip and the photoelectric conversion module to the host computer in real time through the configuration signal transmission cable, once the temperature of the second FPGA chip or the photoelectric conversion module exceeds 26 ℃, the host computer will send a cooling command to the image signal conversion terminal through the configuration signal transmission cable, and then the image signal conversion terminal is cooled by adopting measures such as cooling and a fan, so as to ensure that each device is not influenced by the too high temperature.
It will be readily understood by those skilled in the art that the details of the present invention which have not been described in detail herein are not to be interpreted as limiting the scope of the invention, but as merely illustrative of the presently preferred embodiments of the invention.
Claims (9)
1. An apparatus for transmitting and converting an image signal for providing a display module with an image signal required for a test, the apparatus comprising:
the device comprises a source image signal sending end, a source image signal receiving end and a source image signal converting end, wherein the source image signal sending end is used for receiving a source image signal and converting the source image signal into an optical signal;
the image signal conversion end is used for receiving the optical signal and converting the optical signal into an image signal format which can be identified by the display module;
a configuration signal transmission link for transmitting a configuration signal issued by an upper computer for the source image signal transmitting end and the image signal converting end;
the source image signal transmitting end comprises:
the image input protection module is used for receiving the source image signal and eliminating electromagnetic interference and/or surge clutter attached to the source image signal;
the first programmable logic device is used for restoring the source image signal output by the image input protection module into a frame image data packet according to the configuration signal; dividing the frame image data packet into a plurality of groups of sub-frame image data packets; simultaneously carrying out error correction coding operation on each group of the subframe image data packets to generate a plurality of groups of error correction subframe image data packets which are in one-to-one correspondence with the plurality of groups of subframe image data packets; each group of error correction subframe image data packets comprises a frame image data packet part and an error correction coding part, and the bit width of the frame image data packet part is the same as that of the error correction coding part;
and the electro-optical conversion module is used for converting the plurality of groups of error correction subframe image data packets into optical signals.
2. The apparatus for transmitting and converting an image signal according to claim 1, wherein the configuration signal includes a temperature control signal; the source image signal transmitting end further comprises:
and the first constant temperature control module is used for transmitting the temperature control signal issued by the upper computer to the electro-optical conversion module through the configuration signal transmission link.
3. The apparatus for transmitting and converting an image signal according to claim 1, wherein the configuration signal includes source image signal link data arrangement information and a source image signal transmission protocol; the first programmable logic device is provided with:
the frame image restoration and segmentation unit is used for restoring the source image signal output by the image input protection module into a frame image according to the source image signal link data arrangement information and the source image signal transmission protocol, and segmenting the frame image into frame image data of a plurality of data areas;
and the image lossless compression unit is used for performing lossless compression operation on the frame of image data to generate a compressed file, and performing packet packing operation on the compressed file to generate the frame of image data packet.
4. The apparatus for transmitting and converting an image signal according to claim 3, wherein the configuration signal further comprises a transmission clock control signal and/or an operating power control signal; the first programmable logic device is also provided with:
and the transmission clock monitoring module is used for transmitting the transmission clock control signal and/or the working power supply control signal issued by the upper computer to the first programmable logic device through the configuration signal transmission link.
5. The apparatus for transmitting and converting an image signal according to claim 1, wherein the image signal converting terminal comprises:
the photoelectric conversion module is used for receiving the optical signal and converting the optical signal into a frame image data packet;
and the second programmable logic device is used for sequentially carrying out unpacking operation and decompressing operation on the frame image data packet to restore the frame image data packet into frame image data, and converting the frame image data into an image signal format which can be identified by the display module according to the configuration signal.
6. The apparatus for transmitting and converting an image signal according to claim 5, wherein the configuration signal includes a temperature control signal; the image signal conversion terminal further includes:
and the second constant temperature control module is used for transmitting the temperature control signal issued by the upper computer to the photoelectric conversion module through the configuration signal transmission link.
7. The apparatus for transmitting and converting an image signal according to claim 5, wherein the configuration signal includes a conversion configuration signal; the second programmable logic device is provided with:
the image decompression unit is used for carrying out unpacking operation on the frame image data packet to restore the frame image data packet into a compressed file and carrying out decompression operation on the compressed file to restore the frame image data packet;
the image signal conversion unit is used for converting the frame image data into an image signal format which can be identified by the display module according to the conversion configuration signal.
8. The apparatus for transmitting and converting an image signal according to claim 7, wherein the configuration signal further includes a conversion clock control signal and/or an operating power control signal; the second programmable logic device is also provided with:
and the conversion clock monitoring module is used for transmitting the conversion clock control signal and/or the working power supply control signal transmitted by the upper computer to the second programmable logic device through the configuration signal transmission link.
9. The apparatus for transmitting and converting image signals according to any of claims 1 to 8, further comprising a first electromagnetic shielding layer in which the source image signal transmitting terminal is disposed, a second electromagnetic shielding layer in which the image signal converting terminal is disposed, and a third electromagnetic shielding layer in which the configuration signal transmission link is disposed.
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| CN107071568B (en) * | 2017-04-10 | 2019-12-17 | 青岛海信电器股份有限公司 | transmitter and state control method |
| CN108769564B (en) * | 2018-06-25 | 2020-05-22 | 河南思维轨道交通技术研究院有限公司 | Image acquisition system and image data processing method |
| CN109194889B (en) * | 2018-08-16 | 2020-11-20 | 长芯盛（武汉）科技有限公司 | Low-speed signal conversion module for DP interface |
| CN109525826B (en) * | 2018-11-30 | 2021-09-03 | 武汉精立电子技术有限公司 | Long-distance distributed pattern signal generator based on optical fibers |
| CN109901907B (en) * | 2019-03-15 | 2022-05-20 | 北京星网锐捷网络技术有限公司 | Method and server for transmitting virtual desktop |
| CN111428560B (en) * | 2020-02-20 | 2023-09-12 | 重庆创通联达智能技术有限公司 | Video image processing method, device, electronic equipment and storage medium |
| CN112601090B (en) * | 2020-11-26 | 2023-04-28 | 苏州华兴源创科技股份有限公司 | Image transmission system and image signal generator |
| CN113573000A (en) * | 2021-07-27 | 2021-10-29 | 武汉帆茂电子科技有限公司 | Displayport HBR3 signal conversion device based on FPGA |
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