CN202772998U - Video verification, output and display system based on FPGA - Google Patents
Video verification, output and display system based on FPGA Download PDFInfo
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- CN202772998U CN202772998U CN 201220301625 CN201220301625U CN202772998U CN 202772998 U CN202772998 U CN 202772998U CN 201220301625 CN201220301625 CN 201220301625 CN 201220301625 U CN201220301625 U CN 201220301625U CN 202772998 U CN202772998 U CN 202772998U
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Abstract
The utility model discloses a video verification, output and display system based on the FPGA and the processing effect of video images can be quickly and intuitively displayed on a display screen with the system adopted. The system at least comprises an FPGA video processing and verification platform, a TTL-LVDS processing board and a liquid crystal display, wherein the FPGA video processing and verification platform is used for receiving the input of composite video signals and outputting field synchronization TTL signals to the TTL-LVDS processing board after signal processing, the TTL-LVDS processing board is used for converting the TTL signals into LVDS signals and transmitting the LVDS signals to the liquid crystal display, and the liquid crystal display is used for displaying the LVDS signals on a screen. The system disclosed by the utility model has the beneficial effect that the effect of video image quality can be seen quickly and intuitively by building a system platform based on an FPGA platform and through signal transmission between hardware so that intuitive image quality evaluation and performance test can be carried out.
Description
Technical field
The utility model relates to television video process chip design verification field, relates in particular to a kind of video verification output display system based on FPGA.
Background technology
In the design of television video process chip and application, checking many times and design are directly to carry out at the eda tool platform, and the vision signal of the general more difficult activity of EDA platform, the requirement that does not reach Video processing based on CPU computer platform speed.
The checking processing procedure of traditional field of video processing much is direct Straight simulation on the workbench of EDA, and the pictorial information file after processing by output at last finally Shows Picture at computer display screen.What this checking thought can not be accomplished quicklook sees video image quality effect, thereby has influence on evaluation and test directly perceived and some performance tests of image quality.
The utility model content
For the problems referred to above, the purpose of this utility model is to provide a kind of video verification output display system based on FPGA, and that can accomplish quicklook shows the treatment effect of its picture at display screen.
For achieving the above object, a kind of video verification output display system based on FPGA described in the utility model comprises that at least FPGA Video processing verification platform, TTL turn LVDS disposable plates and liquid crystal display screen, wherein;
FPGA Video processing verification platform receives the input of composite video signal, and the TTL signal of processing the capable field synchronization of rear output band turns the LVDS disposable plates to TTL;
TTL turns the LVDS disposable plates, the TTL signal is converted to the LVDS signal is transported to liquid crystal display screen;
Liquid crystal display screen carries out screen display with the LVDS signal.
Preferably, comprise at least video sampling unit group, video decoding unit group and image quality converting unit group in the described FPGA Video processing verification platform, wherein;
Video sampling unit group is carried out collection of simulant signal to composite video signal, is digital signal with the analog signal conversion that collects, and sends to video descrambling unit group;
Video descrambling unit group is separated and is decoded and send decoded digital space signal to image quality converting unit group after processing the digital signal that receives;
Image quality converting unit group is carried out color image quality conversion process to the digital space signal that receives, and sends the TTL signal.
Preferably, described video sampling unit group comprises true stream recovery and gain control unit and sampling analog to digital converter at least, wherein;
Direct current recovers and gain control unit, the composite video signal of input is carried out recovery and the signal gain of signal level precision and process, and the vision signal after will processing sends to the sampling analog to digital converter;
The sampling analog to digital converter carries out collection of simulant signal to the vision signal after over recovery and gain process, is digital signal with the analog signal conversion that collects, and sends to video descrambling unit group.
Preferably, described video descrambling unit group comprise at least synchronous detection with valid data extraction unit, digital resampling unit, brightness separates and motion detection unit and colour decoding unit, wherein;
Detect synchronously and the valid data extraction unit, the digital signal that receives is detected and the extraction of valid data synchronously, and the effective synchronous digital signal after will extracting sends to digital resampling unit;
Numeral resampling unit the effective synchronous digital signal that receives is carried out the digital signal resampling, and the digital signal after will sampling sends to brightness separation and motion detection unit;
Brightness separation and motion detection unit the digital signal behind the resampling is carried out brightness separation and kinetic characteristic Check processing, and the digital signal after will processing send to the colour decoding unit;
The colour decoding unit carries out colour decoding to the digital signal after the processing that receives, and digital signal sends to the image quality conversion group after will decoding.
Preferably, described image quality converting unit group comprises interlacing unit and yuv space at least to the color conversion cell of rgb space, wherein,
Go to the interlacing unit, go interlacing to process to the decoded digital signal that receives, and the digital signal after will processing sends to yuv space to the color conversion cell of rgb space;
Yuv space is to the color conversion cell of rgb space, and the digital signal after interlacing is processed of going that receives is carried out color conversion, and the TTL signal is issued to TTL turns the LVDS disposable plates.
Preferably, described LVDS signal is odd even two-way signal.
Preferably, described TTL signal is odd even two-way signal.
Preferably, described TTL turns and adopts in the LVDS disposable plates TTL signal of DS90C385 model to turn the LVDS signal chip.
Preferably, described composite video signal is the vision signal with synchronizing information.
Preferably, strange, the even signal output part of described FPGA Video processing verification platform connects with the corresponding pin data that TTL turns on the LVDS disposable plates respectively.
The beneficial effects of the utility model are:
The utility model is by building system platform based on the FPGA platform, by the transmission of the signal between the hardware, quicklook see video image quality effect, thereby carry out evaluation and test directly perceived and some performance tests of image quality.
Description of drawings
Fig. 1 is the structure master map of the described video verification output display system based on FPGA of the utility model embodiment;
Fig. 2 is the process chart of the described FPGA Video processing of the utility model embodiment verification platform;
Fig. 3 is the strange pixel output port of the described FPGA of the utility model embodiment design principle figure;
Fig. 4 is the described FPGA dual pixel of the utility model embodiment output port design principle figure.
Embodiment
Below in conjunction with Figure of description the utility model is further described.
As shown in Figure 1, the described a kind of video verification output display system based on FPGA of the utility model embodiment comprises that at least FPGA Video processing verification platform, TTL turn LVDS disposable plates and liquid crystal display screen, wherein;
FPGA Video processing verification platform receives the input of composite video signal, and the TTL signal of processing the capable field synchronization of rear output band turns the LVDS disposable plates to TTL;
TTL turns the LVDS disposable plates, the TTL signal is converted to the LVDS signal is transported to liquid crystal display screen;
Liquid crystal display screen carries out screen display with the LVDS signal.
The design principle of the present embodiment is in detail:
1, the design of FPGA Video processing verification platform
The FPGA platform is by decoding that outside composite video signal is sampled, after carrying out the processing of various image quality simultaneously, finally need realization to show to export and see subjective effect, because the output of signal generally is Transistor-Transistor Logic level among the general FPGA, simultaneously general liquid crystal display screen is the input of supporting TTL, so the design of the present embodiment FPGA plate also needs to design capable field synchronization when being output as ttl, data effectively reach the clock output signal, use in order to turn the LVDS module for the ttl of next link.
The importance of row field synchronization design: image will be realized normal demonstration, needs so the synchronous of line direction, namely needs up-downgoing to align, and can not leak black surround at the right and left.Also want synchronously at field direction, namely need image not leak black surround on both sides up and down, only have and realized capable field synchronization, can allow image on display screen, show between two parties, twisting and shaking phenomenon do not occur.The image input source is all with synchronizing information, signal is separated row field and DE data useful signal by synchronizing separator circuit in the FPGA, then the synchronizing signal of image is reproduced, so just can realize the up and down adjusting of picture position, also will keep simultaneously the stable of image.
In order to finish a platform that can be used for the complete machine checking, need to be on the basis of FPGA platform the signal of the lvds of the ttl signal two-way of a 24bit of supporting design, so that the output signal of FPGA platform is through conversion, be converted to the lvds signal of two-way from the ttl signal, thereby satisfy the requirement that liquid crystal display screen drives.Owing to will support the demonstration of high cls, one-channel signal can't satisfy bandwidth demand, so the output of signal will be divided into two groups, the strange pixel of one group of signal display up direction shows, the dual pixel of one group of signal display up direction shows, equal the transmission of two-way signal, the frequency with one-channel signal transmission implementation has been reduced by one times, so the design of odd even pixel can be satisfied the signal transmission demand of 1080p high bandwidth.
At first need the pin output signal of FPGA is done the definition of TTL signal:
The strange pixel output port of the image ttl Definition of design part of FPGA:
FPGA output port #J10.64 is defined as the clk clock signal of ttl signal: TTL_clk_out_odd
FPGA output port #J10.68 is defined as the de data useful signal of ttl signal: TTL_de_out_odd
FPGA output port #J10.70 is defined as the VS field sync signal of ttl signal: TTL_vs_out_odd
FPGA output port #J10.72 is defined as the HS line synchronizing signal of ttl signal: TTL_hs_out_odd
FPGA output port #J10.74 is defined as blue signal: the TTL_b_out_odd[7 of B7 of ttl signal]
FPGA output port #J10.76 is defined as blue signal: the TTL_b_out_odd[6 of B6 of ttl signal]
FPGA output port #J10.78 is defined as blue signal: the TTL_b_out_odd[5 of B5 of ttl signal]
FPGA output port #J10.80 is defined as blue signal: the TTL_b_out_odd[4 of B4 of ttl signal]
FPGA output port #J10.82 is defined as blue signal: the TTL_b_out_odd[3 of B3 of ttl signal]
FPGA output port #J10.84 is defined as blue signal: the TTL_b_out_odd[2 of B2 of ttl signal]
FPGA output port #J10.86 is defined as blue signal: the TTL_b_out_odd[1 of B1 of ttl signal]
FPGA output port #J10.88 is defined as blue signal: the TTL_b_out_odd[0 of B0 of ttl signal]
FPGA output port #J10.90 is defined as the green signal of G7 of ttl signal: TTL_g_out_odd[7]
FPGA output port #J10.92 is defined as the green signal of G6 of ttl signal: TTL_g_out_odd[6]
FPGA output port #J10.94 is defined as the green signal of G5 of ttl signal: TTL_g_out_odd[5]
FPGA output port #J10.96 is defined as the green signal of G4 of ttl signal: TTL_g_out_odd[4]
FPGA output port #J10.98 is defined as the green signal of G3 of ttl signal: TTL_g_out_odd[3]
FPGA output port #J10.100 is defined as the green signal of G2 of ttl signal: TTL_g_out_odd[2]
FPGA output port #J10.102 is defined as the green signal of G1 of ttl signal: TTL_g_out_odd[1]
FPGA output port #J10.104 is defined as the green signal of G0 of ttl signal: TTL_g_out_odd[0]
FPGA output port #J10.106 is defined as the green signal of R7 of ttl signal: TTL_r_out_odd[7]
FPGA output port #J10.108 is defined as the green signal of R6 of ttl signal: TTL_r_out_odd[6]
FPGA output port #J10.110 is defined as the green signal of R5 of ttl signal: TTL_r_out_odd[5]
FPGA output port #J10.112 is defined as the green signal of R4 of ttl signal: TTL_r_out_odd[4]
FPGA output port #J10.114 is defined as the green signal of R3 of ttl signal: TTL_r_out_odd[3]
FPGA output port #J10.116 is defined as the green signal of R2 of ttl signal: TTL_r_out_odd[2]
FPGA output port #J10.118 is defined as the green signal of R1 of ttl signal: TTL_r_out_odd[1]
FPGA output port #J10.120 is defined as the green signal of R0 of ttl signal: TTL_r_out_odd[0]
The image ttl dual pixel output port Definition of design part of FPGA:
FPGA output port #J10.04 is defined as the clk clock signal of ttl signal: TTL_clk_out_even
FPGA output port #J10.08 is defined as the de data useful signal of ttl signal: TTL_de_out_even
FPGA output port #J10.10 is defined as the VS field sync signal of ttl signal: TTL_vs_out_even
FPGA output port #J10.12 is defined as the HS line synchronizing signal of ttl signal: TTL_hs_out_even
FPGA output port #J10.14 is defined as blue signal: the TTL_b_out_even[7 of B7 of ttl signal]
FPGA output port #J10.16 is defined as blue signal: the TTL_b_out_even[6 of B6 of ttl signal]
FPGA output port #J10.18 is defined as the blue signal of B5 of ttl signal: TTL_b_out even[5
FPGA output port #J10.20 is defined as blue signal: the TTL_b_out_even[4 of B4 of ttl signal]
FPGA output port #J10.22 is defined as blue signal: the TTL_b_out_even[3 of B3 of ttl signal]
FPGA output port #J10.24 is defined as blue signal: the TTL_b_out_even[2 of B2 of ttl signal]
FPGA output port #J10.26 is defined as the blue signal of B1 of ttl signal: TTL_b_out even[1
FPGA output port #J10.28 is defined as the blue signal of B0 of ttl signal: TTL_b out_even[0]
FPGA output port #J10.30 is defined as blue signal: the TTL_g_out_even[7 of G7 of ttl signal]
FPGA output port #J10.32 is defined as blue signal: the TTL_g_out_even[6 of G6 of ttl signal]
FPGA output port #J10.34 is defined as blue signal: the TTL_g_out_even[5 of G5 of ttl signal]
FPGA output port #J10.36 is defined as blue signal: the TTL_g_out_even[4 of G4 of ttl signal]
FPGA output port #J10.38 is defined as blue signal: the TTL_g_out_even[3 of G3 of ttl signal]
FPGA output port #J10.40 is defined as blue signal: the TTL_g_out_even[2 of G2 of ttl signal]
FPGA output port #J10.42 is defined as blue signal: the TTL_g_out_even[1 of G1 of ttl signal]
FPGA output port #J10.44 is defined as blue signal: the TTL_g_out_even[0 of G0 of ttl signal]
FPGA output port #J10.46 is defined as blue signal: the TTL_r_out_even[7 of R7 of ttl signal]
FPGA output port #J10.48 is defined as blue signal: the TTL_r_out_even[6 of R6 of ttl signal]
FPGA output port #J10.50 is defined as blue signal: the TTL_r_out_even[5 of R5 of ttl signal]
FPGA output port #J10.52 is defined as blue signal: the TTL_r_out_even[4 of R4 of ttl signal]
FPGA output port #J10.54 is defined as blue signal: the TTL_r_out_even[3 of R3 of ttl signal]
FPGA output port #J10.56 is defined as blue signal: the TTL_r_out_even[2 of R2 of ttl signal]
FPGA output port #J10.58 is defined as blue signal: the TTL_r_out_even[1 of R1 of ttl signal]
FPGA output port #J10.60 is defined as blue signal: the TTL_r_out_even[0 of R0 of ttl signal]
Wherein, the two-way parity signal of output is respectively the rgb signal of 8bit, line synchronizing signal, field sync signal, clock signal, data useful signal.
Be illustrated in figure 2 as the flow chart of FPGA platform processes signal.In the figure, Y is luminance signal, and C is carrier chrominance signal.At least comprise video sampling unit group, video decoding unit group and image quality converting unit group in the described FPGA Video processing verification platform, wherein;
Described video sampling unit group comprises true stream recovery and gain control unit and sampling analog to digital converter at least, wherein;
Direct current recovers and gain control unit, the composite video signal of input is carried out recovery and the signal gain of signal level precision and process, and the vision signal after will processing sends to the sampling analog to digital converter;
The sampling analog to digital converter carries out collection of simulant signal to the vision signal after over recovery and gain process, is digital signal with the analog signal conversion that collects, and sends to video descrambling unit group.
Described video descrambling unit group comprise at least synchronous detection with valid data extraction unit, digital resampling unit, brightness separates and motion detection unit and colour decoding unit, wherein;
Detect synchronously and the valid data extraction unit, the digital signal that receives is detected and the extraction of valid data synchronously, and the effective synchronous digital signal after will extracting sends to digital resampling unit;
Numeral resampling unit the effective synchronous digital signal that receives is carried out the digital signal resampling, and the digital signal after will sampling sends to brightness separation and motion detection unit;
Brightness separation and motion detection unit the digital signal behind the resampling is carried out brightness separation and kinetic characteristic Check processing, and the digital signal after will processing send to the colour decoding unit;
The colour decoding unit carries out colour decoding to the digital signal after the processing that receives, and digital signal sends to the image quality conversion group after will decoding.
Described image quality converting unit group comprises interlacing unit and yuv space at least to the color conversion cell of rgb space, wherein,
Go to the interlacing unit, go interlacing to process to the decoded digital signal that receives, and the digital signal after will processing sends to yuv space to the color conversion cell of rgb space;
Yuv space is to the color conversion cell of rgb space, and the digital signal after interlacing is processed of going that receives is carried out color conversion, and the TTL signal is issued to TTL turns the LVDS disposable plates.Wherein, the TTL signal is the rgb signal after the color conversion.
2, TTL turns the design of LVDS disposable plates
FPGA mainboard output two-way TTL signal, the TTL signal is input to TTL and turns the LVDS plate, turns the LVDS plate by TTL and carries out TTL to the conversion of LVDS.The compatible output of single and double line LVDS in this design, two-way can be supported the demonstration of full hd liquid crystal display screen, has used U4, the TTL of U5 turns the LVDS circuit module.U4 wherein, U5 is the mark agreement according to LVDS, and the ttl signal of input is converted to the effective LVDS signal of embedded row field screen and data and data.Adopt the TTL signal of (state half) National Semiconductor Corporation to turn LVDS signal chip DS90C385, realize that ttl turns the protocol conversion of lvds signal, final lvds exports to liquid crystal display screen and shows.
Be depicted as the strange pixel output port of FPGA design principle figure such as embodiment accompanying drawing 3.
The ttl signal of FPGA outputting standard, wherein the corresponding relation of FPGA port numbers and ttl signal shows hereinbefore, and the ttl signal of fpga output turns the LVDS plate through TTL, just can change output lvds signal.
Wherein the strange pixel output port of FPGA corresponds to the corresponding relation that TTL turns the input pin of LVDS plate U4
TTL_clk_out_odd outputs to CLOCKIN
TTL_de_out_odd outputs to DATAEN
TTL_vs_out_odd outputs to VS
TTL_hs_out_odd outputs to HS
TTL_b_out_odd[7] output to BLU7
TTL_b_out_odd[6] output to BLU6
TTL_b_out_odd[5] output to BLU5
TTL_b_out_odd[4] output to BLU4
TTL_b_out_odd[3] output to BLU3
TTL_b_out_odd[2] output to BLU2
TTL_b_out_odd[1] output to BLU1
TTL_b_out_odd[0] output to BLU0
TTL_g_out_odd[7] output to GRE7
TTL_g_out_odd[6] output to GRE6
TTL_g_out_odd[5] output to GRE5
TTL_g_out_odd[4] output to GRE4
TTL_g_out_odd[3] output to GRE3
TTL_g_out_odd[2] output to GRE2
TTL_g_out_odd[1] output to GRE1
TTL_g_out_odd[0] output to GRE0
TTL_r_out_odd[7] output to RED7
TTL_r_out_odd[6] output to RED6
TTL_r_out_odd[5] output to RED5
TTL_r_out_odd[4] output to RED4
TTL_r_out_odd[3] output to RED3
TTL_r_out_odd[2] output to RED2
TTL_r_out_odd[1] output to RED1
TTL_r_out_odd[0] output to RED0
U4 realizes that ttl turns the conversion of lvds, and TTL turns LVDS plate U4 output difference sub-signal, and the U4 differential signal outputs to and corresponds to screen socket U2, and wherein the corresponding relation of U2 pin and U4 pin definitions is as follows:
Pin48 lvds exports TXOUT0N
Pin47 lvds exports TXOUT0P
Pin46 1vds exports TXOUT1N
Pin45 lvds exports TXOUT1P
Pin42 lvds exports TXOUT2N
Pin41 lvds exports TXOUT2P
Pin40 lvds exports TXCLKN
Pin39 lvds exports TXCLKP
Pin38 lvds exports TXOUT3N
Pin37 lvds exports TXOUT3P
Be depicted as FPGA dual pixel output port design principle figure such as embodiment accompanying drawing 4.
In the drawings as can be known, the pin corresponding relation is with the connection corresponding relation of strange pixel output port.
The utility model is by building system platform based on the FPGA platform, by the transmission of the signal between the hardware, quicklook see video image quality effect, thereby carry out evaluation and test directly perceived and some performance tests of image quality.
Above; it only is preferred embodiment of the present utility model; but protection range of the present utility model is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement all should be encompassed within the protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range that claim was defined.
Claims (10)
1. the video verification output display system based on FPGA is characterized in that, comprises that at least FPGA Video processing verification platform, TTL turn LVDS disposable plates and liquid crystal display screen, wherein;
FPGA Video processing verification platform receives the input of composite video signal, and the TTL signal of processing the capable field synchronization of rear output band turns the LVDS disposable plates to TTL;
TTL turns the LVDS disposable plates, the TTL signal is converted to the LVDS signal is transported to liquid crystal display screen;
Liquid crystal display screen carries out screen display with the LVDS signal.
2. the video verification output display system based on FPGA according to claim 1 is characterized in that, comprises at least video sampling unit group, video decoding unit group and image quality converting unit group in the described FPGA Video processing verification platform, wherein;
Video sampling unit group is carried out collection of simulant signal to composite video signal, is digital signal with the analog signal conversion that collects, and sends to video descrambling unit group;
Video descrambling unit group is separated and is decoded and send decoded digital space signal to image quality converting unit group after processing the digital signal that receives;
Image quality converting unit group is carried out color image quality conversion process to the digital space signal that receives, and sends the TTL signal.
3. the video verification output display system based on FPGA according to claim 2 is characterized in that, described video sampling unit group comprises true stream recovery and gain control unit and sampling analog to digital converter at least, wherein;
Direct current recovers and gain control unit, the composite video signal of input is carried out recovery and the signal gain of signal level precision and process, and the vision signal after will processing sends to the sampling analog to digital converter;
The sampling analog to digital converter carries out collection of simulant signal to the vision signal after over recovery and gain process, is digital signal with the analog signal conversion that collects, and sends to video descrambling unit group.
4. the video verification output display system based on FPGA according to claim 2, it is characterized in that, described video descrambling unit group comprise at least synchronous detection with valid data extraction unit, digital resampling unit, brightness separates and motion detection unit and colour decoding unit, wherein;
Detect synchronously and the valid data extraction unit, the digital signal that receives is detected and the extraction of valid data synchronously, and the effective synchronous digital signal after will extracting sends to digital resampling unit;
Numeral resampling unit the effective synchronous digital signal that receives is carried out the digital signal resampling, and the digital signal after will sampling sends to brightness separation and motion detection unit;
Brightness separation and motion detection unit the digital signal behind the resampling is carried out brightness separation and kinetic characteristic Check processing, and the digital signal after will processing send to the colour decoding unit;
The colour decoding unit carries out colour decoding to the digital signal after the processing that receives, and digital signal sends to the image quality conversion group after will decoding.
5. the video verification output display system based on FPGA according to claim 2 is characterized in that, described image quality converting unit group comprises interlacing unit and yuv space at least to the color conversion cell of rgb space, wherein,
Go to the interlacing unit, go interlacing to process to the decoded digital signal that receives, and the digital signal after will processing sends to yuv space to the color conversion cell of rgb space;
Yuv space is to the color conversion cell of rgb space, and the digital signal after interlacing is processed of going that receives is carried out color conversion, and the TTL signal is issued to TTL turns the LVDS disposable plates.
6. the video verification output display system based on FPGA according to claim 1 is characterized in that, described LVDS signal is odd even two-way signal.
7. the video verification output display system based on FPGA according to claim 1 is characterized in that, described TTL signal is odd even two-way signal.
8. the video verification output display system based on FPGA according to claim 1 is characterized in that, the TTL signal that described TTL turns employing DS90C385 model in the LVDS disposable plates turns the LVDS signal chip.
9. the video verification output display system based on FPGA according to claim 1 is characterized in that, described composite video signal is the vision signal with synchronizing information.
10. the video verification output display system based on FPGA according to claim 1 is characterized in that, strange, the even signal output part of described FPGA Video processing verification platform connects with the corresponding pin data that TTL turns on the LVDS disposable plates respectively.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105025291A (en) * | 2015-07-30 | 2015-11-04 | 武汉精测电子技术股份有限公司 | Method and device for generating TTL video signal |
| CN105915890A (en) * | 2016-04-27 | 2016-08-31 | 山东大学 | FPGA based SVAC video coding and decoding chip verifying apparatus and method |
| CN106791839A (en) * | 2016-12-19 | 2017-05-31 | 中国航空工业集团公司洛阳电光设备研究所 | It is a kind of to CCIR or EIA standard analog video digitized sampling method and devices |
| CN107564460A (en) * | 2017-10-31 | 2018-01-09 | 京东方科技集团股份有限公司 | Display driver circuit and its driving method, display driving system, display device |
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| CN105025291A (en) * | 2015-07-30 | 2015-11-04 | 武汉精测电子技术股份有限公司 | Method and device for generating TTL video signal |
| CN105915890A (en) * | 2016-04-27 | 2016-08-31 | 山东大学 | FPGA based SVAC video coding and decoding chip verifying apparatus and method |
| CN106791839A (en) * | 2016-12-19 | 2017-05-31 | 中国航空工业集团公司洛阳电光设备研究所 | It is a kind of to CCIR or EIA standard analog video digitized sampling method and devices |
| CN106791839B (en) * | 2016-12-19 | 2020-03-27 | 中国航空工业集团公司洛阳电光设备研究所 | Method and device for digitally sampling CCIR (China center IR) or EIA (electronic article Association) standard analog video |
| CN107564460A (en) * | 2017-10-31 | 2018-01-09 | 京东方科技集团股份有限公司 | Display driver circuit and its driving method, display driving system, display device |
| US10650729B2 (en) | 2017-10-31 | 2020-05-12 | Boe Technology Group Co., Ltd. | Display driving circuit and a driving method thereof, a display driving system and a display apparatus |
| CN107564460B (en) * | 2017-10-31 | 2020-07-31 | 京东方科技集团股份有限公司 | Display driving circuit, driving method thereof, display driving system and display device |
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