CN107707829A - A kind of method that multiplex roles intelligence SDI video switching boxs are realized based on FPGA - Google Patents
A kind of method that multiplex roles intelligence SDI video switching boxs are realized based on FPGA Download PDFInfo
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- CN107707829A CN107707829A CN201710894257.XA CN201710894257A CN107707829A CN 107707829 A CN107707829 A CN 107707829A CN 201710894257 A CN201710894257 A CN 201710894257A CN 107707829 A CN107707829 A CN 107707829A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
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- Controls And Circuits For Display Device (AREA)
Abstract
The present invention relates to a kind of method that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, based on FPGA technology, design polytype video input interface, the timing conversion in input video source is completed using bumpless transfer technology to each input interface, Video Quality Metric by various forms is the video for meeting SMPTE standards, and video can be rotated, color adjusts, the operations such as logo superpositions, user can carry out corresponding functional configuration according to rear end display device or collecting device situation to the video switching box in the present invention, adapt to the use of a variety of occasions.
Description
Technical field
The present invention relates to Video Quality Metric technical field, more particularly to one kind realizes multiplex roles intelligence SDI videos based on FPGA
The method of boxcar.
Background technology
Serial Digital Interface interfaces (abbreviation SDI), i.e. digital component serial line interface, at present main application
In monitoring trade and television.Nearly 2 years, the SDI technologies for coming from broadcasting and TV were paid attention in field of video monitoring, and
To extensive application.In numerous uncompressed standards of digital video, SDI is most promising, and its reason is mainly：SDI is used
The distance of high-grade coaxial cable repeaterless transmission reaches 100 meters or so, is farthest in the uncompressed standard of numerous videos, is existing
Field use brings facility.Monitoring system based on SDI, its advantage essentially consist in：1. distortionless reliability, SDI are different from
The such video data of IP systems be compression after in a manner of package in transmission over networks, SDI videos are with uncompressed signal same
Shaft cable transmits, reliable and stable, undistorted；2. the realtime graphic of high definition grade, SDI is produced in video and not had in transmitting procedure
Process through overcompression, packetized and decoding, the delay similar to IP high-definition images will not be produced, be pursued in fact suitable for various
When the occasion that monitors, such as road traffic；3. multiplexing transmission can be done on coax.It can not only transmit and regard on coaxial cable
Frequency signal, can also transmit audio signal, and the video matrix and Audio Matrix can in such simulation system are combined into one, together
When SDI standards also support transmission of control signals on coax, following PTZ control signal can also be passed by coaxial cable
Defeated, without laying controlling cable, power supply is also very likely transmitted by coaxial cable.So really realize that a coaxial cable passes
Defeated multi-signal, save wiring cost；4. possess the signaling security similar with simulation system and systemic openness extension potentiality.
At this stage, it is following 3 standards by SDI points according to the difference of video resolution and frame per second：1. SD-SDI is SD
SDI, mainly for Standard Definition resolution, 25 frame or 30 frames per second, video bandwidth substantially 250Mbps or so after analog-to-digital conversion；
2. HD-SDI is high definition SDI, this standard is 1080P mainly for resolution ratio, and frame per second is 25 or 30, the number after analog-to-digital conversion
It is 1.485Gbps according to amount；3. 3G-SDI is high aloof from politics and material pursuits frame per second SDI, resolution ratio is still 1080P, but frame per second increase to 50 or
60, the data volume after analog-to-digital conversion is 2.97Gbps.
There are DVI, HDMI, VGA, CVBS etc. in the conventional video interface of computer and monitoring field at present, wherein DVI,
HDMI, VGA can be used for transmitting HD video as 1080P@60, but transmission range is typically restricted in 10 meters, CVBS
Transmission range can reach more than 200 meters, but its picture quality is not more than 768*576@25, belong to SD scope.Because SDI exists
Possess the advantage of picture quality and transmission range in terms of image transmitting, can be SDI interfaces by the Video Quality Metric of other interface types
It is used to transmit after video.
During existing design, mainly by the electrical characteristic of the video interfaces such as DVI, HDMI, VGA, CVBS simply
SDI electrical characteristics are converted to, timing conversion are not done to the video of transmission, when input video is unsatisfactory for VESA's mark
During the resolution ratio suddenly change of accurate (VESA) or input video, the output at SDI ends is also changed, and rear end may be caused to show and set
Standby " flower screen " or " blank screen ", the video of SMPTE standards is not met after conversion can not show at all on conventional display device, and
Current SDI Video Quality Metrics pod interface existing on the market is more single, can only often meet that certain single face turns to SDI interfaces
Change, such as DVI turns SDI, CVBS and turns SDI, and versatility is low, limits application scenarios.
The content of the invention
The object of the present invention is to design a kind of method that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, it is based on
FPGA technology, polytype video input interface is designed, input video is completed using bumpless transfer technology to each input interface
The timing conversion in source, the Video Quality Metric by various forms is the video for meeting SMPTE standards, and video can be rotated,
Color adjusts, and the operation such as Logo superpositions, user can be according to rear end display device or collecting device situation to regarding in the present invention
Frequency boxcar carries out corresponding functional configuration, adapts to the use of a variety of occasions.
The present invention is achieved through the following technical solutions：
A kind of method that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, it is characterised in that use following structure
SDI video switching boxs realize：
The structure of the SDI video switching boxs includes：
FPGA, for realizing video signal detection and collection, timing conversion, generation high-speed serial data, interface circuit control
System, receive from DVI, CVBS, USB interface vision signal after, vision signal is entered row format conversion, pass through SDI IP kernels
High Speed Serial signal is generated, the order for coming from main control end is received by serial communication interface, completes Image Reversal, color adjustment
It is superimposed with Logo；
Clock circuit, it is connected with the FPGA, for providing FPGA logical timer and the reference clock of SDI IP kernels；
1 road DVI video input interfaces, it is arranged at FPGA video inputs；
1 road CVBS video input interfaces, it is arranged at FPGA video inputs；
1 road VGA video input interfaces, it is arranged at FPGA video inputs；
3 road SD/HD/3G SDI video output interfaces being independently arranged, the 3 road SD/HD/3G SDI video output interfaces
FPGA video output terminals are independently disposed to, meet SDI standard electricals for FPGA High Speed Serial data signal to be converted to
The signal of characteristic, add balanced and driving；
DDR3 memories, it is connected with the FPGA, for being stored to the video data of three passages；
EPCQ256 memories, it is connected with the FPGA, for being stored to the configuration parameter of the FPGA；
Host interface, it is connected by serial ports transceiving chip with the FPGA.
Further, the 1 road DVI video input interfaces front end is provided with model DVI-I (24+5) video primary input
Connector.
Further, the host interface uses model DB9 interface connector, and host interface is carried out using serial mode
Communication, the transceiving chip model MAX3491 that serial communication uses.
Further, the SD/HD/3G SDI video output interfaces are driven from the video frequency output that chip model is LMH0303
Dynamic device, SD/HD/3G SDI video output interfaces output end set SMA coaxial connectors.
Further, the DVI video input interfaces are used to receive DVI vision signals, and maximum supports the resolution ratio of 1080P@60,
Resolution ratio is inputted in the case of no more than ultimate resolution arbitrarily to be set.
Further, the CVBS video input interfaces are used to receive CVBS vision signals, support NTSC, PAL, SECAM mould
Intend vision signal, can automatic detection signal type.
Further, the VGA video input interfaces are used to receive VGA vision signals, and maximum supports the resolution ratio of 1080P@60,
Resolution ratio is inputted in the case of no more than ultimate resolution arbitrarily to be set.
Further, the FPGA be integrated with serial communication modular, Logo buffer areas module, image inversion control module,
DDR3 write control module, DDR3 read control modules, RAM module, video timing conversion module, reference clock switching control module,
Clock circuit module, SDI core modules, color adjusting module, color-space conversion module, write FIFO control modules, fifo module
With resolution ratio detection module；
The serial communication modular, color adjusting module, color-space conversion module, write FIFO control modules, FIFO moulds
Block, DDR3 write control module, DDR3 read control modules, RAM module, video timing conversion module and SDI core modules and are sequentially connected；
The external DVI video input interfaces of the color adjusting module input, CVBS video input interfaces or VGA videos are defeated
Incoming interface；
The color adjusting module by resolution ratio detection module respectively with writing FIFO control modules, DDR3 writes control module
Connected with DDR3 read control modules；
The DDR3 writes control module and is connected with Image Reversal module；
The video timing conversion module is connected with DDR3 read control modules；
The serial communication modular is connected with image inversion control module, DDR3 read control modules, Logo buffer areas module,
Video timing conversion module and reference clock switching control module connect respectively, and image inversion control module output end connects respectively
Control module and DDR3 read control modules are write to DDR3；
The Logo buffer areas module is connected with DDR3 read control modules；
The reference clock switching control module is connected with hardware clock circuit, and clock circuit output connects with SDI core modules
Connect.
The invention provides a kind of method that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, with prior art
Compare, beneficial effect is：
The present invention is based on FPGA technology, designs polytype video input interface, and seamless turn is used to each input interface
The timing conversion that technology completes input video source is changed, the Video Quality Metric by various forms is the video for meeting SMPTE standards, and
Video can be rotated, color adjustment, the operation such as Logo superpositions, user can be according to rear end display device or collecting device feelings
Condition carries out corresponding functional configuration to the video switching box in the present invention, adapts to the use of a variety of occasions；By applying this hair
It is bright, it can facilitate and the currently a popular class video interface of DVI, CVBS, VGA tri- is uniformly arrived into SDI interfaces so that rear end equipment can be done
It is single, SDI is simple using 75 Europe coaxial cables transmission, long transmission distance, equipment installation so that hardware cost reduces.At this
In invention, intelligent bumpless transfer technology causes arbitrary standards or non-standard video to show solve in conventional SDI displays
Non-standard video can not be show the problem of on conventional display.In some occasions, it is desirable to Image Reversal can be performed, color is adjusted
Function, these functions such as whole, logo superposition are typically completed in rear end equipment, using the present invention rear end equipment can not be made with
Upper functional requirement, further reduce the use cost of rear end equipment.
Brief description of the drawings
Fig. 1 is the structural representation that multiplex roles intelligence SDI video switching boxs are realized based on FPGA that the present invention designs.
Fig. 2 realizes block diagram for fpga logic in the present invention.
In Fig. 1：1 road DVI video input interfaces use TFP401 (DVI)；CVBS video input interfaces use ADV7281
(CVBS)；VGA video input interfaces use AD9984A (VGA)；DDR3 is DDR3 memories；
In Fig. 2：Color is adjusted to color adjusting module；It is color-space conversion module that RGB, which turns YUV422,；Write FIFO controls
To write FIFO control modules；FIFO is fifo module；Resolution ratio is detected as resolution ratio detection module；DDR3 writes control and write for DDR3
Control module；DDR3 is DDR3 modules；Image inversion control is image inversion control module；Logo buffer areas are Logo buffer areas
Module；It is DDR3 read control modules that DDR3, which reads control,；RAM is RAM module；Timing conversion is video timing conversion module；SDI cores
For SDI core modules；Clock circuit is clock circuit module；Reference clock switching control is reference clock switching control module；
FPGA is integrated with serial communication modular, Logo buffer areas module, image inversion control module, DDR3 modules, DDR3
Write control module, DDR3 read control modules, RAM module, video timing conversion module, reference clock switching control module, clock
Circuit module, SDI core modules, color adjusting module, color-space conversion module, write FIFO control modules, fifo module and point
Resolution detection module.
Embodiment
The present invention is described further refering to accompanying drawing 1 and Fig. 2.
The present invention relates to a kind of method that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, it is characterised in that adopts
Realized with the SDI video switching boxs of following structure：
The structure of the SDI video switching boxs includes：
FPGA, for realizing video signal detection and collection, timing conversion, generation high-speed serial data, interface circuit control
System, receive from DVI, CVBS, USB interface vision signal after, vision signal is entered row format conversion, pass through SDI IP kernels
High Speed Serial signal is generated, the order for coming from main control end is received by serial communication interface, completes Image Reversal, color adjustment
It is superimposed with Logo；
Clock circuit, it is connected with the FPGA, for controlling FPGA sequential；
1 road DVI video input interfaces, it is arranged at FPGA video inputs；
1 road CVBS video input interfaces, it is arranged at FPGA video inputs；
1 road VGA video input interfaces, it is arranged at FPGA video inputs；
3 road SD/HD/3G SDI video output interfaces being independently arranged, the 3 road SD/HD/3G SDI video output interfaces
FPGA video output terminals are independently disposed to, meet SDI standard electrical characteristics for FPGA High Speed Serial signal to be converted to
Signal, add balanced and driving；
DDR3 memories, it is connected with the FPGA, for being stored to the logical order that host interface inputs；
EPCQ256 memories, it is connected with the FPGA, for being stored to the configuration parameter of the FPGA；
Host interface, it is connected by serial communication modular with the FPGA.
As an improvement, the video master that the 1 road DVI video input interfaces front end is provided with model DVI-I (24+5) is defeated
Incoming interface.
As an improvement, the host interface uses model DB9 host interface, serial communication modular selects model
MAX3491 serial ports transceiving chip.
As an improvement, the SD/HD/3G SDI video output interfaces are from the video frequency output that chip model is LMH0303
Interface, SD/HD/3G SDI video output interfaces output end set SMA coaxial connectors.
As an improvement, the DVI video input interfaces are used to receive DVI vision signals, maximum supports 1080P@60 to differentiate
Rate, input resolution ratio can arbitrarily be set in the case of no more than ultimate resolution.
As an improvement, the CVBS video input interfaces are used to receive CVBS vision signals, NTSC, PAL, SECAM are supported
Analog video signal, can automatic detection signal type.
As an improvement, the VGA video input interfaces are used to receive VGA vision signals, maximum supports 1080P@60 to differentiate
Rate, input resolution ratio can arbitrarily be set in the case of no more than ultimate resolution.
As an improvement, the FPGA be integrated with serial communication modular, Logo buffer areas module, image inversion control module,
DDR3 modules, DDR3 write control module, DDR3 read control modules, RAM module, video timing conversion module, reference clock switching
Control module, clock circuit module, SDI core modules, color adjusting module, color-space conversion module, write FIFO control modules,
Fifo module and resolution ratio detection module；
The serial communication modular, color adjusting module, color-space conversion module, write FIFO control modules, FIFO moulds
Block, DDR3 write control module, DDR3 modules, DDR3 read control modules, RAM module, video timing conversion module and SDI core modules
It is sequentially connected；
The external DVI video input interfaces of the color adjusting module input, CVBS video input interfaces or VGA videos are defeated
Incoming interface；
The color adjusting module by resolution ratio detection module respectively with writing FIFO control modules, DDR3 writes control module
Connected with DDR3 read control modules；
The DDR3 writes control module and is connected with video timing conversion module；
The video timing conversion module is connected with DDR3 read control modules；
The serial communication modular is connected with image inversion control module, DDR3 read control modules, Logo buffer areas module,
Video timing conversion module and reference clock switching control module connect respectively, and image inversion control module output end connects respectively
Control module and DDR3 read control modules are write to DDR3；
The serial communication modular is connected by Logo buffer areas module with DDR3 read control modules；
Reference clock switching control module, clock circuit module and the SDI core modules are sequentially connected.
Compared with prior art,
The present invention is based on FPGA technology, designs polytype video input interface, and seamless turn is used to each input interface
The timing conversion that technology completes input video source is changed, the Video Quality Metric by various forms is the video for meeting SMPTE standards, and
Video can be rotated, color adjustment, the operation such as Logo superpositions, user can be according to rear end display device or collecting device feelings
Condition carries out corresponding functional configuration to the video switching box in the present invention, adapts to the use of a variety of occasions；
By the application present invention, it can facilitate and uniformly connect the currently a popular class video interface of DVI, CVBS, VGA tri- to SDI
Mouthful so that rear end equipment can be done single, and SDI is installed simply using 75 Europe coaxial cable transmission, long transmission distance, equipment,
So that hardware cost reduces.In the present invention, intelligent bumpless transfer technology make it that arbitrary standards or non-standard video can be normal
Show solve the problems, such as that non-standard video can not be shown on conventional display with SDI displays.In some occasions, it is desirable to
The functions such as Image Reversal, color adjustment, logo superpositions can be performed, these functions are typically completed in rear end equipment, using this hair
It is bright to make function above requirement to rear end equipment, further reduce the use cost of rear end equipment.
In specific implementation, DVI video input interfaces, CVBS video input interfaces and VGA video input interfaces are matched somebody with somebody respectively
Respective video processing unit is equipped with, the corresponding SD/HD/3G SDI video output interface of an input video interface is each
Interface is completely independent processing, when in use may be selected either interface work, can also three interfaces work simultaneously.
Control interface of the serial communication modular as SDI video switching boxs, ordered using RSYUV422 interfaces with main frame
Order and data interaction, main frame can be the PC with serial interface or the microcontroller of MCU classes.Application has main frame intervention at the scene
When, each module of SDI video switching boxs carries out corresponding configuration by main frame, annexation as shown in Figure 2, color can be adjusted,
Image Reversal, Logo superpositions, SDI IP kernel modules are controlled, so as to complete corresponding function.When field application lacks main frame,
SDI video switching boxs can automatic detection input picture form and resolution ratio, the parameter obtained by detection complete video acquisition and
The self-configuration of necessary module needed for conversion, reach the purpose of intelligent work.
Color adjusting module can be configured by serial communication modular, and brightness, contrast and saturation are carried out to input picture
The adjustment of degree, make image visual effect more gorgeous, the module can be also operated under offline mode, i.e., when main frame lacks, now
The working condition of module can be divided into two classes, carried out parameter configuration if last time has to the module during main frame access and enabled master
Machine lacks retention parameter function, then the configuration parameter for continuing to use last time is operated by module；When if last time main frame accesses not
Enabled hosts lack retention parameter function, then module will not carry out any processing to input picture, and view data enters next
Module.
Color-space conversion module is that the RGB shown in Fig. 2 turns YUV422 modules, and the conversion is to reduce input picture number
According to amount, so as to reduce bandwidth requirement of the input picture to subsequent treatment module, SDI video switching boxs are enable to reach three road interfaces same
When the state that works, data volume will be reduced to the 2/3 of former data after the module, and effect is obvious.
Video data is being written into the fifo module of DDR3 front ends after color-space conversion module, while resolution ratio is examined
Survey module and enter row format and resolution ratio detection to video, if under main frame miss status, the video image that the module detects is joined
Number will complete the call parameter of basic function as SDI video switching boxs, and video timing conversion module, SDI IP kernel modules are both needed to
The intelligent conversion of video is realized according to the detection parameters of resolution ratio detection module, if video input be meet VESA and
SMPTE standards, then the direct parameter obtained using detection is completed into conversion in transfer process, if video input is not inconsistent
Close VESA or SMPTE standards, then can intelligently be paired to and meet according to the form and resolution ratio of input video in transfer process
The resolution ratio of VESA and SMPTE standards, the resolution ratio will be closest to input a standard resolution of resolution ratio, so exists
The video of SDI ends output meets SMPTE standards all the time, ensure that rear end is shown and the normal work of collecting device.
Image Reversal control module can be configured by serial communication module, and under some use occasions, display may
Can be laterally disposed, it is also possible to it is vertical to place, input picture is carried out by Image Reversal control module up and down, left and right mirror image or 90 °,
After 270 ° of rotations, image is recovered to conventional visual to show, convenient use people viewing.The module can be operated under offline mode,
When i.e. main frame lacks, now the working condition of Image Reversal control module can be divided into two classes, if when there is a main frame access last time pair
The module has carried out parameter configuration and has enabled main frame missing retention parameter function, then module will continue to use the configuration parameter of last time
It is operated；If last time main frame is not enabled on main frame missing retention parameter function when accessing, then module will not be to input picture
Any processing is carried out, view data enters next module.
Logo laminating modules are arranged between Logo buffer areas module and DDR3 read control modules, can be by serial communication module
Configured, picture carried out to input picture and character adding, picture, the character of superposition are sent to Logo buffer areas by serial ports,
Overlap-add region is optional, and convenient use people adds significant Logo in the image of transmission, is publicized for individual or company,
Image is spliced using the function or insertion is changed.The module can be operated under offline mode, i.e., when main frame lacks, this
When module working condition can be divided into two classes, parameter configuration has been carried out to the module during main frame access and enabled if last time has
Main frame lacks retention parameter function, then the configuration parameter for continuing to use last time is operated by module；If last time main frame accesses
It is not enabled on main frame missing retention parameter function, then module will not carry out any processing to input picture, under view data enters
One module.
Video timing conversion module can be configured by serial communication module, and seamless turn of sequential is carried out to input picture
Change, no matter whether front-end image meets SMPTE standards, will be all converted into after the module and meet SMPTE standards.The module
It can be operated under offline mode, i.e., when main frame lacks, now the working condition of module can be divided into two classes, if last time has main frame to connect
It is fashionable that parameter configuration has been carried out to the module and has enabled main frame missing retention parameter function, then module will continue to use matching somebody with somebody for last time
Parameter is put to be operated；If last time main frame is not enabled on main frame missing retention parameter function when accessing, then module will use intelligence
Energy matching function is handled image.
SDI IP kernels module can be configured by serial communication module, and the image after front-end processing is carried out into coding and and gone here and there
View data after conversion, coding and conversion will meet SDI host-host protocols.The module can be operated under offline mode, i.e. main frame
During missing, now the working condition of module can be divided into two classes, if last time has and carried out parameter to the module during main frame access and match somebody with somebody
Put and enable main frame missing retention parameter function, then the configuration parameter for continuing to use last time is operated by module；If last time
Main frame access when be not enabled on main frame missing retention parameter function, then module will use intelligent matching function to image at
Reason.
As described above, you can the present invention is applied.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, technique according to the invention scheme and its
Inventive concept is subject to equivalent substitution or change, should all be included within the scope of the present invention.
Claims (8)
- A kind of 1. method that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, it is characterised in that using following structure SDI video switching boxs are realized：The structure of the SDI video switching boxs includes：FPGA, for realizing that video signal detection controls with collection, timing conversion, generation high-speed serial data, interface circuit, Receive from DVI, CVBS, USB interface vision signal after, vision signal is entered row format conversion, generated by SDI IP kernels High Speed Serial signal, received by serial communication interface and come from the order of main control end, complete Image Reversal, color adjustment and Logo is superimposed；Clock circuit, it is connected with the FPGA, for providing FPGA logical timer and the reference clock of SDI IP kernels；1 road DVI video input interfaces, it is arranged at FPGA video inputs；1 road CVBS video input interfaces, it is arranged at FPGA video inputs；1 road VGA video input interfaces, it is arranged at FPGA video inputs；3 road SD/HD/3G SDI video output interfaces being independently arranged, the 3 road SD/HD/3G SDI video output interfaces are independent FPGA video output terminals are arranged at, meet SDI standard electrical characteristics for FPGA High Speed Serial data signal to be converted to Signal, add balanced and driving；DDR3 memories, it is connected with the FPGA, for being stored to the video data of three passages；EPCQ256 memories, it is connected with the FPGA, for being stored to the configuration parameter of the FPGA；Host interface, it is connected by serial ports transceiving chip with the FPGA.
- 2. the method according to claim 1 that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, its feature are existed In the 1 road DVI video input interfaces front end is provided with model DVI-I (24+5) video primary input connector.
- 3. the method according to claim 1 that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, its feature are existed In the host interface uses model DB9 interface connector, and host interface is communicated using serial mode, and serial ports leads to Believe the transceiving chip model MAX3491 used.
- 4. the method according to claim 1 that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, its feature are existed In the SD/HD/3G SDI video output interfaces are from the video output driver that chip model is LMH0303, SD/HD/3G SDI video output interfaces output end sets SMA coaxial connectors.
- 5. the method according to claim 1 that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, its feature are existed In the DVI video input interfaces are used to receive DVI vision signals, and maximum supports the resolution ratio of 1080P@60, no more than maximum Resolution ratio is inputted in the case of resolution ratio arbitrarily to be set.
- 6. the method according to claim 1 that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, its feature are existed In the CVBS video input interfaces are used to receive CVBS vision signals, support NTSC, PAL, SECAM analog video signal, can Automatic detection signal type.
- 7. the method according to claim 1 that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, its feature are existed In the VGA video input interfaces are used to receive VGA vision signals, and maximum supports the resolution ratio of 1080P@60, no more than maximum Resolution ratio is inputted in the case of resolution ratio arbitrarily to be set.
- 8. the method according to claim 1 that multiplex roles intelligence SDI video switching boxs are realized based on FPGA, its feature are existed In, the FPGA be integrated with serial communication modular, Logo buffer areas module, image inversion control module, DDR3 write control module, DDR3 read control modules, RAM module, video timing conversion module, reference clock switching control module, clock circuit module, SDI Core module, color adjusting module, color-space conversion module, write FIFO control modules, fifo module and resolution ratio detection module；The serial communication modular, color adjusting module, color-space conversion module, write FIFO control modules, fifo module, DDR3 writes control module, DDR3 read control modules, RAM module, video timing conversion module and SDI core modules and is sequentially connected；Color adjusting module input external DVI video input interfaces, CVBS video input interfaces or the VGA video inputs connect Mouthful；The color adjusting module by resolution ratio detection module respectively with writing FIFO control modules, DDR3 writes control module and DDR3 read control modules connect；The DDR3 writes control module and is connected with Image Reversal module；The video timing conversion module is connected with DDR3 read control modules；The serial communication modular is connected with image inversion control module, DDR3 read control modules, Logo buffer areas module, video Timing conversion module and reference clock switching control module are connected respectively, and image inversion control module output end is respectively connecting to DDR3 writes control module and DDR3 read control modules；The Logo buffer areas module is connected with DDR3 read control modules；The reference clock switching control module is connected with hardware clock circuit, and clock circuit output is connected with SDI core modules.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710894257.XA CN107707829B (en) | 2017-09-28 | 2017-09-28 | Multi-interface intelligent SDI video conversion box realized based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710894257.XA CN107707829B (en) | 2017-09-28 | 2017-09-28 | Multi-interface intelligent SDI video conversion box realized based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107707829A true CN107707829A (en) | 2018-02-16 |
| CN107707829B CN107707829B (en) | 2020-04-21 |
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