CN201185457Y - System for monitoring high-resolution video - Google Patents
System for monitoring high-resolution video Download PDFInfo
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- CN201185457Y CN201185457Y CNU2008200113137U CN200820011313U CN201185457Y CN 201185457 Y CN201185457 Y CN 201185457Y CN U2008200113137 U CNU2008200113137 U CN U2008200113137U CN 200820011313 U CN200820011313 U CN 200820011313U CN 201185457 Y CN201185457 Y CN 201185457Y
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Abstract
The utility model discloses a high-definition video monitoring system which has the advantages of simple structure and low cost and can generate, transmit, display, store and play back 720P or 1080P high-definition video data. The output of the image sensor of a camera is connected with a FPGA (1); one output of the FPGA (1) is connected with a lens through an aperture-driving circuit, one output is connected with a RS422 interface, and another output is connected with a photoelectric conversion module (1); the FPGA (1) is provided with a data-receiving circuit, the outputs of which are respectively connected with a color-processing circuit and an image-reconstructing circuit (1); the output of the color-processing circuit is connected with a data encoding and decoding circuit which is connected with a microprocessor; the output of the image-reconstructing circuit (1) is connected with the microprocessor through a lightness-processing circuit; the output of the microprocessor is connected with an I2C interface circuit; the output of the photoelectric conversion module (1) is connected with a matrix through an optic fiber; the matrix is provided with a photoelectric conversion module (2), the output of which is connected with a switching circuit.
Description
Technical field:
The utility model relates to a kind of video monitoring system, and is especially a kind of simple in structure, with low cost, can generate, transmit, show, store the high-resolution video monitoring system of playback 720P or 1080P HD video data.
Background technology:
At present, the range of application of video monitoring system is wider, as fields such as bank, hotel, airport, highway, residential areas.Existing video monitoring system comprises the scene of being positioned at and is installed in video camera on the The Cloud Terrace, video camera is controlled the video signal transmission of being produced by cable to matrix and by the control device (computer, keyboard etc.) that joins with matrix, make vision signal lead up to display driver circuit and show on the display of Surveillance center, another road storage is used for playback; Surveillance center sends control informations such as control The Cloud Terrace, video camera zoom by control device to the scene simultaneously, in the hope of obtaining vision signal the most clearly.Though existing field of broadcast televisions can generate and transmit the high-definition video signal that is respectively 720p, 1080i and three kinds of display formats of 1080p, but device therefor price higher (being import equipment), can not popularize in field of video monitoring and use, to such an extent as to the image sharpness of existing video monitoring system is lower, be difficult to satisfy the requirement of monitoring.In addition, existing video storage device generally adopts DVR, gathers video data by built-in video frequency collection card, is sent to computer through pci bus, can not satisfy the requirement of high definition.
Summary of the invention:
The utility model is in order to solve the existing low problem of video monitoring system definition, to provide a kind of simple in structure, with low cost, can generating, transmit, show, store the high-resolution video monitoring system of playback 720P or 1080P HD video data.
Technical solution of the present utility model is: a kind of high-resolution video monitoring system, the video camera that is arranged on the The Cloud Terrace is arranged, the output and the matrix of video camera join, the output of matrix is joined by display driver circuit and display, be connected to control device and image storage playback reproducer with matrix, it is characterized in that:
A. described video camera has camera lens, is connected to imageing sensor with camera lens, and the output and the FPGA1 of imageing sensor join, and the output of FPGA1 is leaded up to aperture drive circuit and camera lens and joined; One the tunnel joins with the RS422 interface, and another road and photoelectric conversion module 1 join; Described FPGA1 has data receiver circuit, and the output of data receiver circuit is joined with chroma processing circuit, image reconstruction circuit 1 respectively, and the output of chroma processing circuit and data coding-decoding circuit join, and data coding-decoding circuit and microprocessor join; The output of image reconstruction circuit 1 is joined by brightness processed circuit and microprocessor, and the output of microprocessor and I2C interface circuit join;
The output of b. described photoelectric conversion module 1 is joined by optical fiber and matrix, and described matrix is provided with photoelectric conversion module 2, and the output and the commutation circuit of photoelectric conversion module 2 are joined.
Described display driver circuit is provided with FPGA2, is connected to high-res high width video data interface and double digit rate synchronous dynamic random access memory with FPGA2; Described FPGA2 has image reconstruction circuit 2, is connected to the synchronous dynamic random access memory read-write controller with image reconstruction circuit 2; Described FPGA2 is provided with also that display interface drives and clock synchronous circuit, the high width video data of high-res interface configuration circuit, and display interface drives and clock synchronous circuit and synchronous dynamic random access memory read-write controller join.
Be connected to photoelectric conversion module 3 with the output of described commutation circuit, the output of photoelectric conversion module 3 is joined by optical fiber and photoelectric conversion module 4, and the FPGA2 in photoelectric conversion module 4 and the display driver circuit joins.
The output of described photoelectric conversion module 3 is joined by optical fiber and photoelectric conversion module 5, photoelectric conversion module 5 joins with image storage playback reproducer, described image storage playback reproducer is provided with FPGA3, is connected to high-speed RAM with FPGA3, and FPGA3 joins by PCI Express socket and computer; Described FPGA3 has the fpga logic unit, is connected to serial/separate serializer circuit, RAM functional module and PCI Express functional module with the fpga logic unit.
The utility model is by the set field programmable processor of definition, realization is to functions such as video data reception, processing, image reconstruction, video output data coding and decodings, can generate 720P or 1080P HD video data and also can transmit by optical fiber, loss is low, message capacity is big, anti-electromagnetic interference capability is strong, good confidentiality, in light weight; By the set field programmable processor of definition, realize display driver, demonstration and storage playback simultaneously to high sharpness video, simple in structure, with low cost, can be widely used in supervisory control system, satisfy the high definition performance index requirement of supervisory control system.
Description of drawings:
Fig. 1 is that the circuit theory of the utility model embodiment is always schemed.
Fig. 2 is the internal circuit theory diagram of the utility model embodiment video camera.
Fig. 3 is the theory diagram of field programmable processor FPGA1 in the utility model embodiment video camera.
Fig. 4 is the utility model embodiment camera video data output forms.
Fig. 5 is the schematic block circuit diagram that the utility model embodiment matrix is connected with control device.
Fig. 6 is the theory diagram of the utility model embodiment display driver circuit.
The theory diagram of field programmable processor FPGA2 in Fig. 7 the utility model embodiment display driver circuit.
Fig. 8 is the utility model embodiment image storage playback reproducer schematic block circuit diagram.
Fig. 9 is the theory diagram of field programmable processor FPGA3 in the utility model embodiment image storage playback reproducer.
Embodiment:
Below in conjunction with description of drawings embodiment of the present utility model.
Embodiment 1:
As shown in Figure 1: the video camera that is arranged on the The Cloud Terrace is arranged, and the output and the matrix of video camera join, and the output of matrix is joined by display driver circuit and display, are connected to control device and image storage playback reproducer with matrix.Described video camera has camera lens as shown in Figure 2, is connected to the cmos imageing sensor of 5,000,000 pixels with camera lens, and the output and the FPGA1 of cmos imageing sensor join, and the output of FPGA1 is leaded up to aperture drive circuit and camera lens and joined; One the tunnel joins with the RS422 interface, and output is used to control control signals such as The Cloud Terrace, and another road and photoelectric conversion module 1 join; Described FPGA1 is as shown in Figure 3: data receiver circuit is arranged, the output of data receiver circuit is joined with chroma processing circuit, image reconstruction circuit 1 respectively, the dateout and the coding-decoding circuit of chroma processing circuit joins (the video data output form as shown in Figure 4), and data coding-decoding circuit and microprocessor join; The output of image reconstruction circuit 1 is joined by brightness processed circuit and microprocessor, the output of microprocessor and I2C interface circuit join, the output of described photoelectric conversion module 1 is joined by optical fiber and matrix, described matrix is as shown in Figure 5: be provided with photoelectric conversion module 2, the output and the commutation circuit of photoelectric conversion module 2 are joined, and control device and commutation circuit and photoelectric conversion module 2 join.
The course of work:
The cmos imageing sensor of 5,000,000 pixels can be realized the raw image data collection of HD video form, and speed＞25 frame/seconds is with the smoothness that guarantees that picture shows dynamic object.FPGA1 mainly is responsible for the processing and the control of data, issues two-way photoelectric conversion module with handling data later in the mode of serial, and realizes the controlled function of camera lens auto iris and video camera automatic gate or the like by the aperture drive circuit.Simultaneously, the reverse control signal that the photoelectric conversion module receiving matrix is sent is given FPGA1, by the action of RS422 interface control The Cloud Terrace and camera lens.The concrete course of work is as follows: chroma processing circuit is mainly realized the color rectification of data among the FPGA1, to realize the color data of real-world object correspondence, issues two-way photoelectric conversion module 1 by the data coding-decoding circuit in the mode of serial; The data that image reconstruction circuit 1 is original with imageing sensor (Bayer color) revert to the RGB data, are used for brightness processed and cooperate microprocessor to pass through I2C control chart image-position sensor, and the output of microprocessor and RS422 interface join; The output of brightness processed circuit and aperture control circuit join, controls lens auto iris.Photoelectric conversion module 2 in the matrix will become the signal of telecommunication by the signal of Optical Fiber Transmission, give commutation circuit with view data, output after switching; The reverse control signal of control device is then issued video camera by photoelectric conversion module 2, optical fiber.
Embodiment 2:
Other circuit are with embodiment 1, with embodiment 1 different shown in Fig. 6,7: display driver circuit is provided with FPGA2, is connected to the high width video data of high-res interface (HDMI/DVI) and double digit rate synchronous dynamic random access memory (DDR SDRAM) with FPGA2; Described FPGA2 has image reconstruction circuit 2, is connected to the synchronous dynamic random access memory read-write controller with image reconstruction circuit 2; Image reconstruction circuit 2 cooperates the DDR SDRAM memory circuit data (Bayer color) that imageing sensor is original to revert to the RGB data, the synchronous dynamic random access memory read-write controller is used for the frame of view data to be deposited and handles, initial data is transformed into the RGB data of 720p@60Hz or 1080p@50Hz, uses for showing.Described FPGA2 is provided with also that display interface drives and clock synchronous circuit, the high width video data of high-res interface configuration circuit, display interface drives and the clock synchronous circuit is used for the generation of internal clocking and the generation of display interface synchronised clock, and HDMI/DVI preparation circuit is used for the preparation control to the HDMI/DVI chip.
The output of commutation circuit can by cable directly and display driver circuit join, but preferably the output with described commutation circuit is connected to photoelectric conversion module 3, the output of photoelectric conversion module 3 is joined by optical fiber and photoelectric conversion module 4, and the FPGA2 in photoelectric conversion module 4 and the display driver circuit joins.
Embodiment 3:
Other circuit are with embodiment 1 or embodiment 2, different shown in Fig. 8,9: the output of photoelectric conversion module 3 is joined by optical fiber and photoelectric conversion module 5, photoelectric conversion module 5 joins with image storage playback reproducer, described image storage playback reproducer is provided with FPGA3, be connected to high-speed RAM with FPGA3, FPGA3 joins by PCI Express socket and computer; Described FPGA3 has the fpga logic unit, is connected to serial/separate crosstalk, RAM functional module and PCI Express functional module with the fpga logic unit, can be integrated on the circuit board, places in the PCI Express bus slot.
Primary processor adopts the programmable processor (FPGA) that has PCI Express function, realization is communicated by letter with the PCIExpress interface, programmable processor can make things convenient for the design memory interface, with outside high-speed RAM swap data, processor has serial/separate serializer circuit, can with photoelectric conversion module directly to connecting, realize the Optical Fiber Transmission of high sharpness video.
Claims (4)
1. high-resolution video monitoring system, the video camera that is arranged on the The Cloud Terrace is arranged, and the output and the matrix of video camera join, and the output of matrix is joined by display driver circuit and display, be connected to control device and image storage playback reproducer with matrix, it is characterized in that:
A. described video camera has camera lens, is connected to imageing sensor with camera lens, and the output and the FPGA1 of imageing sensor join, and the output of FPGA1 is leaded up to aperture drive circuit and camera lens and joined; One the tunnel joins with the RS422 interface, and another road and photoelectric conversion module 1 join; Described FPGA1 has data receiver circuit, and the output of data receiver circuit is joined with chroma processing circuit, image reconstruction circuit 1 respectively, and the output of chroma processing circuit and data coding-decoding circuit join, and data coding-decoding circuit and microprocessor join; The output of image reconstruction circuit 1 is joined by brightness processed circuit and microprocessor, and the output of microprocessor and I2C interface circuit join;
The output of b. described photoelectric conversion module 1 is joined by optical fiber and matrix, and described matrix is provided with photoelectric conversion module 2, and the output and the commutation circuit of photoelectric conversion module 2 are joined.
2. high-resolution video monitoring system according to claim 1 is characterized in that: described display driver circuit is provided with FPGA2, is connected to high-res high width video data interface and double digit rate synchronous dynamic random access memory with FPGA2; Described FPGA2 has image reconstruction circuit 2, is connected to the synchronous dynamic random access memory read-write controller with image reconstruction circuit 2; Described FPGA2 is provided with also that display interface drives and clock synchronous circuit, the high width video data of high-res interface configuration circuit, and display interface drives and clock synchronous circuit and synchronous dynamic random access memory read-write controller join.
3. high-resolution video monitoring system according to claim 2, it is characterized in that: be connected to photoelectric conversion module 3 with the output of described commutation circuit, the output of photoelectric conversion module 3 is joined by optical fiber and photoelectric conversion module 4, and the FPGA2 in photoelectric conversion module 4 and the display driver circuit joins.
4. high-resolution video monitoring system according to claim 3, it is characterized in that: the output of described photoelectric conversion module 3 is joined by optical fiber and photoelectric conversion module 5, photoelectric conversion module 5 joins with image storage playback reproducer, described image storage playback reproducer is provided with FPGA3, be connected to high-speed RAM with FPGA3, FPGA3 joins by PCI Express socket and computer; Described FPGA3 has the fpga logic unit, is connected to serial/separate serializer circuit, RAM functional module and PCIExpress functional module with the fpga logic unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200113137U CN201185457Y (en) | 2008-02-26 | 2008-02-26 | System for monitoring high-resolution video |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200113137U CN201185457Y (en) | 2008-02-26 | 2008-02-26 | System for monitoring high-resolution video |
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| CN201185457Y true CN201185457Y (en) | 2009-01-21 |
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| CNU2008200113137U Expired - Fee Related CN201185457Y (en) | 2008-02-26 | 2008-02-26 | System for monitoring high-resolution video |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227598B (en) * | 2008-02-26 | 2010-06-02 | 大连恒为电子有限公司 | High-resolution video monitoring system |
| CN102740053A (en) * | 2011-04-12 | 2012-10-17 | 东南大学 | Greenhouse monitoring informatization system networking method |
-
2008
- 2008-02-26 CN CNU2008200113137U patent/CN201185457Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227598B (en) * | 2008-02-26 | 2010-06-02 | 大连恒为电子有限公司 | High-resolution video monitoring system |
| CN102740053A (en) * | 2011-04-12 | 2012-10-17 | 东南大学 | Greenhouse monitoring informatization system networking method |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090121 Termination date: 20160226 |