A kind of broadcast level high speed high-definition camera
Technical field
The utility model relates to a kind of broadcast level video camera, and especially a kind of broadcast level high speed high-definition camera, belongs to camera technique field.
Background technology
The basic functional principle of video camera is: change optical image signal into the signal of telecommunication, so that gather, edit, store or transmit; When user takes an object with video camera, the light camera shots being shot that external sights therewith object reflects, pass through light path system, make on its sensitive surface focusing on picture pick-up device (target surface of such as camera chip), by semiconductor imaging device, the bright blackout of light is become large few different signal of telecommunication again, namely obtain what is called " vision signal ".The electro-optical signal obtained due to sensitive chip is very faint, first to be amplified the signal of telecommunication by pre-arcing road, carry out processing and adjusting through various circuit again, obtain standard " video " signal to deliver on record or the recording medium such as storage and remain, or play by broadcasting system, or deliver on monitor image is shown.
Usually video camera is roughly divided into three classes in industry, i.e. broadcast level, professional and family expenses level.
Broadcast level video camera is mainly used in the field of broadcast televisions of specialty, and picture quality is high, and performance is comprehensive, possesses various function adjustable specially, but expensive, and volume is also larger.According to the difference of radio and television application target, they can be divided into again following three kinds:
1) studio video camera, this camera operation under the condition being conducive to camera operation, as the appropriateness such as illumination intensity, colour temperature.In order to improve performance index, usually adopt larger-size picture pick-up device.Therefore, their definition is the highest, and signal to noise ratio is maximum, and picture quality is best.Certainly, volume is also large, and price common people neither can connect and can stand.
2) news interview (ENG) video camera, because the operational environment of this video camera is special, this kind of machine volume is little, lightweight, be easy to carry, to non-standard lighting condition, there is good adaptability, in adverse circumstances (as working temperature changes on a large scale) there is higher security and stability, have that debugging is convenient, automaticity is high, manipulate the features such as flexible, easy to carry, its picture quality is slightly lower than studio video camera, and price is also more relatively cheap.
3) live show makes (EFP) video camera, and EFP camera operation condition is between above-mentioned two kinds of video cameras, and performance index also take into account this two aspects.Their picture quality is close with studio video camera, but volume is smaller, can meet the needs that lightweight live show makes.
In sum, existing broadcast level video camera has the professional of height, outstanding picture quality and relatively high price.
Utility model content
The purpose of this utility model is the needs for the shooting of broadcast level video camera ultrahigh speed, provide a kind of broadcast level high speed high-definition camera, this broadcast level high speed high-definition camera structure is simple, easy for operation, can realize the high speed acquisition of broadcast level HD video data, transmission, storage and broadcasting.
The purpose of this utility model can reach by taking following technical scheme:
A kind of broadcast level high speed high-definition camera, comprise casing and camera lens bayonet socket, described casing internal is provided with imageing sensor and circuit board, camera lens is fixed on casing front portion by the adapter ring of described camera lens bayonet socket, and be connected with imageing sensor, described circuit board comprises memory device, FPGA data acquisition board, mainboard and image-signal processor, described FPGA data acquisition board adopts the fpga chip with PCI-E stone, and be connected with imageing sensor and image-signal processor respectively by SPI interface, described imageing sensor is also connected with the deserializer in FPGA data acquisition board by differential signal receiver in low voltage, described mainboard is connected with memory device and FPGA data acquisition board respectively by PCI-E interface.
Preferably, described FPGA data acquisition board has external memory storage by the deserializer expansion on this plate, and described external memory storage is connected with image-signal processor.
Preferably, described FPGA data acquisition board adopts the fpga chip of the Stratix IV series of ALTERA company.
Preferably, described casing internal is also provided with sensor panel, and described sensor panel is vertically set on the side of circuit board near camera lens, and is fixed by screws in casing front inner, and described imageing sensor is arranged on the front of sensor panel.
Preferably, the back side of described sensor panel is provided with power supply chip, stabilized voltage power supply, crystal oscillator and cable socket, and described power supply chip, stabilized voltage power supply, crystal oscillator are connected with circuit board respectively with cable socket.
Preferably, described memory device adopts the solid state hard disc of PCI-E interface.
Preferably, the capacity of described solid state hard disc is more than 300GB.
Preferably, described mainboard adopts the mainboard of X86-based.
Preferably, described image-signal processor adopts FH8510 chip.
Preferably, described memory device, FPGA data acquisition board and mainboard are arranged in a casing.
The utility model has following beneficial effect relative to prior art:
1, in broadcast level high speed high-definition camera of the present utility model, FPGA data acquisition board adopts the fpga chip (preferably adopting the fpga chip of the Stratix IV series of ALTERA company) with PCI-E stone, stable PCI-E X8 system can be developed efficiently, the low-voltage differential signal received from imageing sensor (LVDS) interface data is converted to PCI-E interface data by deserializer, then the data after conversion are transferred to image-signal processor, mainboard can be adopted the real-time reading video data of plate from FPGA number and be written to memory device, also exportable video data is to monitor, achieve the high speed acquisition of broadcast level HD video data, transmission, store and play.
2, broadcast level high speed high-definition camera of the present utility model arranges a sensor panel at casing internal; this sensor panel is vertically set on the side of circuit board near camera lens; and be fixed by screws in casing front inner; imageing sensor is arranged on the front of sensor panel; power supply chip, stabilized voltage power supply, crystal oscillator and cable socket are arranged on the back side of sensor panel; make the interior layout of whole casing reasonable; when safeguarding circuit board; first sensor panel can be pulled down, thus the device on protection sensor panel.
3, in broadcast level high speed high-definition camera of the present utility model, FPGA data acquisition board can expand an external memory storage, effectively to increase the memory space of high-speed data.
Accompanying drawing explanation
Fig. 1 is the casing internal board structure of circuit theory diagram of broadcast level high speed high-definition camera of the present utility model.
Fig. 2 is the cabinet sides schematic diagram of broadcast level high speed high-definition camera of the present utility model.
Fig. 3 is the sensor panel front schematic view of broadcast level high speed high-definition camera of the present utility model.
Fig. 4 is the sensor panel schematic rear view of broadcast level high speed high-definition camera of the present utility model.
Fig. 5 is the FPGA data acquisition board inter-process schematic diagram of broadcast level high speed high-definition camera of the present utility model.
Fig. 6 is the operation principle block diagram that broadcast level high speed high-definition camera is held with PC, monitor coordinates of the present utility model.
Wherein, 1-casing, 2-camera lens bayonet socket, 3-imageing sensor, 4-circuit board, 5-sensor panel, 6-adapter ring, 7-fixed screw post, 8-memory device, 9-FPGA data acquisition board, 10-mainboard, 11-image-signal processor, 12-differential signal receiver in low voltage, 13-deserializer, 14-external memory storage, 15-power supply chip, 16-stabilized voltage power supply, 17-crystal oscillator, 18-cable socket.
Embodiment
Embodiment 1:
As shown in Fig. 1 ~ Fig. 5, the broadcast level high speed high-definition camera of the present embodiment comprises casing 1 and camera lens bayonet socket 2, described casing 1 inside is provided with imageing sensor 3 and circuit board 4 and sensor panel 5, it is anterior that camera lens is fixed on casing 1 by the adapter ring 6 of described camera lens bayonet socket 2, and be connected with imageing sensor 3; It is inner that described circuit board 4 is arranged on casing 1 by fixed screw post 7, comprises memory device 8, FPGA (Field-Programmable Gate Array, field programmable gate array) data acquisition board 9, mainboard 10 and image-signal processor 11;
Described memory device 8 adopts solid state hard disc (the Solid State Drives of PCI-E interface, SSD), its capacity is more than 300GB, it is the board of the PCI-E2.08X of one piece of standard, overall dimension is 168.55*68.91*17.14mm, owing to having a large amount of memory spaces, so the multitude of video data write that imageing sensor 3 can be gathered.
In the present embodiment, described FPGA data acquisition board 9 adopts the fpga chip of the Stratix IV series of ALTERA company, the medium scale EP4SGX230 model of preferred employing, because this chip has PCI-E (PCIExpress) stone, stable PCI-E X8 system can be developed efficiently.
Described FPGA data acquisition board 9 is connected with imageing sensor 3 and image-signal processor 11 respectively by SPI interface (Serial Peripheral Interface, Serial Peripheral Interface (SPI)); Described imageing sensor 3 is cmos image sensor, and it adopts NOIL2SM1300A/D chip, is also connected with the deserializer 13 in FPGA data acquisition board 9 by low-voltage differential signal (LVDS) receiver 12; Described image-signal processor (Image SignalProcessor, ISP) 11 adopts FH8510 chip, is that a kind of picture signal strengthens processor; FPGA data acquisition board 9 is responsible for control chart image-position sensor 3, and by deserializer 13, the LVDS interface data of reception is converted to PCI-E interface data, and the bandwidth according to imageing sensor 3 is adjusted, and adopts PCI-E 8X interface to satisfy the demand.
Described FPGA data acquisition board 9 can an expansion external memory storage 14 by deserializer 13, and effectively to increase the memory space of high-speed data, described external memory storage 14 is FLASH RAM, and it is connected with image-signal processor 11; FPGA data acquisition board 9 can control read/write external memory storage 14 address.
Described differential signal receiver in low voltage 12 adopts the drive circuits such as SN65LVDS388A, is the LVDS receiver on more than eight tunnels, according to different demand, can select the LVDS receiver of different way.
Described deserializer 13 is the deserializer of Xilinx Virtex24, can realize the serioparallel exchange of 800Mbit/s input signal.
Described mainboard 10 adopts the mainboard of X86-based, because needs have 2 more than PCI-E2.08X interfaces, so select the mainboard of Micro ATX template, is of a size of 22.6*17.0cm.
Described mainboard 10 is connected with memory device 8 and FPGA data acquisition board 9 respectively by PCI-E interface, be responsible for from the real-time reading video data of FPGA data acquisition board 9 and be written to memory device 8, the data syn-chronization of memory device 8 is read simultaneously, that delivers to mainboard 10 on the one hand carries video card, output to monitor for playback by video driver, the interface be connected with monitor can be HDMI/DVI etc.; Send back FPGA data acquisition board 9 by PCI-E interface on the other hand, export parallel data to image-signal processor 11 by FPGA data acquisition board 9.
Be without prejudice to make these three vitals of memory device 8, FPGA data acquisition board 9 and mainboard 10, a casing is set, memory device 8, FPGA data acquisition board 9 and mainboard 10 are arranged in this casing, the size of comprehensive above-mentioned memory device 8, FPGA data acquisition board 9 and mainboard 10, box sizes is not less than 280mm*220mm*150mm (being followed successively by length), is approximately the size of a 2U cabinet.
Described sensor panel 5 is vertically set on the side of circuit board 4 near camera lens, and be fixed by screws in casing 1 front inner, described imageing sensor 3 is arranged on the front of sensor panel 5, the back side of described sensor panel 5 is provided with power supply chip 15, and (power supply chip 15 of the present embodiment has two, one is 3.3V, another is 1.8V), stabilized voltage power supply 16 (stabilized voltage power supply 16 of the present embodiment has two), crystal oscillator 17 and cable socket 18, described power supply chip 15, stabilized voltage power supply 16, crystal oscillator 17 is connected with circuit board 4 respectively with cable socket 18, such design makes the interior layout of whole casing 1 reasonable, when safeguarding circuit board 4, first sensor panel 5 can be pulled down, thus the device on protection sensor panel 5.
The broadcast level high speed high-definition camera of the present embodiment and PC hold, monitor cooperating as shown in Figure 6, wherein the PC work of having held is as follows:
1) driving of FPGA data collecting card (PCI-E 8X interface), first develops the driver of windows7, and developing instrument adopts SDK, finally provides reading and writing function level interface;
2) driver of solid state hard disc, the disc driver of acquiescence employing standard, without the need to exploitation;
3) interface program, complete the control man-machine interface of imageing sensor, complete the man-machine interface that image-signal processor controls, and PC exports the man-machine interface controlled, adopt VS2008 (Microsoft Visual Studio2008) exploitation, MFC (Microsoft Foundation Classes, Microsoft Foundation class libraries) framework;
4) realize the conversion of imageing sensor video data, reading, buffer memory and write solid state hard disc, adopt VS2008 exploitation, MFC framework;
5) realize the reading of stored video data in solid state hard disc, be sent to FPGA data collecting card, adopt VS2008 exploitation, MFC framework.
FPGA holds the work that will complete as follows:
1) receive the LVDS signal transmitted by differential signal receiver in low voltage from imageing sensor, and realize serioparallel exchange, buffer memory, data framing, be sent to PC end finally by PCI-E X8 passage; Developing instrument is quaruts12.1 (the comprehensive PLD/FPGA of ALTERA company develops software), uses the soft core of ALTLVDS_RX, ALTLVDS_TXIP and PCI-E IP stone;
2) receive PC and hold the solid state hard disc data, the buffer memory that send over from PCI-E interface, the data format converting image-signal processor requirement to sends to image-signal processor, carries out echo by monitor; Developing instrument is quaruts12.1, uses the soft core of ALTLVDS_RX, ALTLVDS_TX IP and PCIe IP stone;
3) the RS232 interface held of the SPI interface of interaction figure image-position sensor and PC, developing instrument is quaruts12.1;
4) the RS232 interface held of the SPI interface of mutual image-signal processor and PC, developing instrument is quaruts12.1.
Embodiment 2:
The main feature of the present embodiment is: described memory device 8, FPGA data acquisition board 9 and mainboard 10 can independently be arranged, and are not arranged in a casing.All the other are with embodiment 1.
In addition, those skilled in the art it will be appreciated that above-mentioned memory device 8, FPGA data acquisition board 9, mainboard 10, image-signal processor 11 etc. can also adopt other hardware of the same type.
In sum, broadcast level high speed high-definition camera structure of the present utility model is simple, easy for operation, adopt the fpga chip with PCI-E stone, stable PCI-E X8 system can be developed efficiently, thus realize the high speed acquisition of broadcast level HD video data, transmission, storage and broadcasting.
The above; be only the utility model patent preferred embodiment; but the protection range of the utility model patent is not limited thereto; anyly be familiar with those skilled in the art in the scope disclosed in the utility model patent; be equal to according to the technical scheme of the utility model patent and utility model patent design thereof and replaced or change, all belonged to the protection range of the utility model patent.