CN205195808U

CN205195808U - Medical treatment camera system

Info

Publication number: CN205195808U
Application number: CN201520845370.5U
Authority: CN
Inventors: 陈锦棋
Original assignee: Guangdong Softlink Medical Innovation Co Ltd
Current assignee: Guangdong Softlink Medical Innovation Co Ltd
Priority date: 2015-09-18
Filing date: 2015-10-27
Publication date: 2016-04-27
Anticipated expiration: 2025-10-27
Also published as: CN105323554A

Abstract

The utility model relates to a medical treatment camera system, sky including setting up above the operating table hangs the formula camera lens, sets up at the dive formula camera lens of implementing surgery location to and be used for the receipt sky to hang the formula camera lens and the video signal's of dive formula camera lens host computer. It hangs and is equipped with video capture chip and image manipulation chip in the formula camera lens, video capture chip is used for gathering outside image information, image manipulation chip is used for handling this image information to send to the host computer, be equipped with video capture chip and image manipulation chip in the dive formula camera lens, image manipulation chip is used for gathering outside image information, image manipulation chip is used for handling this image information to send to the host computer. The host computer is play the video of two camera lenses in real time and is recorded. Compared with the prior art, the utility model discloses an use simultaneously two way camera lenses of day formula of hanging and dive formula, shoot the perform the operation scene of in -process of doctor all -roundly.

Description

A kind of medical camera system

Technical field

The utility model relates to a kind of camera system, particularly a kind of medical camera system.

Background technology

When clinical treatment, particularly when doctor is when performing the operation, often needing to carry out carrying out observation surgical procedure by shooting, play in real time and record, can conveniently watch in surgical procedure, also can carry out demonstration lesson by video recording simultaneously.

But existing pick-up lens is single, the limited angle of shooting, is difficult to reduce the scene of whole operation and details.Particularly, at the discreet portions of operation, be difficult to shooting especially.

Therefore, for existing problem, need to provide a kind of can the medical camera system of omnidirectional shooting surgical.

Utility model content

The utility model is that the shortcoming overcoming prior art is with not enough, provides a kind of medical camera system.

The utility model is achieved through the following technical solutions: a kind of medical camera system, comprise and be arranged on sky hanging camera lens above operating table, be arranged on the submersible type camera lens implementing surgery location, and for the main frame of the vision signal that receives day hanging camera lens and submersible type camera lens;

Video capture processor and picture processing chip is provided with in described sky hanging camera lens; Described video capture processor is for gathering outside image information, and described picture processing chip is used for this image information to process, and is sent to main frame;

Video capture processor and picture processing chip is provided with in described submersible type camera lens; Described picture processing chip is for gathering outside image information, and described picture processing chip is used for this image information to process, and is sent to main frame;

Described main frame inside is provided with and drives display chip and video record chip; Described driving display chip, carries out broadcasting display for the video information of sky hanging camera lens collection that will receive and the video information of submersible type camera lens collection; Described video record chip, preserves for the video information of sky hanging camera lens collection and the video information of submersible type camera lens collection being carried out recording.

Compared to prior art, the utility model is by arranging two camera lenses, a sky hanging camera lens simultaneously, a submersible type camera lens, can respectively on and under observe the overall situation surgical procedure, meanwhile, the subtlety of the operation of doctor on operating table can be observed by submersible type camera lens.Meanwhile, by a main frame, the video gathered by two camera lenses carries out merging and plays and record, and is convenient to the viewing in surgical process, also may be used for formality instructional video and uses.

As further improvement of the utility model, in described sky hanging camera lens, be provided with the first signal conversion chip and secondary signal conversion chip; The video signal of described sky hanging camera lens collection is LVDS signal; Described first signal conversion chip, it is connected with picture processing chip, and this LVDS signal is converted to BT1120 signal, and this BT1120 signal is sent to secondary signal conversion chip; BT1120 signal is converted to sdi signal by described secondary signal conversion chip, and is sent in main frame; Described main frame inside is provided with the 3rd signal conversion chip, for sdi signal is converted to BT1120 signal.

As further improvement of the utility model, the video signal of described submersible type camera lens collection is CVBS signal; Described main frame inside is provided with the 4th signal conversion chip, for this CVBS signal is converted to BT656 signal.

As further improvement of the utility model, described main frame inside is also provided with an image enhaucament chip, for receiving the vision signal of day hanging camera lens and submersible type camera lens, and carries out enhancing process, then is sent to video record chip respectively and drives display chip.

As further improvement of the utility model, the video capture processor of described sky hanging camera lens and submersible type camera lens inside all comprises: control module, driver module, illuminant module, sampling module and output module;

Described control module, it sends triggering signal to driver module for receiving outside triggering signal;

Described driver module, it for receiving the triggering signal of control module, and drives illuminant module work;

Described illuminant module, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;

Described sampling module, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of illuminant module, and is sent to output module by it;

Described output module, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.

As further improvement of the utility model, described video capture processor also comprises one times of frequency module, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to control module.

As further improvement of the utility model, described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal.

As further improvement of the utility model, the picture processing chip of described sky hanging camera lens and submersible type camera lens inside all comprises: data sink, master controller, image processor and data logger;

Described data sink, it is for receiving outside view data;

Described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;

Described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;

Described data logger, it is for exporting the view data after process.

As further improvement of the utility model, described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller.

As further improvement of the utility model, described image processor also comprises an exposure gain circuit, for increasing exposure gain size.

As further improvement of the utility model, described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.

As further improvement of the utility model, described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving.

As further improvement of the utility model, the video record chip of described main frame inside comprises: data sink, video encoder, Video Decoder, data logger and processor;

Described data sink, for receiving outside vision signal, and is sent to video encoder;

Described video encoder, for recording encoding video signal;

Described Video Decoder, for decoding video signal playback;

Described data logger, for exporting vision signal;

Described processor, for the work of control data receiver, video encoder, Video Decoder and data logger.

As further improvement of the utility model, described video record chip also comprises an image processor, processes for the video received data sink, and the image after process is sent to video encoder.

As further improvement of the utility model, described image processor comprises edge intensifier circuit and the interfered circuit that abates the noise.

As further improvement of the utility model, described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM; Described video input port is connected with the data sink of this center processing chip internal, for receiving outside video data; Described video-out port, is connected with described data logger, for output video data; Described PORT COM, is connected with described processor, for receiving outside serial port command.

As further improvement of the utility model, the driving display chip of described main frame inside comprises: receiver of the analog signal, digit signal receiver, analog to digital converter, multiplexer, output format transducer, data logger and controller;

Described receiver of the analog signal, for receiving analog signal, and is sent to analog to digital converter;

Described analog to digital converter, for analog signal is converted to data-signal, and is sent to multiplexer;

Described data signal receiver, for receiving data-signal, and is sent to multiplexer;

Described multiplexer, for being integrated by two paths of signals, line output of going forward side by side is to output format transducer;

Described output format transducer, for signal format being changed, and exports data logger to;

Described data logger, exports signal, and shows;

Described controller, for the work of control simulation signal receiver, digit signal receiver, analog to digital converter, multiplexer, output format transducer and data logger.

As further improvement of the utility model, described driving display chip also comprises a Video Decoder, field flyback data processor and memory;

Described Video Decoder, decodes for the analog signal received by receiver of the analog signal, and is sent to field flyback data processor;

Described field flyback data processor, for by capable for decoded analog signal data inserting, and be sent to described memory and store;

Described memory, for storing the data after field flyback data processor processes, and is sent to output format transducer.

As further improvement of the utility model, described driving display chip also comprises an image border smoothing processor, for receiving the signal of restorer, and to the smoothing process in the edge of video image, then is sent to format converter.

As further improvement of the utility model, described data logger carries out color simultaneously and exports and the output of LVDS vision signal.

As further improvement of the utility model, the outside of described driving display chip is provided with: power port, video reception port and VT mouth; Receiver of the analog signal and the data signal receiver of described video reception port and center processing chip internal are connected; Described video-out port is connected with the data logger of center processing chip internal.

As further improvement of the utility model, described first signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;

Described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;

Described data reader, it for receiving LVDS video transfer signal, and is sent to signal format converter;

Described signal format converter, it for LVDS vision signal being converted to the vision signal of BT1120, and is sent to deserializer;

Described deserializer, it for serial data is converted to parallel data, and is sent to data logger;

Described data logger, for exporting BT1120 video signal data.

As further improvement of the utility model, described secondary signal conversion chip comprises: data buffer, low noise phase-locked loop, ASI synchronization encoders, serializer, serial image scrambler, cable driver and end noise phase-locked loop;

Described data buffer, for receiving the BT1120 signal of the first signal conversion chip, and is sent to ASI synchronization encoders;

Described low noise phase-locked loop, it is connected with data buffer, stable for holding frequency and phase place;

Described ASI synchronization encoders, for this BT1120 signal is carried out coded treatment, is converted to sdi signal, and is sent to serializer;

Described serializer, for parallel signal is converted to serial signal, and is sent to serial image scrambler;

Described serial image scrambler, for being encrypted signal data, and is sent to cable driver;

Described cable driver, for being sent to main frame by this sdi signal.

As further improvement of the utility model, described 3rd signal conversion chip comprises: cable equalizer, data recoverer, crystal oscillator, serial image descrambler, deserializer, ASI sync decoder, data extractor and data buffer;

Described cable equalizer, for receiving sdi signal and carrying out correction process, then is sent to data recoverer;

Described data recoverer, for recovering data from the distortion and noise of transmission channel, and is sent to serial image descrambler;

Described serial image descrambler, for being decrypted by signal data, and is sent to deserializer;

Described deserializer, for serial signal data are converted to parallel signal data, and is sent to ASI sync decoder;

Described ASI sync decoder, for decoding data, is converted to BT1120 signal, and is sent to data extractor;

Described data extractor, for decoded data being extracted, and is sent to data buffer;

Described data buffer, for sending the signal of reception.

As further improvement of the utility model, described 4th signal conversion chip comprises: the contrast saturation control circuit of the data amplitude limiter of analog to digital converter, analog controller, many standards, data bypass sampling filter, colourity and brightness, synchronous circuit, clock generator and formatted output device;

Described analog to digital converter, for receiving CVBS signal, and is converted to digital signal by this analog signal, and sends to analog controller;

Described analog controller, for receiving this BT656 digital signal, and is sent to data amplitude limiter, the data bypass sampling filter of many standards simultaneously, and the contrast saturation control circuit of colourity and brightness;

The data amplitude limiter of described many standards, for the stability of inhibit signal transmission, and is sent to formatted output device;

Described data bypass sampling filter, for filtering interference signal, and is sent to formatted output device;

The contrast saturation control circuit of described colourity and brightness, for controlling the colourity of image data, the contrast saturation of brightness, and is sent to formatted output device;

Described synchronous circuit is connected with the contrast saturation control circuit of colourity and brightness and clock generator respectively, for the contrast saturation control circuit of colourity and brightness provides pulse clock signal, makes itself and main system synchronous operation;

Described formatted output device, for being BT656 by Signal form translate, and exports this signal.

In order to understand better and implement, describe the utility model in detail below in conjunction with accompanying drawing.

Accompanying drawing explanation

Fig. 1 is the connection diagram of medical camera system of the present utility model.

Fig. 2 is the inside chip connection diagram of medical camera system of the present utility model.

The internal circuit connection diagram of Fig. 3 formula video capture processor.

Fig. 4 is the outside port schematic diagram of video capture processor.

Fig. 5 is the circuit diagram of the power unit of video capture processor.

Fig. 6 is the circuit diagram of the 2.7V of video capture processor.

Fig. 7 is the circuit diagram of the 1.8V of video capture processor.

Fig. 8 is the circuit diagram of the 1.2V of video capture processor.

Fig. 9 is the interface enlarged drawing of video capture processor row field signal.

Figure 10 is the partial enlarged drawing of the reference signal port of video capture processor.

Figure 11 is the circuit diagram of the clock circuit of video capture processor.

Figure 12 is the circuit diagram of the configuration circuit of video capture processor.

Figure 13 is the internal circuit connection diagram of picture processing chip of the present utility model.

Figure 14 is the circuit module schematic diagram of image processor of the present utility model.

The voltage segment port circuit figure of Figure 15 picture processing chip.

Figure 16 is picture processing chip outside port circuit diagram.

Figure 17-19 is the power supply of picture processing chip is respectively the circuit diagram of 3.3V, 1.8V and 1.2V.

Figure 20 is the partial enlarged drawing of the receiver port of picture processing chip.

Figure 21 is the partial enlarged drawing of the video signal port of picture processing chip.

Figure 22 is the partial enlarged drawing of the row field signal port of picture processing chip.

Figure 23 is the schematic diagram of the clock circuit of picture processing chip.

Figure 24 is the schematic diagram of the memory circuit of picture processing chip.

Figure 25 is the partial enlarged drawing of the PORT COM of picture processing chip.

Figure 26 is the internal circuit connection diagram of the first signal conversion chip.

Figure 27 is the outside port connection diagram of the first signal conversion chip.

Figure 28 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.

Figure 29 is the partial enlarged drawing of the video signal port of secondary signal conversion chip.

Figure 30 is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.

Figure 31 is the internal circuit connection diagram of secondary signal conversion chip.

Figure 32 is the outside port connection diagram of secondary signal conversion chip.

Figure 33 is the partial enlarged drawing of the power port of secondary signal conversion chip.

Figure 34 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.

Figure 35 is the signal output port partial enlarged drawing of secondary signal conversion chip.

Figure 36 is the partial enlarged drawing of the reseting port of secondary signal conversion chip.

Figure 37 is the internal circuit connection diagram of the 3rd signal conversion chip.

Figure 38 is the outside port connection diagram of the 3rd signal conversion chip.

Figure 39 is the partial enlarged drawing of power port.

Figure 40 is the voltage conversion circuit that 3.3V is converted to 1.2V.

Figure 41 is the partial enlarged drawing of signal input port.

Figure 42 is the partial enlarged drawing of signal output port.

Figure 43 is the internal circuit connection diagram of the 4th signal conversion chip.

Figure 44 is the outside port connection diagram of the 4th signal chip.

Figure 45 is the voltage filtering circuit figure of the 4th signal chip.

Figure 46 is CVBS signal input circuit figure.

Figure 47 is the internal circuit connection diagram of image enhaucament chip.

Figure 48 and Figure 49 is the outside connecting circuit figure of image enhaucament chip respectively.

Figure 50 is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.

Figure 51-52 is the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V respectively.

Figure 53 is the partial enlarged drawing of the receiver port of image enhaucament chip.

Figure 54 is the partial enlarged drawing of the video signal port of image enhaucament chip.

Figure 55 is the circuit diagram of the clock circuit of image enhaucament chip.

Figure 56 is the partial enlarged drawing of the row field signal port of image enhaucament chip.

Figure 57 is the internal circuit connection diagram driving display chip.

Figure 58-59 drives the signal input of display chip and signal to export schematic diagram.

Figure 60 is the partial enlarged drawing of the power port driving display chip.

Figure 61 is the partial enlarged drawing of the video input port driving display chip.

Figure 62 is the partial enlarged drawing of the video-out port driving display chip.

Figure 63 is the internal circuit connection diagram of video record chip.

Figure 64-66 is outside port connection diagrams of video record chip.

Figure 67 is the partial enlarged drawing of power port.

Figure 68 is the partial enlarged drawing of PORT COM.

Embodiment

Refer to Fig. 1, it is the connection diagram of medical camera system of the present utility model.The utility model provides a kind of medical camera system, and it comprises and is arranged on sky hanging camera lens 1 above operating table, is arranged on the submersible type camera lens 2 implementing surgery location, and for the main frame 3 of the vision signal that receives day hanging camera lens 1 and submersible type camera lens 2.

Concrete, refer to Fig. 2, it is the inside chip connection diagram of medical camera system of the present utility model.

Video capture processor 11 and picture processing chip 12 is provided with in described sky hanging camera lens 1; Described video capture processor is for gathering outside image information, and described picture processing chip 12 for this image information being processed, and is sent to main frame 3;

Video capture processor 21 and picture processing chip 22 is provided with in described submersible type camera lens; Described picture processing chip 21 is for gathering outside image information, and described picture processing chip 22 for this image information being processed, and is sent to main frame 3;

Described main frame 3 inside is provided with and drives display chip 34 and video record chip 35; Described driving display chip 34, the video information gathered for the video information that gathered by the sky received hanging camera lens 1 and submersible type camera lens 2 carries out broadcasting display; Described video record chip 35, the video information gathered for the video information that gathered by sky hanging camera lens 1 and submersible type camera lens 2 is carried out recording and is preserved.

Further, in order to reduce the attenuation degree of day hanging camera lens 1 and submersible type camera lens 2 signal in the process of transmission, the stability of inhibit signal transmission.The preferred mode of another kind as the present embodiment, is provided with the first signal conversion chip 13 and secondary signal conversion chip 14 in described sky hanging camera lens; The video signal of described sky hanging camera lens collection 1 is LVDS signal; Described first signal conversion chip 13, it is connected with picture processing chip 12, and this LVDS signal is converted to BT1120 signal, and this BT1120 signal is sent to secondary signal conversion chip 14; BT1120 signal is converted to sdi signal by described secondary signal conversion chip 14, and is sent in main frame 3; Described main frame 3 inside is provided with the 3rd signal conversion chip 31, for sdi signal is converted to BT1120 signal.

Further, the video signal of described submersible type camera lens collection is CVBS signal; Described main frame inside is provided with the 4th signal conversion chip 32, for this CVBS signal is converted to BT656 signal.

Further in order to strengthen show in main frame time image readability, as the optimal way of the present embodiment, described main frame inside is also provided with an image enhaucament chip 33, for receiving the vision signal of day hanging camera lens 1 and submersible type camera lens 2, and carry out enhancing process, then be sent to video record chip 35 respectively and drive display chip 34.

Further, below the connection of the internal circuit blocks of said chip is described respectively, specific as follows:

Refer to Fig. 3, it is the internal circuit connection diagram of video capture processor.

The video capture processor 11 of hanging camera lens inside, described sky and the video capture processor 21 of submersible type camera lens inside all comprise: control module 111, driver module 112, illuminant module 113, sampling module 114, output module 115 and doubly frequency module 116;

Described control module 111, it sends triggering signal to driver module 112 for receiving outside triggering signal;

Described driver module 112, it is for receiving the triggering signal of control module, and drives illuminant module 113 to work;

Described illuminant module 113, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;

Described sampling module 114, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of illuminant module, and is sent to output module 115 by it;

Described output module 115, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.

Described times of frequency module 116, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to control module 111.

Concrete, refer to Fig. 4, it is the outside port schematic diagram of video capture processor.

Described video capture processor outside is provided with: the power port 101 for receiver voltage, the video signal port 102 for outputting video signal, for export row field signal row field signal port one 03, for receiving reference voltage electricity reference signal port one 04 frequently, for receiving the clock signal port 105 of external timing signal and the communication command port one 06 for receiving operate outside mode command.

Please refer to Fig. 5, it is the circuit diagram of the power unit of video capture processor.Concrete, the power unit in video capture processor adopts three kinds of voltages simultaneously, is respectively 2.7V, 1.8V, and 1.2V.

Please refer to Fig. 6-8, it is respectively the circuit diagram of 2.7V, 1.8V and 1.2V of video capture processor.Concrete, the input port 101 of three kinds of voltages of video capture processor is all circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Wherein, the voltage place in circuit of 2.7V and 1.8V comprises four electric capacity, and the voltage place in circuit of 1.2V comprises three electric capacity, to filter the interference signal of different frequency.

Refer to Fig. 9, it is the interface enlarged drawing of row field signal.Further, described row field signal port one 03 is circumscribed with one for providing the resistance of signal strength signal intensity.By this row field signal, for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.

Refer to Figure 10, it is the partial enlarged drawing of the reference signal port of video capture processor.Further, described reference signal port one 04 is circumscribed with the electric capacity as voltage electricity frequency reference data.In the present embodiment, described reference signal port has 7, the electric capacity of the external 1uF of each port.

Refer to Figure 11, it is the circuit diagram of the clock circuit of video capture processor.The external clock circuit of described clock signal port 105, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.

Refer to Figure 12, it is the circuit diagram of the configuration circuit of video capture processor.Further, described communication command port one 06, it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.

Refer to Figure 13, it is the internal circuit connection diagram of picture processing chip of the present utility model.

The picture processing chip of described sky hanging camera lens and submersible type camera lens inside all comprises: data sink 121, master controller 122, image processor 123 and data logger 124;

Described data sink 121, it is for receiving outside view data;

Described master controller 122, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;

Described image processor 123, it is for processing image;

Described data logger 124, it is for exporting the view data after process.

Further, described picture processing chip also comprises a frequency multiplier 125, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller 122.

Refer to Figure 14, it is the circuit module schematic diagram of image processor of the present utility model.

Concrete, described image processor 123 comprises a Lens Shading Compensation circuit 1231, optical detection circuit 1232, flash detection circuit 1233, exposure gain circuit 1234 and white balance permanent circuit 1235.

Described Lens Shading Compensation circuit 1231, it compensates process for the shade produced by camera lens.

Described optical detection circuit 1232 and flash detection circuit 1233, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.

Described exposure gain circuit 1234, for increasing exposure gain size.

Described white balance permanent circuit 1235, it, for according to the parameter preset, carries out the fixed adjustment of white balance.

Please refer to Figure 15 and Figure 16, it is respectively voltage segment and other outside port circuit diagrams of picture processing chip.In addition, in order to the application in order to adapt to this video capture processor, be provided with in described video capture processor outside further: for receive supply power voltage power port 201, for receive picture signal receiver port 202, for outputting video signal video signal port 203, for export row field signal row field signal port 204, for receive external timing signal clock signal port 205, for receive store data data receiver port 206 and one for receiving the PORT COM 207 of external communication order.

Refer to Figure 17-19, its power supply being respectively picture processing chip is the circuit diagram of 3.3V, 1.8V and 1.2V.Further, described power port 201 is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Concrete, the external voltage of video capture processor of the present utility model comprises: 3.3V, 1.8V and 1.2V tri-kinds.Wherein, 3.3V voltage place in circuit comprises 2 electric capacity, and 1.8V voltage place in circuit comprises 5 electric capacity, and the voltage place in circuit of 1.2V comprises 6 electric capacity, to filter the interference signal of different frequency respectively.

Refer to Figure 20, it is the partial enlarged drawing of the receiver port of picture processing chip.Described receiver port 202 comprises 8 pins, for receiving outside video signal.

Refer to Figure 21, it is the partial enlarged drawing of the video signal port of picture processing chip.Described video signal port 203 comprises the vision signal of two groups of different-formats, carries out doubleway output, plays in real time respectively to facilitate and records.

Refer to Figure 22, it is the partial enlarged drawing of the row field signal port of picture processing chip.Described row field signal port 204 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.

Refer to Figure 23, it is the schematic diagram of the clock circuit of picture processing chip.The external clock circuit of described clock signal port 205, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.

Refer to Figure 24, it is the schematic diagram of the memory circuit of picture processing chip.Further, described data receiver port 206 is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.

Refer to Figure 25, it is the partial enlarged drawing of the PORT COM of picture processing chip.Described PORT COM 207, for receiving the trigger command of external transmission, carries out work with what trigger this picture processing chip.

Refer to Figure 26, it is the internal circuit connection diagram of the first signal conversion chip.

Described first signal conversion chip 13 comprises: controller 131, data reader 132, signal format converter 133, deserializer 134, data logger 135, phase-locked loop 136 and clock data restorer 137;

Described controller 131, it is for receiving outside triggering signal, and the work of control data reader 132, signal format converter 133, deserializer 134 and data logger 135;

Described data reader 132, its LVDS video transfer signal for video capture processor is gathered, and be sent to signal format converter 133;

Described signal format converter 133, it for LVDS vision signal being converted to the vision signal of bt1120, and is sent to deserializer 134;

Described deserializer 134, it is for being converted to parallel data by serial data, and is sent to data logger 135;

Described data logger 135, for exporting bt1120 video signal data.

Described phase-locked loop 136, is connected with signal format converter 133 and deserializer 134 respectively, for unified integration clock signal.

Described clock data restorer 137, it is connected with data reader 132, for recovering data from the distortion and noise of transmission channel.

Refer to Figure 27, it is the outside port connection diagram of the first signal conversion chip.

In addition, in order to the application in order to adapt to this first signal conversion chip, be provided with in described signal conversion chip outside further: for receive LVDS vision signal receiver port 301, for exporting video signal port 302 and the row field signal port 303 of bt1120 vision signal.

Refer to Figure 28, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip.Described receiver port 301, it is connected with described data reader 132; Concrete, this receiver port includes 4 pins, for receiving the LVDS vision signal that picture processing chip exports.

Refer to Figure 29, it is the partial enlarged drawing of the video signal port of secondary signal conversion chip.Described video signal port 302 includes 20 output pins, and for exporting bt1120 vision signal, and this video signal port is connected with this data logger.

Refer to Figure 30, it is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.Described row field signal port 303 includes a line signal output pin and a field signal output pin; Described row field signal port 303 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.

Refer to Figure 31, it is the internal circuit connection diagram of secondary signal conversion chip.

Described secondary signal conversion chip 14 comprises: data buffer 141, low noise phase-locked loop 142, ASI synchronization encoders 143, serializer 144, serial image scrambler 145, cable driver 146 and end noise phase-locked loop 147;

Described data buffer 141, for receiving the BT1120 signal of the first signal conversion chip, and is sent to ASI synchronization encoders 142;

Described low noise phase-locked loop 142, it is connected with data buffer, stable for holding frequency and phase place;

Described ASI synchronization encoders 143, for this BT1120 signal is carried out coded treatment, is converted to sdi signal, and is sent to serializer 144;

Described serializer 144, for parallel signal is converted to serial signal, and is sent to serial image scrambler 145;

Described serial image scrambler 145, for being encrypted signal data, and is sent to cable driver 146;

Described cable driver 146, for being sent to main frame 30 by this sdi signal.

Refer to Figure 32, it is the outside port connection diagram of secondary signal conversion chip.

In addition, in order to the application in order to adapt to this first signal conversion chip, be provided with in described signal conversion chip outside further: for carry out powering for chip power port 401, for receiving the receiver port 402 of the BT1120 signal of the first signal conversion chip,, for exporting the signal output port 403 of sdi signal, and for the reseting port 404 of chip reset.

Please refer to Figure 33, it is the partial enlarged drawing of the power port of secondary signal conversion chip.Described power port 401 comprises the pin of 8 access power supplys, and the power supply wherein accessed is 1.2V.

Please refer to Figure 34, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip.Described receiver port 402 comprises 20 signal access pins.

Please refer to Figure 35, it is the signal output port partial enlarged drawing of secondary signal conversion chip.Described signal output port 403 is for exporting sdi signal, and this port comprises a reset pin and two output pins.

Please refer to Figure 36, it is the partial enlarged drawing of the reseting port of secondary signal conversion chip.Described reseting port is external passes through a resistance R83 and electric capacity C73 ground connection; Meanwhile, power supply VCC is connected between resistance R83 and electric capacity C73 by a resistance R84.

Refer to Figure 37, it is the internal circuit connection diagram of the 3rd signal conversion chip.

Described 3rd signal conversion chip 31 comprises: cable equalizer 311, data recoverer 312, crystal oscillator 313, serial image descrambler 314, deserializer 315, ASI sync decoder 316, data extractor 317 and data buffer 318;

Described cable equalizer 311, for receiving sdi signal and carrying out correction process, then is sent to data recoverer 312;

Described data recoverer 312, for recovering data from the distortion and noise of transmission channel, and is sent to serial image descrambler 314;

Described crystal oscillator 313, for providing pulse clock signal for data recoverer 312;

Described serial image descrambler 314, for being decrypted by signal data, and is sent to deserializer 315;

Described deserializer 315, for serial signal data are converted to parallel signal data, and is sent to ASI sync decoder 316;

Described ASI sync decoder 316, for decoding data, is converted to BT1120 signal, and is sent to data extractor 317;

Described data extractor 317, for decoded data being extracted, and is sent to data buffer 318;

Described data buffer 318, for sending the signal of reception.

Please refer to Figure 38, it is the outside port connection diagram of the 3rd signal conversion chip.

Further, in order to adapt to the application of the 3rd signal conversion chip, the outside port for this chip is now needed to be configured, concrete, the outside of described 3rd signal conversion chip is provided with: for for chip power supply power port 501, for receive sdi signal signal input port 502, for export BT1120 signal signal output port 503, for receiving the PORT COM 504 of external communication order, and for the clock signal port 505 of receive clock signal; Described clock signal port 505 is circumscribed with a crystal oscillator, for providing clock signal.

Please refer to Figure 39, it is the partial enlarged drawing of power port.Described power port comprises 15 power input pin, and the supply voltage wherein inputted comprises 1.2V and 3.3V two kinds.And in order to realize the conversion of voltage, the present embodiment also provides voltage conversion circuit.Specifically refer to Figure 40, it is converted to the voltage conversion circuit of 1.2V for 3.3V.Described voltage conversion circuit comprises an electric pressure converter; The input of described electric pressure converter is connected with 3.3V voltage; Concrete, the voltage of this 3.3V is connected with the input IN of electric pressure converter by an inductance L 9, and holds at the IN of this inductance and electric pressure converter, by two capacity earths in parallel, to play the effect of filtering.The output OUT of described electric pressure converter exports 1.2V voltage; Concrete, the output voltage of this 1.2V passes through the capacity earth of two parallel connections, to play the effect of filtering.

Refer to Figure 41, it is the partial enlarged drawing of signal input port.Described signal input port 502 is for receiving sdi signal, and this sdi signal carries out impedance matching, to improve through-put power by connecting inductance, electric capacity and resistance.

Refer to Figure 42, it is the partial enlarged drawing of signal output port.Described signal output port 503 is for exporting BT1120 signal, and this signal output port comprises the signal output pin of 20 BT1120, and row field signal output pin.

Refer to Figure 43, it is the internal circuit connection diagram of the 4th signal conversion chip.

Described 4th signal conversion chip 32 comprises: the contrast saturation control circuit 325 of the data amplitude limiter 323 of analog to digital converter 321, analog controller 322, many standards, data bypass sampling filter 324, colourity and brightness, synchronous circuit 326, clock generator 327 and formatted output device 328;

Described analog to digital converter 321, for receiving CVBS signal, and is converted to digital signal by this analog signal, and sends to analog controller 322;

Described analog controller 322, for receiving this BT656 digital signal, and is sent to data amplitude limiter 323, the data bypass sampling filter 324 of many standards simultaneously, and the contrast saturation control circuit 325 of colourity and brightness;

The data amplitude limiter 323 of described many standards, for the stability of inhibit signal transmission, and is sent to formatted output device 328;

Described data bypass sampling filter 324, for filtering interference signal, and is sent to formatted output device 328;

The contrast saturation control circuit 325 of described colourity and brightness, for controlling the colourity of image data, the contrast saturation of brightness, and is sent to formatted output device 328;

Described synchronous circuit 326 is connected with the contrast saturation control circuit 325 of colourity and brightness and clock generator 327 respectively, for the contrast saturation control circuit 325 of colourity and brightness provides pulse clock signal, makes itself and main system synchronous operation;

Described formatted output device 328, for being BT656 by Signal form translate, and exports this signal.

Please refer to Figure 44, it is the outside port connection diagram of the 4th signal chip.

Further, in order to adapt to the application of the 4th signal conversion chip, the outside port for this chip is now needed to be configured, concrete, the outside of described 4th signal conversion chip is provided with: for for chip power supply power port 601, for receive CVBS signal signal input port 602, for export BT656 signal signal output port 603, for receiving the PORT COM 604 of external communication order, and for the clock signal port 605 of receive clock signal; Described clock signal port 605 is circumscribed with a crystal oscillator, for providing clock signal.

Please refer to Figure 45, it is the voltage filtering circuit figure of the 4th signal chip.Described voltage signal port is circumscribed with a voltage filtering circuit.The voltage of the .33V inputted accesses the power port of the 4th signal chip by this filter circuit.

Please refer to Figure 46, it is CVBS signal input circuit figure.Described signal input port 603 is for receiving CVBS signal; Described CVBS signal, when inputting, by contact resistance and electric capacity, carries out leading anti-coupling, provides signal power during input.

Refer to Figure 47, it is the internal circuit connection diagram of image enhaucament chip.

Described image enhaucament chip internal comprises: data sink 331, de-noising processor 332, dynamic memory 333, image intensifier 334, pixel self adaptation proofreading equipment 335, data logger 336, static memory 337, controller 338, vision signal multiplier 339, storage signal multiplier 3310 and clock generator 3311.

Described data sink 331, it is for receiving viewdata signal, and is sent to de-noising processor 332;

The viewdata signal that described data sink 331 receives, is sent to de-noising processor 332 and carries out noise reduction process, then be forwarded to dynamic memory 333.

After the view data of described dynamic memory 333 after receiving de-noising processor 2 process, then be forwarded to image intensifier 334.

Described image intensifier 334, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border.Further, the view data after process is first sent to described pixel self adaptation proofreading equipment 335 by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger 336 by this pixel self adaptation proofreading equipment 335.

Described data logger 336, it for receiving the view data after image intensifier process, and carries out data output;

Described static memory 337, it is for the driving data of memory image booster, to drive the work of this image intensifier;

Described controller 338, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;

Described clock generator 3311, its for centered by process chip clocking.Further, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier 339 and storage signal multiplier 3310, and by this vision signal multiplier 339, clock signal is sent to data sink, by this storage signal multiplier 3310, clock signal is sent to dynamic memory and static memory.

Please refer to Figure 48 and Figure 49, it is respectively the outside connecting circuit figure of image enhaucament chip.

Further, described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port 701, for outputting video signal video signal port 702, for receive external timing signal clock signal port 703, for exporting the row field signal port 704 of row field signal.

Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and 1.2V tri-kinds of voltages.Refer to Figure 50, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.

Refer to Figure 51-52, it is respectively the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively the voltage of 1.8V and 1.2V.Concrete, described power-switching circuit comprises a power conversion chip; The voltage of the input access 3.3V of described power conversion chip, output exports the voltage of 1.8V and 1.2V respectively, to power to image enhaucament chip.

Refer to Figure 53, it is the partial enlarged drawing of the receiver port of image enhaucament chip.Described receiver port 701 comprises 20 signal pins, is connected with the data sink 331 of inside, for receiving the picture signal of input.

Refer to Figure 54, it is the partial enlarged drawing of the video signal port of image enhaucament chip.Described video signal port 702 comprises 20 signal pins, and it is connected, for output image signal with inner data logger 336.

Refer to Figure 55, it is the circuit diagram of the clock circuit of image enhaucament chip.Further, the external clock circuit of described clock signal port 703, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.

Refer to Figure 56, it is the partial enlarged drawing of the row field signal port of image enhaucament chip.Described row field signal port 704 comprises a row signal pins and a field signal pin.Described row field signal port 704 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.

Refer to Figure 57, it is the internal circuit connection diagram driving display chip.

The driving display chip 34 of described main frame inside comprises: receiver of the analog signal 341, digit signal receiver 342, analog to digital converter 343, multiplexer 344, image border smoothing processor 345, Video Decoder 346, field flyback data processor 347, memory 348, output format transducer 349, data logger 3410 and controller 3411.

Described receiver of the analog signal 341, for receiving analog signal, and is sent to analog to digital converter 343;

Described data signal receiver 342, for receiving data-signal, and is sent to multiplexer 344;

Described analog to digital converter 343, for analog signal is converted to data-signal, and is sent to multiplexer 344;

Described multiplexer 344, for being integrated by two paths of signals, line output of going forward side by side is to output image edge-smoothing processor 345;

Described image border smoothing processor 345, for receiving the signal of restorer, and to the smoothing process in the edge of video image, then is sent to format converter 349.

Described Video Decoder 346, decodes for the analog signal received by receiver of the analog signal, and is sent to field flyback data processor 347;

Described field flyback data processor 347, for by capable for decoded analog signal data inserting, and be sent to described memory 348 and store;

Described memory 348, for storing the data after field flyback data processor processes, and is sent to output format transducer 349.

Described output format transducer 349, for signal format being changed, and exports data logger 3410 to;

Described data logger 3410 carries out color simultaneously and exports and the output of lvds vision signal.

Described controller 3411, for the work of control simulation signal receiver 341, digit signal receiver 342, analog to digital converter 343, multiplexer 344, image border smoothing processor 345, Video Decoder 346, field flyback data processor 347, memory 348, output format transducer 349 and data logger 3410.

Please refer to Figure 58-59, it is drive the signal input of display chip and signal to export schematic diagram.

The outside of described driving display chip is provided with: power port 801, video reception port 802 and VT mouth 803; Described video reception port 802 is connected with the receiver of the analog signal 341 and data signal receiver 342 driving display chip 34 inside; Described video-out port 803 is connected with driving the data logger 3410 of display chip inside.

Refer to Figure 60, it is the partial enlarged drawing of the power port driving display chip.Described power port 801 comprises the power pins of a 1.2V and the power pins of 3.3V; Described 1.2V pin is circumscribed with two electric capacity in parallel, for filtering AC signal; Described 3.3V is circumscribed with 5 shunt capacitances, for filtering the AC signal of different frequency.

Refer to Figure 61, it is the partial enlarged drawing of the video input port driving display chip.Described video input port 802 comprises two groups of pins, and record the recording signal of circuit for receiving for one group, another group is for receiving the vision signal play in real time.Wherein, pin B5 ~ B8, A5 ~ A8 record the recording signal of circuit for receiving, and pin B1 ~ B4, A1 ~ A4 are for receiving the vision signal play in real time.

Refer to Figure 62, it is the partial enlarged drawing of the video-out port driving display chip.Described video-out port 803 comprises 12 groups of pins, is connected respectively with data logger 3410, for exporting playback video signal and real time video signals.

Refer to Figure 63, it is the internal circuit connection diagram of video record chip.

The video record chip 35 of described main frame inside comprises: data sink 351, image processor 352, video encoder 353, Video Decoder 354, data logger 355 and processor 356;

Described data sink 351, for receiving outside vision signal, and is sent to image processor 352;

Described image processor 352, the video sent for receiving data sink carries out, and processes video image, then is sent to video encoder 353; Wherein, described image processor comprises the edge intensifier circuit of the definition for strengthening image border and the interfered circuit that abates the noise for erasure signal interference.

Described video encoder 353, for recording encoding video signal;

Described Video Decoder 354, for decoding video signal playback;

Described data logger 355, for exporting vision signal;

Described processor 356, for the work of control data receiver 351, image processor 352, video encoder 353, Video Decoder 354 and data logger 355.

Refer to Figure 64-66, it is the outside port connection diagram of video record chip.

Further, described video record chip exterior is provided with: power port 901, video input port 902, video-out port 903 and PORT COM 904; Described video input port 902 is connected with the data sink 351 of this video chip inside, for receiving outside video data; Described video-out port 903, is connected with described data logger 355, for output video data; Described PORT COM 904, is connected with described processor 356, for receiving outside serial port command.

Refer to Figure 67, it is the partial enlarged drawing of power port.Described power port 901 is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at least one electric capacity; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected between magnetic bead and electric capacity.

Refer to Figure 68, it is the partial enlarged drawing of PORT COM.Described PORT COM 904 includes two pins, carries out communication as serial ports and external command.By the mode of serial communication, the data wire of use is few, can save communications cost.

The utility model is not limited to above-mentioned execution mode, if do not depart from spirit and scope of the present utility model to various change of the present utility model or distortion, if these are changed and distortion belongs within claim of the present utility model and equivalent technologies scope, then the utility model is also intended to comprise these changes and distortion.

Claims

1. a medical camera system, is characterized in that: comprise and be arranged on sky hanging camera lens above operating table, be arranged on the submersible type camera lens implementing surgery location, and for the main frame of the vision signal that receives day hanging camera lens and submersible type camera lens;

2. medical camera system according to claim 1, is characterized in that: be provided with the first signal conversion chip and secondary signal conversion chip in described sky hanging camera lens; The video signal of described sky hanging camera lens collection is LVDS signal; Described first signal conversion chip, it is connected with picture processing chip, and this LVDS signal is converted to BT1120 signal, and this BT1120 signal is sent to secondary signal conversion chip; BT1120 signal is converted to sdi signal by described secondary signal conversion chip, and is sent in main frame; Described main frame inside is provided with the 3rd signal conversion chip, for sdi signal is converted to BT1120 signal; The video signal of described submersible type camera lens collection is CVBS signal; Described main frame inside is provided with the 4th signal conversion chip, for this CVBS signal is converted to BT656 signal.

3. medical camera system according to claim 2, is characterized in that: described first signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;

Described data logger, for exporting BT1120 video signal data;

Described secondary signal conversion chip comprises: data buffer, low noise phase-locked loop, ASI synchronization encoders, serializer, serial image scrambler, cable driver and end noise phase-locked loop;

Described cable driver, for being sent to main frame by this sdi signal;

Described 3rd signal conversion chip comprises: cable equalizer, data recoverer, crystal oscillator, serial image descrambler, deserializer, ASI sync decoder, data extractor and data buffer;

Described data buffer, for sending the signal of reception;

Described 4th signal conversion chip comprises: the contrast saturation control circuit of the data amplitude limiter of analog to digital converter, analog controller, many standards, data bypass sampling filter, colourity and brightness, synchronous circuit, clock generator and formatted output device;

4. medical camera system according to Claims 2 or 3, it is characterized in that: described main frame inside is also provided with an image enhaucament chip, for receiving the vision signal of day hanging camera lens and submersible type camera lens, and carry out enhancing process, then be sent to video record chip respectively and drive display chip.

5. medical camera system according to claim 1, is characterized in that: the video capture processor of described sky hanging camera lens and submersible type camera lens inside all comprises: control module, driver module, illuminant module, sampling module, output module and doubly frequency module;

Described output module, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side;

Described times of frequency module, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to control module.

6. medical camera system according to claim 5, is characterized in that: described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal.

7. medical camera system according to claim 1, is characterized in that: the picture processing chip of described sky hanging camera lens and submersible type camera lens inside all comprises: data sink, master controller, image processor, data logger and frequency multiplier;

Described data sink, it is for receiving outside view data;

Described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit and exposure gain circuit, described white balance permanent circuit, for according to the parameter preset, carries out the fixed adjustment of white balance; Described exposure gain circuit, for increasing exposure gain size.

Described data logger, it is for exporting the view data after process;

Described frequency multiplier, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller.

8. medical camera system according to claim 7, is characterized in that: described image processor also comprises an optical detection and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.

9. medical camera system according to claim 8, is characterized in that: described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, for receive store data data receiver port and for receiving the PORT COM of external communication order.

10. medical camera system according to claim 1, is characterized in that: the video record chip of described main frame inside comprises: data sink, video encoder, Video Decoder, data logger, processor and image processor;

Described video encoder, for recording encoding video signal;

Described Video Decoder, for decoding video signal playback;

Described data logger, for exporting vision signal;

Described processor, for the work of control data receiver, video encoder, Video Decoder and data logger;

Described image processor, processes for the video received data sink, and the image after process is sent to video encoder.

11. medical camera systems according to claim 10, is characterized in that: described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM; Described video input port is connected with the data sink of this center processing chip internal, for receiving outside video data; Described video-out port, is connected with described data logger, for output video data; Described PORT COM, is connected with described processor, for receiving outside serial port command.

12. medical camera systems according to claim 1, is characterized in that: the driving display chip of described main frame inside comprises: receiver of the analog signal, digit signal receiver, analog to digital converter, multiplexer, output format transducer, data logger, controller, Video Decoder, field flyback data processor, memory and image border smoothing processor;

Described data logger, exports signal, and shows; Described data logger carries out color simultaneously and exports and the output of LVDS vision signal;

Described controller, for the work of control simulation signal receiver, digit signal receiver, analog to digital converter, multiplexer, output format transducer and data logger;

Described memory, for storing the data after field flyback data processor processes, and is sent to output format transducer.Described driving display chip also comprises an image border smoothing processor, for receiving the signal of restorer, and to the smoothing process in the edge of video image, then is sent to format converter.

13., according to camera system medical described in claim 12, is characterized in that: the outside of described driving display chip is provided with: power port, video reception port and VT mouth; Receiver of the analog signal and the data signal receiver of described video reception port and center processing chip internal are connected; Described video-out port is connected with the data logger of center processing chip internal.