CN105007400B - Video acquisition process, video record and the display circuit of a kind of medical endoscope - Google Patents

Video acquisition process, video record and the display circuit of a kind of medical endoscope Download PDF

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CN105007400B
CN105007400B CN201510385620.6A CN201510385620A CN105007400B CN 105007400 B CN105007400 B CN 105007400B CN 201510385620 A CN201510385620 A CN 201510385620A CN 105007400 B CN105007400 B CN 105007400B
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video
data
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CN105007400A (en
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陈锦棋
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Guangdong Softlink Medical Innovation Co Ltd
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Guangdong Softlink Medical Innovation Co Ltd
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Abstract

The present invention relates to video acquisition process, video record and the display circuit of a kind of medical endoscope, including video capture processor, picture processing chip, signal conversion chip, image enhaucament chip, video record chip and display driver chip；Video data transmitting after described video capture processor will gather is delivered to picture processing chip and is processed；Described signal conversion chip includes the first signal conversion chip and secondary signal conversion chip；Picture signal after described picture processing chip will process sends to the first signal conversion chip, and is sent to secondary signal conversion chip by this first signal conversion chip；Described secondary signal conversion chip sends to image enhaucament chip after being changed by signal；The video image of reception is carried out enhancing process by described image enhaucament chip, and is simultaneously sent to video record chip and display driver chip, this video record chip record, this display driver chip play in real time.

Description

Video acquisition process, video record and the display circuit of a kind of medical endoscope
Technical field
The present invention relates to a kind of video capture circuit, a kind of video acquisition for medical endoscope processes, video record And display circuit.
Background technology
Endoscope is a kind of conventional medicine equipment, is made up of bendable portion, light source and one group of camera lens.Natural hole through human body Road, or the little otch that does of underwent operative enters in human body, endoscope imports during use the organ of preliminary examination, can directly spy on Change about position.
Wherein, the quality of picture quality directly affects the using effect of endoscope.The existing fujinon electronic video endoscope that generally uses is carried out Observe.Common fujinon electronic video endoscope uses the electronic imaging element CCD (charge-coupled image sensor) that size is minimum, will observe Chamber in object be imaged onto on CCD by small objective lens optical system, then by leading as the image that receive is believed by fibre bundle Number deliver on image processing system, the image after output processes the most on a monitor, observe for doctor and diagnosis.But, existing Some CCD chip yet suffer from the defect that power consumption is too high, image quality is the most clear.
Meanwhile, the existing fujinon electronic video endoscope that generally uses is observed, and the image after observing sends to the process of external connection System carries out image procossing.But, during owing to carrying out IMAQ in human body, understand due to a variety of causes of inside of human body, and Cause occurring that noise jamming, brightness cannot be automatically adjusted or cause due to the color of light image aberration occur, so cause In the image procossing in later stage, it is difficult to reduce real image, doctor is made to be difficult to recognize when observing.
Summary of the invention
The invention reside in the shortcoming overcoming prior art with not enough, it is provided that a kind of high definition, low-power consumption, the medical endoscope of low-light (level) Video acquisition process, video record and display circuit.
The present invention is achieved through the following technical solutions: video acquisition process, video record and the display circuit of a kind of medical endoscope, Drive including video capture processor, picture processing chip, signal conversion chip, image enhaucament chip, video record chip and display Dynamic chip；
Video data transmitting after described video capture processor will gather is delivered to picture processing chip and is processed；
Described signal conversion chip includes the first signal conversion chip and secondary signal conversion chip；Described first signal conversion chip For bt1120 signal is converted to lvds signal；Described secondary signal conversion chip is for being converted to bt1120 by lvds signal Signal；
Picture signal after described picture processing chip will process sends to the first signal conversion chip, and is changed by this first signal Chip sends to secondary signal conversion chip；Described secondary signal conversion chip sends to image enhaucament chip after being changed by signal；
The video image of reception is carried out enhancing process by described image enhaucament chip, and is simultaneously sent to video record chip and display Driving chip, is recorded by this video record chip, this display driver chip plays in real time；
After described video record chip completes video record, send to display driver chip, carry out video playback.
Compared to prior art, the image gathered, by increasing by a picture processing chip in camera lens part, is processed by the present invention, Main frame backstage increases an image enhaucament chip, carries out level image enhancing, make the image finally exported become apparent from.
First, picture processing chip is divided into multiple functional module, distinguishes and by each functional module independence co-ordination, It is capable of low-power consumption, low-light (level), and can be the picture more high definition of output.Meanwhile, further at this image processor In a white balance permanent circuit is set, for being fixed by this white balance parameter, it is not necessary to operationally carry out the regulation of white balance, Thus prevent the phenomenon of aberration interference.
Then, image enhaucament chip is also divided into multiple functional module, distinguishes and by each functional module independence co-ordination, It is capable of the enhancing to image to process.Meanwhile, an image border intensifier circuit is set further in this image intensifier, uses To strengthen the definition of image border.
It addition, in order to improve signal transmission stability, the present invention by first bt1120 signal being converted to lvds signal, thus Stable transmission, and there is low noise ability.Then, it is being bt1120 signal by lvds signals revivification, thus ensure that follow-up The quality of the picture play.
As a further improvement on the present invention, include inside described video capture processor: controller, driver, photoreceptor, take Sample device and follower；
Described controller, it sends trigger signal to driver for receiving the triggering signal of outside；
Described driver, it is for receiving the triggering signal of controller, and drives photoreceptor to work；
Described photoreceptor, it is for receiving the optical signal in the external world, and this optical signal is converted to the signal of telecommunication；
Described sampler, it is for being sampled processing to the signal of telecommunication of photoreceptor, and is sent extremely by the signal of telecommunication processed Follower；
Described follower, it for being converted to data signal by this signal of telecommunication, and carries out exporting picture processing chip；
Described picture processing chip includes: data sink, master controller, image processor, data logger；
Described data sink, it is for receiving the view data of outside；
Described master controller, it is for receiving the triggering signal of outside, and controls described data sink, image accordingly Processor and the duty of data logger；
Described image processor, it is for processing image；Described image processor includes a white balance permanent circuit, It is for according to the parameter preset, carrying out the fixed adjustment of white balance；
Described data logger, its view data after processing exports；
Described first signal conversion chip includes: controller, data reader, signal format converter, serializer, data are defeated Go out device；
Described controller, its for receive outside triggering signal, and control data reader, signal format converter, Serializer and the work of data logger；
Described data reader, it transmits signal for the bt1120 receiving outside, and sends to signal format converter；
Described signal format converter, it for being converted to the vision signal of lvds by bt1120 vision signal, and sends extremely Serializer；
Described serializer, it is used for converting parallel data into serial data, and sends to data logger；
Described data logger, for exporting lvds signal data to secondary signal conversion chip；
Described secondary signal conversion chip includes: controller, data reader, signal format converter, deserializer, number According to follower；
Described controller, its for receive outside triggering signal, and control data reader, signal format converter, Deserializer and the work of data logger；
Described data reader, it is for the lvds video transfer signal of the first signal conversion chip, and sends to signal lattice Formula converter；
Described signal format converter, it for being converted to the vision signal of bt1120 by lvds vision signal, and sends extremely Deserializer；
Described deserializer, it is used for converting serial data into parallel data, and sends to data logger；
Described data logger, for exporting bt1120 video signal data；
Described image enhaucament chip includes: data sink, controller, static memory, image intensifier, data are defeated Go out device and clock generator；
Described data sink, it is used for receiving viewdata signal, and sends to this image intensifier；
Described controller, it is used for receiving outer triggering signal, and controls data sink, its sum of image enhaucament accordingly Duty according to follower；
Described static memory, it is for storing the driving data of image intensifier, to drive the work of this image intensifier；
Described image intensifier, it includes an image border intensifier circuit；Described image border intensifier circuit is used for strengthening figure Definition as edge；
Described data logger, it is for receiving the view data after image intensifier processes, and carries out data output；
Described clock generator, it is for producing clock signal for image enhaucament chip；
Described video record chip includes: data sink, video encoder, Video Decoder, data logger and processor；
Described data sink, for receiving the vision signal of outside, and sends to video encoder；
Described video encoder, for recording encoding video signal；
Described Video Decoder, for playing back decoding video signal；
Described data logger, for exporting vision signal；
Described processor, for controlling the work of data sink, video encoder, Video Decoder and data logger；
Described display driver chip includes: receiver of the analog signal, digit signal receiver, analog-digital converter, multiplexer, defeated Go out format converter, data logger and controller；
Described receiver of the analog signal, is used for receiving analog signal, and sends to analog-digital converter；
Described analog-digital converter, is used for converting analog signals into data-signal, and sends to multiplexer；
Described data signal receiver, is used for receiving data-signal, and sends to multiplexer；
Described multiplexer, for being integrated by two paths of signals, and carries out exporting to output format converter；
Described output format converter, for signal format being changed, and exports to data logger；
Described data logger, exports signal, and shows；
Described controller, be used for controlling receiver of the analog signal, digit signal receiver, analog-digital converter, multiplexer, Output format converter and the work of data logger.
As a further improvement on the present invention, described video capture processor also includes a frequency multiplier, and it is for touching of being inputted outside The frequency signaled carries out doubling process, retransmits to controller；
Described picture processing chip also includes a frequency multiplier, and it carries out doubling process for the frequency triggering signal inputted outside, Retransmit to master controller；
Described first signal conversion chip also includes a phase-locked loop, being connected with signal format converter and serializer respectively, being used for Unified integration clock signal；
Described secondary signal conversion chip also includes a phase-locked loop, being connected with signal format converter and serializer respectively, being used for Unified integration clock signal；
Described image enhaucament chip also includes a de-noising processor；The viewdata signal that described data sink receives, sends Carry out noise reduction process to de-noising processor, then be forwarded to image intensifier；
Described video record chip also includes an image processor, processes for the video being received data sink, and Image after processing sends to video encoder；
Described display driver chip also includes a Video Decoder, field flyback data processor and memory；
Described Video Decoder, for the analog signal that receiver of the analog signal receives being decoded, and sends to field flyback number According to processor；
Described field flyback data processor, for decoded analog signal is inserted data row, and transmission to described memory enters Row storage；
Described memory, for storage data after field flyback data processor processes, and sends to output format converter.
As a further improvement on the present invention, the image processor in described picture processing chip also includes an exposure gain circuit, For increasing exposure gain size；
Described first signal conversion chip also includes a clock data restorer, and it is connected with data reader, for from transmission letter The distortion in road and noise recover data；
Described secondary signal conversion chip also includes a clock data restorer, and it is connected with data reader, for from transmission letter The distortion in road and noise recover data；
Described image enhaucament chip also includes a dynamic memory；Described de-noising processor process after view data, first send to Dynamic memory stores, then is forwarded to image intensifier；
The image processor of described video record chip includes edge intensifier circuit and the interference circuit that abates the noise；
Described display driver chip also includes an image border smoothing processor, for receiving the signal of restorer, and to video figure The edge of picture is smoothed, and retransmits to format converter.
As a further improvement on the present invention, described image processor also includes an optical detection circuit and flash detection circuit, its For brightness and the flashing state of detection image, and result of detection is sent to exposure gain circuit；
Described image enhaucament chip also includes a pixel self adaptation proofreading equipment；Described image intensifier first will process after view data Send to described pixel self adaptation proofreading equipment, this pixel self adaptation proofreading equipment carry out pixel and adapt to check and correction, retransmit to data defeated Go out device.
As a further improvement on the present invention, be provided with outside described video capture processor: for receive supply voltage power port, For exporting the video signal port of vision signal, for exporting the row field signal port of row field signal, for receiving reference voltage The reference signal port of electricity frequency and one is for receiving the clock signal port of external timing signal；
It is provided with outside described picture processing chip: for receiving the power port of supply voltage, for receiving the signal of picture signal Receiving port, for exporting the video signal port of vision signal, for exporting the row field signal port of row field signal, being used for connecing Receive the clock signal port of external timing signal, for receiving the data receiver port and of storage data for receiving external communication The PORT COM of order；
It is provided with outside described first signal conversion chip: described center processing chip exterior is provided with: for receiving the electricity of supply voltage Source port, for receiving the receiver port of bt1120 vision signal, for exporting the video signal port of lvds vision signal With the row field signal port for exporting row field signal；
It is provided with outside described secondary signal conversion chip: described center processing chip exterior is provided with: be used for receiving supply voltage Power port, for receiving the receiver port of lvds vision signal and for exporting the vision signal of bt1120 vision signal Port；
Described image enhaucament chip exterior is provided with: for receiving the power port of supply voltage, for receiving the signal of picture signal Receiving port, for exporting the video signal port of vision signal, for exporting the row field signal port of row field signal, being used for connecing Receive the clock signal port of external timing signal and for receiving the data receiver port of storage data；
Described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM；Institute State video input port to be connected with the data sink of this video record chip internal, for receiving the video data of outside；Described Video-out port, is connected with described data logger, is used for exporting video data；Described PORT COM, with described processor Connect, for receiving the serial port command of outside；
It is provided with outside described display driver chip: power port, video input port, video-out port and PORT COM；Institute State video input port to be connected with the data sink of this video record chip internal, for receiving the video data of outside；Described Video-out port, is connected with described data logger, is used for exporting video data；Described PORT COM, with described processor Connect, for receiving the serial port command of outside.
As a further improvement on the present invention, the power port of described video capture processor is circumscribed with one for the filter circuit of voltage stabilizing； Described filter circuit includes an inductance and at least one electric capacity；Described inductance one end is connected with external power source, the other end respectively with Each electric capacity connects, the other end of described each electric capacity and ground connection；Power port is accessed in one end that described inductance is connected with electric capacity；
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing；Described filter circuit includes an electricity Sense and at least one electric capacity；Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, described each The other end of electric capacity and ground connection；Power port is accessed in one end that described inductance is connected with electric capacity；
The power port of described video record chip is circumscribed with a filter circuit；Described filter circuit include a magnetic bead and at least one Electric capacity；Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity；Described power port is connected to magnetic bead and electricity Between appearance；
Described display driver chip power port is circumscribed with a filter circuit；Described filter circuit includes a magnetic bead and at least one electricity Hold；Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity；Described power port is connected to magnetic bead and electric capacity Between.
As a further improvement on the present invention, the row field signal port of described video capture processor is circumscribed with one for providing signal strong The resistance of degree.
As a further improvement on the present invention, the reference signal port of described video capture processor is circumscribed with as the frequency reference of voltage electricity The electric capacity of benchmark.
As a further improvement on the present invention, the external clock circuit of clock signal port of described video capture processor, it includes One clock shakes chip；The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock passes through One debugging circuit is connected with described clock signal port；Described filter circuit includes being made up of an inductance and capacitances in series, described electricity One end of sense is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity；Described clock shakes the power end of chip Be connected between inductance and electric capacity；Described debugging electricity routing resistance and electric capacity composition；One end of the resistance of this debugging circuit and clock The output shaken connects, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity；Described clock signal port is connected to this Between resistance and electric capacity；
The described external clock circuit of picture processing chip clock signal port, it includes that a clock shakes chip；Described clock shakes chip Power end is connected with power supply by a filter circuit, and the shake output of chip of this clock debugs circuit and described clock signal terminal by one Mouth connects；Described filter circuit includes being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, the other end It is connected with electric capacity, and the other end ground connection of this electric capacity；Described clock shake chip power end be connected between inductance and electric capacity；Institute State debugging electricity routing resistance and electric capacity composition；One end of the resistance of this debugging circuit is connected with the output of Zhong Zhen, the other end and electricity Hold and connect, and the other end ground connection of this electric capacity；Described clock signal port is connected between this resistance and electric capacity；
The external clock circuit of clock signal port of described image enhaucament chip, it includes that a clock shakes chip；Described clock shakes chip Power end be connected with power supply by a filter circuit, the shake output of chip of this clock is connected with described clock signal port；Described Filter circuit includes being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, And the other end ground connection of this electric capacity.
In order to be more fully understood that and implement, describe the present invention below in conjunction with the accompanying drawings in detail.
Accompanying drawing explanation
Fig. 1 is the chip connection diagram of the present invention.
Fig. 2 is the internal module connection diagram of video capture processor.
Fig. 3 is that the outside port of video capture processor connects circuit diagram.
Fig. 4 is the circuit diagram of the power unit connection of video capture processor.
The voltage of the 2.7V of Fig. 5 video capture processor accesses circuit diagram.
Fig. 6 is that the voltage of the 1.8V of video capture processor accesses circuit diagram.
Fig. 7 is that the voltage of the 1.2V of video capture processor accesses circuit diagram.
Fig. 8 is the partial enlarged drawing of the row field signal of video capture processor.
Fig. 9 is the partial enlarged drawing of the reference signal port of video capture processor.
Figure 10 is the circuit diagram of the clock circuit of video capture processor.
Figure 11 is the circuit diagram of the configuration circuit of video capture processor.
Figure 12 is the internal module connection diagram of picture processing chip.
Figure 13 is the circuit module schematic diagram of the image processor of picture processing chip.
Figure 14 is the voltage segment circuit diagram of picture processing chip.
Figure 15 is the outside port circuit diagram of picture processing chip.
Figure 16 is the circuit diagram of the filter circuit of the 3.3V voltage of picture processing chip.
Figure 17 is the circuit diagram of the filter circuit of the 1.8V voltage of picture processing chip.
Figure 18 is the circuit diagram of the filter circuit of the 1.2V voltage of picture processing chip.
Figure 19 is the partial enlarged drawing of the receiver port of picture processing chip.
Figure 20 is the partial enlarged drawing of the video signal port of picture processing chip.
Figure 21 is the partial enlarged drawing of the row field signal port of picture processing chip.
Figure 22 is the schematic diagram of the clock circuit of picture processing chip.
Figure 23 is the schematic diagram of the storage circuit of picture processing chip.
Figure 24 is the partial enlarged drawing of the PORT COM of picture processing chip.
Figure 25 is the internal components connection diagram of the first signal conversion chip.
Figure 26 is the internal module connection diagram of secondary signal conversion chip.
Figure 27 is the outside port connection diagram of the first signal conversion chip.
Figure 28 is the close-up schematic view of the power port of the first signal conversion chip.
Figure 29 is the partial enlarged drawing of the receiver port of the first signal conversion chip.
Figure 30 is the partial enlarged drawing of the video signal port of the first signal conversion chip.
Figure 31 is the partial enlarged drawing of the row field signal port of the first signal conversion chip.
Figure 32 is the external connection circuit diagram of secondary signal conversion chip.
Figure 33 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.
Figure 34 is the partial enlarged drawing of the video signal port of secondary signal conversion chip.
Figure 35 is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.
Figure 36 is the internal module connection diagram of image enhaucament chip.
Figure 37 is the Part I external connection circuit diagram of image enhaucament chip.
Figure 38 is the Part II external connection circuit diagram of image enhaucament chip.
Figure 39 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltage of image enhaucament chip.
Figure 40 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.8V.
Figure 41 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.2V.
Figure 42 is the partial enlarged drawing of the receiver port of image enhaucament chip.
Figure 43 a is the partial enlarged drawing of the video signal port Part I of image enhaucament chip.
Figure 43 b is the partial enlarged drawing of the video signal port Part II of image enhaucament chip.
Figure 44 is the circuit diagram of the clock circuit of image enhaucament chip.
Figure 45 is the partial enlarged drawing of the row field signal port of image enhaucament chip.
Figure 46 is the internal components connection diagram of video record chip.
Figure 47 is the video input circuit figure of video record chip.
Figure 48 is the video output circuit figure of video record chip.
Figure 49 is video record chip and communication input circuit figure.
Figure 50 is the partial enlarged drawing of the power port of video record chip.
Figure 51 is the partial enlarged drawing of the PORT COM of video record chip.
Figure 52 is the internal components connection diagram of display driver chip.
Figure 53 is the external signal input circuit figure of display driver chip.
Figure 54 is the external signal output circuit figure of display driver chip.
Figure 55 is the partial enlarged drawing of the power port of display driver chip.
Figure 56 is the partial enlarged drawing of the video input port of display driver chip.
Figure 57 is the partial enlarged drawing of the video-out port of display driver chip.
Detailed description of the invention
Referring to Fig. 1, it is the chip connection diagram of invention.The invention provides at the video acquisition of a kind of medical endoscope Reason, video record and display circuit, including video capture processor 10, picture processing chip 20, signal conversion chip 30 and figure Image intensifying chip 40.
Video data transmitting after described video capture processor 10 will gather is delivered to picture processing chip 20 and is processed；Described signal Conversion chip 30 includes the first signal conversion chip 31 and secondary signal conversion chip 32；
Described first signal conversion chip 31 is for being converted to lvds signal by bt1120 signal；Described secondary signal conversion chip 32 for being converted to bt1120 signal by lvds signal；
Picture signal after described picture processing chip 20 will process sends to the first signal conversion chip 31, and first is believed by this Number conversion chip 31 sends to secondary signal conversion chip 32；Described secondary signal conversion chip 32 by signal change after send to Image enhaucament chip 40.
Referring to Fig. 2, it is the internal module connection diagram of video capture processor.Described video capture processor 10 is internal to be included: Controller 11, driver 12, photoreceptor 13, sampler 14, follower 15 and frequency multiplier 16；
Described controller 11, it sends trigger signal to driver for receiving the triggering signal of outside；
Described driver 12, it is for receiving the triggering signal of controller, and drives photoreceptor to work；
Described photoreceptor 13, it is for receiving the optical signal in the external world, and this optical signal is converted to the signal of telecommunication；
Described sampler 14, it is for being sampled processing to the signal of telecommunication of photoreceptor, and sends the signal of telecommunication processed to defeated Go out device；
Described follower 15, it is for being converted to data signal by this signal of telecommunication, and exports.
Described frequency multiplier 16, it carries out doubling process for the frequency triggering signal inputted outside, retransmits to controller. Further, for convenience in the requirement of use frequency of video capture processor, the regulation being realized frequency by frequency multiplier is amplified.
Please refer to Fig. 3, it is the outside port circuit diagram of video capture processor.In addition to adapt to this video capture processor Application, be provided with outside described video capture processor: for receiving the power port 101 of voltage, for exporting vision signal Video signal port 102, for export row field signal row field signal port 103, for receive reference voltage electricity frequency reference Signal port 104, for receiving the clock signal port 105 of external timing signal and for receiving outside mode of operation order Communication command port 106.
Please refer to Fig. 4, it is the circuit diagram of power unit of video capture processor.Concrete, in video capture processor Power unit uses three kinds of voltages, respectively 2.7V, 1.8V, and 1.2V simultaneously.
Please refer to Fig. 5-7, it is respectively the circuit diagram of 2.7V, 1.8V and 1.2V of video capture processor.Concrete, depending on Frequently the input port 101 of three kinds of voltages of acquisition chip is all circumscribed with one for the filter circuit of voltage stabilizing；Described filter circuit includes One inductance and at least one electric capacity；Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, institute State the other end and the ground connection of each electric capacity；Power port is accessed in one end that described inductance is connected with electric capacity.Wherein, 2.7V and 1.8V Voltage access circuit and include four electric capacity, the voltage of 1.2V accesses circuit and includes three electric capacity, to filter the interference of different frequency Signal.
Referring to Fig. 8, it is the interface enlarged drawing of row field signal.Further, described row field signal port 103 is circumscribed with a use In the resistance providing signal strength signal intensity.By this row field signal, for controlling frequency and the order of video frequency output.Such as: can control The vision signal processed display frequency on screen and DISPLAY ORDER, can be often row output under upper, it is also possible to be from left to right Output.
Referring to Fig. 9, it is the partial enlarged drawing of reference signal port of video capture processor.Further, described reference signal Port 104 is circumscribed with the electric capacity as voltage electricity frequency reference data.In the present embodiment, described reference signal port has 7, The electric capacity of the external 1uF of each port.
Referring to Figure 10, it is the circuit diagram of clock circuit of video capture processor.Described clock signal port 105 external a period of time Clock circuit, it includes that a clock shakes chip；The shake power end of chip of described clock is connected with power supply by a filter circuit, this Zhong Zhenxin The output of sheet is connected with described clock signal port by a debugging circuit；Described filter circuit includes by an inductance and electric capacity string Joint group becomes, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity；Described clock Shake chip power end be connected between inductance and electric capacity；Described debugging electricity routing resistance and electric capacity composition；This debugging circuit One end of resistance is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity；Described clock is believed Number port is connected between this resistance and electric capacity.
Referring to Figure 11, it is the circuit diagram configuring circuit of video capture processor.Further, described communication command port 106, It is circumscribed with a mode of operation configuration circuit；Described configuration circuit is made up of two resistant series, and described communication command port connects Between two resistance.
Referring to Figure 12, it is the internal module connection diagram of picture processing chip.Described picture processing chip 20 includes: Data sink 21, master controller 22, image processor 23, data logger 24.
Described data sink 21, it is for receiving the view data of outside；
Described master controller 22, it is for receiving the triggering signal of outside, and controls accordingly at described data sink, image Reason device and the duty of data logger；
Described image processor 23, it is for processing image.
Described data logger 24, its view data after processing exports.
Further, described video capture processor also includes a frequency multiplier 25, and it enters for the frequency triggering signal inputted outside Row doubles process, retransmits to master controller 22.
Referring to Figure 13, it is the circuit module schematic diagram of image processor of picture processing chip.Concrete, at described image Reason device 23 includes a Lens Shading Compensation circuit 231, optical detection circuit 232, flash detection circuit 233, exposure gain electricity Road 234 and white balance permanent circuit 235.
Described Lens Shading Compensation circuit 231, it is for compensating process by the shade that camera lens produces.
Described optical detection circuit 232 and flash detection circuit 233, its brightness being used for detection image and flashing state, and will Result of detection sends to exposure gain circuit.
Described exposure gain circuit 234, is used for increasing exposure gain size.
Described white balance permanent circuit 235, it is for according to the parameter preset, carrying out the fixed adjustment of white balance.
Please refer to Figure 14 and Figure 15, its be respectively the voltage segment of video capture processor of picture processing chip and other outside Portion's port circuit figure.It addition, for the application in order to adapt to this video capture processor, further outside described video capture processor Portion is provided with: for receiving the power port 201 of supply voltage, for receiving the receiver port 202 of picture signal, for defeated Go out the video signal port 203 of vision signal, for exporting the row field signal port 204 of row field signal, for receiving external clock The clock signal port 205 of signal, for receiving the data receiver port 206 and of storage data for receiving external communication life The PORT COM 207 of order.
Referring to Figure 16-18, it is respectively the circuit diagram that power supply is 3.3V, 1.8V and 1.2V of picture processing chip.Further, Described power port 201 is circumscribed with one for the filter circuit of voltage stabilizing；Described filter circuit includes an inductance and at least one electricity Hold；Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity with Ground connection；Power port is accessed in one end that described inductance is connected with electric capacity.Concrete, the external electricity of the video capture processor of the present invention Pressure includes: 3.3V, 1.8V and 1.2V tri-kinds.Wherein, 3.3V voltage accesses circuit and includes 2 electric capacity, and 1.8V voltage accesses Circuit includes 5 electric capacity, and the voltage of 1.2V accesses circuit and includes 6 electric capacity, to filter the interference signal of different frequency respectively.
Referring to Figure 19, it is the partial enlarged drawing of receiver port of picture processing chip.Described receiver port 202 Including 8 pins, for receiving the video signal of outside.
Referring to Figure 20, it is the partial enlarged drawing of video signal port of picture processing chip.Described video signal port 203 Including the vision signal of two groups of different-formats, carry out doubleway output, play the most in real time to facilitate and record.
Referring to Figure 21, it is the partial enlarged drawing of row field signal port of picture processing chip.Described row field signal port 204 For controlling frequency and the order of video frequency output.Such as: vision signal display frequency on screen and DISPLAY ORDER can be controlled, Can be often row output under upper, it is also possible to be to export from left to right.
Referring to Figure 22, it is the schematic diagram of clock circuit of picture processing chip.Described clock signal port 205 external a period of time Clock circuit, it includes that a clock shakes chip；The shake power end of chip of described clock is connected with power supply by a filter circuit, this Zhong Zhenxin The output of sheet is connected with described clock signal port by a debugging circuit；Described filter circuit includes by an inductance and electric capacity string Joint group becomes, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity；Described clock Shake chip power end be connected between inductance and electric capacity；Described debugging electricity routing resistance and electric capacity composition；This debugging circuit One end of resistance is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity；Described clock is believed Number port is connected between this resistance and electric capacity.
Referring to Figure 23, it is the schematic diagram storing circuit of picture processing chip.Further, described data receiver port 206 Being circumscribed with a memory circuitry, it includes a memory, is connected to the filter circuit of the voltage port of this memory, and connects Resistance at the output port of this memory.
Referring to Figure 24, it is the partial enlarged drawing of PORT COM of picture processing chip.Described PORT COM 207 is used for receiving The trigger command of external transmission, to trigger being operated of this picture processing chip.
Referring to Figure 25, it is the internal components connection diagram of the first signal conversion chip.Described first signal conversion chip 31 Including: controller 311, data reader 312, signal format converter 313, serializer 314, data logger 315, Phase-locked loop 316 and clock data restorer 317；
Described controller 311, it is for receiving the triggering signal of outside, and controls data reader 312, signal format converter 313, serializer 314 and the work of data logger 315；
Described data reader 312, it transmits signal for the bt1120 receiving outside, and sends to signal format converter；
Described signal format converter 313, it for being converted to the vision signal of lvds by bt1120 vision signal, and sends extremely Serializer；
Described serializer 314, it is used for converting parallel data into serial data, and sends to data logger；
Described data logger 315, for exporting lvds signal data to secondary signal conversion chip.
Described phase-locked loop 316, is connected with signal format converter and serializer respectively, for unified integration clock signal.
Described clock data restorer 317, it is connected with data reader, for recovering from the distortion and noise of transmission channel Data.
Referring to Figure 26, it is the internal module connection diagram of secondary signal conversion chip.Described secondary signal conversion chip 32 Including: controller 321, data reader 322, signal format converter 323, deserializer 324, data logger 325, Phase-locked loop 326 and clock data restorer 327；
Described controller 321, it is for receiving the triggering signal of outside, and controls data reader 322, signal format converter 323, deserializer 324 and the work of data logger 325；
Described data reader 322, it is for the lvds video transfer signal of the first signal conversion chip, and sends to signal lattice Formula converter；
Described signal format converter 323, it for being converted to the vision signal of bt1120 by lvds vision signal, and sends extremely Deserializer 324；
Described deserializer 324, it is used for converting serial data into parallel data, and sends to data logger；
Described data logger 325, for exporting bt1120 video signal data.
Described phase-locked loop 326, is connected with signal format converter and deserializer respectively, for unified integration clock signal.
Described clock data restorer 327, it is connected with data reader 222, for from the distortion and noise of transmission channel Recover data.
Referring to Figure 27, it is the outside port connection diagram of the first signal conversion chip.Outside described first signal conversion chip Portion is provided with: described center processing chip exterior is provided with: for receiving the power port 3101 of supply voltage, for receiving bt1120 The receiver port 3102 of vision signal, for exporting the video signal port 3103 of lvds vision signal and for exporting row The row field signal port 3104 of field signal.
Please refer to Figure 28, it is the close-up schematic view of power port of the first signal conversion chip.Described power port The electric capacity for filtering alternating current it is circumscribed with at 3101.
Referring to Figure 29, it is the partial enlarged drawing of receiver port of the first signal conversion chip.Described receiver port 3102, it is connected with described data reader 31；Concrete, this receiver port includes 20 pins, is used for receiving The vision signal of outside bt1120.
Referring to Figure 30, it is the partial enlarged drawing of video signal port of the first signal conversion chip.Described video signal port 3103 include 4 output pins, are used for exporting lvds vision signal, and this video signal port is connected with this data logger.
Referring to Figure 31, it is the partial enlarged drawing of row field signal port of the first signal conversion chip.Described row field signal port 3104 include a line signal output pin and a field signal output pin；Described row field signal port 3104 is used for controlling video The frequency of output and order.Such as: vision signal display frequency on screen and DISPLAY ORDER can be controlled, can be from upper Under often row output, it is also possible to be to export from left to right.
Referring to Figure 32, it is the external connection circuit diagram of secondary signal conversion chip.Outside described secondary signal conversion chip Portion is provided with: for receiving the receiver port 3201 of lvds vision signal, for exporting the video letter of bt1120 vision signal Number port 3202 and row field signal port 3203.
Referring to Figure 33, it is the partial enlarged drawing of receiver port of secondary signal conversion chip.Described receiver port 3201, it is connected with described data reader 321；Concrete, this receiver port includes 4 pins, is used for receiving The lvds vision signal of the first signal conversion chip output.
Referring to Figure 34, it is the partial enlarged drawing of video signal port of secondary signal conversion chip.Described video signal port 3202 include 20 output pins, are used for exporting bt1120 vision signal, and this video signal port and this data logger Connect.
Referring to Figure 35, it is the partial enlarged drawing of row field signal port of secondary signal conversion chip.Described row field signal port 3203 include a line signal output pin and a field signal output pin；Described row field signal port 3104 is used for controlling video The frequency of output and order.Such as: vision signal display frequency on screen and DISPLAY ORDER can be controlled, can be from upper Under often row output, it is also possible to be to export from left to right.
Referring to Figure 36, it is the internal module connection diagram of image enhaucament chip.Described image enhaucament chip 40 includes: Data sink 41, de-noising processor 42, dynamic memory 43, image intensifier 44, pixel self adaptation proofreading equipment 45, number According to follower 46, static memory 47, controller 48, vision signal multiplier 49, storage signal multiplier 410, clock Generator 411.
Described data sink 41, it is used for receiving viewdata signal, and sends to de-noising processor 42；
The viewdata signal that described data sink 41 receives, transmission to de-noising processor 42 carries out noise reduction process, then turns Send to dynamic memory 43.
Described dynamic memory 43 is after receiving the view data after de-noising processor 22 processes, then is forwarded to image intensifier 44。
Described image intensifier 44, it includes an image border intensifier circuit；Described image border intensifier circuit is used for strengthening image The definition at edge.Further, the view data after described image intensifier first will process sends to the check and correction of described pixel self adaptation Device 45, is carried out pixel by this pixel self adaptation proofreading equipment 45 and adapts to check and correction, retransmit to data logger 46.
Described data logger 46, it is for receiving the view data after image intensifier processes, and carries out data output；
Described static memory 47, it is for storing the driving data of image intensifier, to drive the work of this image intensifier；
Described controller 48, it is used for receiving outer triggering signal, and controls data sink, image enhaucament itself and data accordingly The duty of follower；
Described clock generator 411, it is for producing clock signal for image enhaucament chip.Further, described clock generator, The clock signal of generation is respectively sent to vision signal multiplier 49 and storage signal multiplier 410, and by this vision signal times Increase device 49 to send clock signal to data sink, this storage signal multiplier 410 clock signal is sent to dynamic memory Device and static memory.
Please refer to Figure 37 and Figure 38, it is respectively the external connection circuit diagram of image enhaucament chip.
Further, described image enhaucament chip exterior is provided with: for receiving the power port of supply voltage, for receiving image letter Number receiver port 401, for export vision signal video signal port 402, for receive external timing signal time Clock signal port 403, for exporting the row field signal port 404 of row field signal.
Concrete, in the present embodiment, the external voltage of described power port comprises tri-kinds of voltages of 3.3V, 1.8V and 1.2V. Referring to Figure 39, it is the circuit diagram of filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit includes an inductance and at least One electric capacity；Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, described each electric capacity another One end and ground connection；Power port is accessed in one end that described inductance is connected with electric capacity.
Referring to Figure 40-41, it is respectively 3.3V and is converted to the power-switching circuit figure of 1.8V and 3.3V is converted to turning of 1.2V Change circuit diagram.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is respectively converted into 1.8V's and 1.2V Voltage.Concrete, described power-switching circuit includes a power conversion chip；The input of described power conversion chip accesses 3.3V Voltage, output exports the voltage of 1.8V and 1.2V respectively, to be powered image enhaucament chip.
Referring to Figure 42, it is the partial enlarged drawing of receiver port of image enhaucament chip.Described receiver port 401 Including 20 signal pins, it is connected with internal data sink 41, for receiving the picture signal of input.
Refer to Figure 43 a and 43b, its Part I of video signal port being respectively image enhaucament chip and Part II Partial enlarged drawing.Described video signal port 402 includes 20 signal pins, and it is connected with internal data logger 46, For output image signal.
Referring to Figure 44, it is the circuit diagram of clock circuit of image enhaucament chip.Further, described clock signal port 403 An external clock circuit, it includes that a clock shakes chip；The shake power end of chip of described clock is connected with power supply by a filter circuit, The shake output of chip of this clock is connected with described clock signal port；Described filter circuit includes being made up of an inductance and capacitances in series, One end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Referring to Figure 45, it is the partial enlarged drawing of row field signal port of image enhaucament chip.Described row field signal port 404 Including a row signal pins and a field signal pin.Described row field signal port 404 for control video frequency output frequency and Sequentially.Such as: vision signal display frequency on screen and DISPLAY ORDER can be controlled, can be often row output under upper, Can also be to export from left to right.
Referring to Figure 46, it is the internal components connection diagram of video record chip.Described video record chip includes: data Receiver 51, image processor 52, video encoder 53, Video Decoder 54, data logger 55 and processor 56；
Described data sink 51, for receiving the vision signal of outside, and sends to image processor；
Described image processor 52, the video sent for receiving data sink carries out, and processes video image, then Send to video encoder；Wherein, described image processor includes the edge intensifier circuit of the definition for strengthening image border With the interference circuit that abates the noise for eliminating signal disturbing.
Described video encoder 53, for recording encoding video signal；
Described Video Decoder 54, for playing back decoding video signal；
Described data logger 55, for exporting vision signal；
Described processor 56, is used for controlling data sink 51, image processor 52, video encoder 53, Video Decoder 54 and the work of data logger 55.
Referring to Figure 47-49, it is the video input of video record chip, video frequency output and communication input circuit figure.Further, Described video record chip exterior is provided with: power port 501, video input port 502, video-out port 503 and communication terminal Mouth 504.Described video input port is connected with the data sink of this video record chip internal, for receiving the video of outside Data；Described video-out port, is connected with described data logger, is used for exporting video data；Described PORT COM, with Described processor connects, for receiving the serial port command of outside.
Referring to Figure 50, it is the partial enlarged drawing of power port of video record chip.Described power port 501 is circumscribed with one Filter circuit；Described filter circuit includes a magnetic bead and at least one electric capacity；Described magnetic bead is connected with one end of electric capacity, and this electricity The other end ground connection held；Described power port is connected between magnetic bead and electric capacity.
Referring to Figure 51, it is the partial enlarged drawing of PORT COM of video record chip.Described PORT COM 504 includes two Individual pin, carries out communication as serial ports and external command.By the way of serial communication, the data wire of use is few, can save Communications cost.
Referring to Figure 52, it is the internal components connection diagram of display driver chip.Described display driver chip 60 includes: Receiver of the analog signal 61, digit signal receiver 62, analog-digital converter 63, multiplexer 64, image border smoothing processor 65, Video Decoder 66, field flyback data processor 67, memory 68, output format converter 69, data logger 610 With controller 611.
Described receiver of the analog signal 61, is used for receiving analog signal, and sends to analog-digital converter 63；
Described data signal receiver 62, is used for receiving data-signal, and sends to multiplexer 64；
Described analog-digital converter 63, is used for converting analog signals into data-signal, and sends to multiplexer 64；
Described multiplexer 64, for being integrated by two paths of signals, and carries out output to output image border smoothing processor 65；
Described image border smoothing processor 65, for receiving the signal of restorer, and carries out smooth place to the edge of video image Reason, retransmits to format converter 69.
Described Video Decoder 66, for the analog signal that receiver of the analog signal receives being decoded, and sends to field flyback Data processor 67；
Described field flyback data processor 67, for decoded analog signal is inserted data row, and sends to described memory 68 store；
Described memory 68, for storage data after field flyback data processor processes, and sends to output format converter 69。
Described output format converter 69, for signal format being changed, and exports to data logger 610；
Described data logger 610 carries out color output simultaneously and lvds vision signal exports.
Described controller 611, is used for controlling receiver of the analog signal 61, digit signal receiver 62, analog-digital converter 63, answering With device 64, image border smoothing processor 65, Video Decoder 66, field flyback data processor 67, memory 68, output Format converter 69 and the work of data logger 610.
Refer to Figure 53 and Figure 54, its external signal input circuit figure being respectively display driver chip and signal output apparatus figure. Further, the outside of described display driver chip is provided with: power port 601, video reception port 602 and vision signal Output port 603；Described video reception port 602 and the receiver of the analog signal 61 within display driver chip and data Signal receiver 62 connects；Described video-out port 603 is connected with the data logger 610 within display driver chip.
Referring to Figure 55, it is the partial enlarged drawing of power port of display driver chip.Described power port 601 includes one The power pins of 1.2V and the power pins of 3.3V；Described 1.2V pin is circumscribed with two electric capacity in parallel, is used for filtering exchange Signal；Described 3.3V is circumscribed with 5 shunt capacitances, for filtering the AC signal of different frequency.
Referring to Figure 56, it is the partial enlarged drawing of video input port of display driver chip.Described video input port 602 Including two groups of pins, one group of recording signal recording circuit for receiving, another group is for receiving the vision signal of broadcasting in real time. Wherein, pin B5～B8, A5～A8 record the recording signal of circuit for receiving, and pin B1～B4, A1～A4 are used for receiving The vision signal play in real time.
Referring to Figure 57, it is the partial enlarged drawing of video-out port of display driver chip.Described video-out port 603 Including 12 groups of pins, it is connected with data logger respectively, is used for exporting playback vision signal and real time video signals.
Hereinafter the course of work of the video acquisition process circuit of the present invention is described:
S11: the outside port of this video capture processor, picture processing chip, signal conversion chip and image enhaucament chip will be depended on Circuit access is carried out according to above-mentioned requirement；
S12: when video capture processor is energized, first passes through this frequency multiplier and input voltage frequency carries out multiplication regulation, to adapt to work as Front operating frequency；
S13: described controller 11 transmission triggering signal, to driver 12, is driven photoreceptor 13 to work by driver 12；
S14: when light is irradiated on photoreceptor 13, is converted optical signals to the signal of telecommunication by this photoreceptor 13, and transmits to taking Sample device 14；
S15: when sampler 14 receives the signal of telecommunication from photoreceptor 13, is sampled this signal of telecommunication processing, and will process The complete signal of telecommunication sends to follower 15；
S16: finally by described follower 15, this signal of telecommunication is converted to data signal, and carries out exporting to picture processing chip 30。
S17: described data sink 21 receives the view data of outside；
S8: image is processed by described image processor 23.Concrete the most respectively by described Lens Shading Compensation circuit 231 by mirror The shade that head produces compensates process；Bright by described optical detection circuit 232 and flash detection circuit 233 detection image Degree and flashing state, and result of detection is sent to exposure gain circuit；Then exposure is increased by described exposure gain circuit 234 Gain size.The most again by described white balance permanent circuit 35 according to default parameter, carry out the fixed adjustment of white balance.
View data after S19: described data logger 24 will process carries out exporting to the first signal conversion chip 31.
S20: the data reader 312 of described first signal conversion chip receives the bt1120 transmission letter of picture processing chip output Number, and send to signal format converter；
Bt1120 vision signal is converted to the vision signal of lvds by S21: described signal format converter 313, and sends to string Row device 314；
S22: described serializer 314 converts parallel data into serial data, and sends to data logger；
S23: described data logger 315, for exporting lvds signal data to secondary signal conversion chip.
S24: the lvds transmission of video of the first signal conversion chip is believed by the data reader 322 in secondary signal conversion chip Number, and send to signal format converter；
S25: lvds vision signal is converted to the vision signal of bt1120 by described signal format converter 323, and sends to also Row device；
S26: described deserializer 324 converts serial data into parallel data, and sends to data logger；
Bt1120 video signal data is exported to image enhaucament chip 40 by S27: described data logger 325.
S28: received the view data of outside by the data sink 41 of image enhaucament chip 40；
S29: described data sink 41, receives viewdata signal, and sends to de-noising processor 42；
S30: described de-noising processor 42 carries out noise reduction process, then is forwarded to dynamic memory 43.
S31: described dynamic memory 43 is after receiving the view data after de-noising processor 42 processes, then is forwarded to image increasing Strong device 44.
S32: described image intensifier 44, it includes an image border intensifier circuit；Described image border intensifier circuit strengthens figure Definition as edge.View data after described image intensifier first will process sends to described pixel self adaptation proofreading equipment 45.
S33: described pixel self adaptation proofreading equipment 45 carries out pixel and adapts to check and correction, retransmits to data logger 46.
View data after S34: described data logger 46 will process exports respectively to video record chip 50 and display driving core Sheet 60.
S35: by the described data sink 51 of video record chip 50 in the vision signal outside reception, and send to image Reason device 52；
S36: described image processor 52 receives the video of data sink transmission to be carried out, and processes video image, then Send to video encoder 53；Wherein, described image processor includes that the edge of the definition for strengthening image border strengthens electricity Road and for eliminating the interference circuit that abates the noise of signal disturbing.
Encoding video signal is recorded by S37: described video encoder 53；
S38: when receiving external communication order, decoding video signal is played back, and sends by described Video Decoder 54 To data logger 55；
S39: vision signal is exported to display driver chip 60 by described data logger 55.
The receiver of the analog signal 61 of S40: described display driver chip receives analog signal, and sends to analog-digital converter 63；
S41: described data signal receiver 62 receives data-signal, and sends to multiplexer 64；
S42: described analog-digital converter 63 converts analog signals into data-signal, and sends to multiplexer 64；
S43: two paths of signals is integrated by described multiplexer 64, and carry out output to output image border smoothing processor 65；
S44: described image border smoothing processor 65 receives the signal of restorer, and the edge of video image is carried out smooth place Reason, retransmits to format converter 69.
S45: the analog signal that receiver of the analog signal receives is decoded by described Video Decoder 66, and sends to field flyback Data processor 67；
S46: described field flyback data processor 67, for decoded analog signal is inserted data row, and sends to described Memory 68 stores；
S47: described memory 68 stores the data after field flyback data processor processes, and sends to output format converter 69。
S48: described output format converter 69, for signal format being changed, and exports to data logger 610；
S49: described data logger 610 carries out color output simultaneously and lvds vision signal exports.
Compared to prior art, the image gathered, by increasing by a picture processing chip in camera lens part, is processed by the present invention, Main frame backstage increases an image enhaucament chip, carries out level image enhancing, make the image finally exported become apparent from.
First, picture processing chip is divided into multiple functional module, distinguishes and by each functional module independence co-ordination, It is capable of low-power consumption, low-light (level), and can be the picture more high definition of output.Meanwhile, further at this image processor In a white balance permanent circuit is set, for being fixed by this white balance parameter, it is not necessary to operationally carry out the regulation of white balance, Thus prevent the phenomenon of aberration interference.
Then, image enhaucament chip is also divided into multiple functional module, distinguishes and by each functional module independence co-ordination, It is capable of the enhancing to image to process.Meanwhile, an image border intensifier circuit is set further in this image intensifier, uses To strengthen the definition of image border.
It addition, in order to improve signal transmission stability, the present invention by first bt1120 signal being converted to lvds signal, thus Stable transmission, and there is low noise ability.Then, it is being bt1120 signal by lvds signals revivification, thus ensure that follow-up The quality of the picture play.
The invention is not limited in above-mentioned embodiment, if to the various changes of the present invention or deformation without departing from the spirit of the present invention And scope, if within the scope of these are changed and deform claim and the equivalent technologies belonging to the present invention, then the present invention is also intended to Comprise these to change and deformation.

Claims (9)

1. video acquisition process, video record and the display circuit of a medical endoscope, it is characterised in that: include video acquisition core Sheet, picture processing chip, signal conversion chip, image enhaucament chip, video record chip and display driver chip；
Video data transmitting after described video capture processor will gather is delivered to picture processing chip and is processed；
Described signal conversion chip includes the first signal conversion chip and secondary signal conversion chip；Described first signal conversion Chip is for being converted to lvds signal by bt1120 signal；Described secondary signal conversion chip is for being converted to lvds signal Bt1120 signal；
Picture signal after described picture processing chip will process sends to the first signal conversion chip, and by this first signal Conversion chip sends to secondary signal conversion chip；Described secondary signal conversion chip sends after being changed by signal to image increasing Strong chip；
The video image of reception is carried out enhancing process by described image enhaucament chip, and be simultaneously sent to video record chip and Display driver chip, is recorded by this video record chip, this display driver chip plays in real time；
After described video record chip completes video record, send to display driver chip, carry out video playback；
Include inside described video capture processor: controller, driver, photoreceptor, sampler and follower；
Described controller, it sends trigger signal to driver for receiving the triggering signal of outside；
Described driver, it is for receiving the triggering signal of controller, and drives photoreceptor to work；
Described photoreceptor, it is for receiving the optical signal in the external world, and this optical signal is converted to the signal of telecommunication；
Described sampler, it is for being sampled processing to the signal of telecommunication of photoreceptor, and is sent extremely by the signal of telecommunication processed Follower；
Described follower, it for being converted to data signal by this signal of telecommunication, and carries out exporting picture processing chip；
Described picture processing chip includes: data sink, master controller, image processor, data logger；
Described data sink, it is for receiving the view data of outside；
Described master controller, it is for receiving the triggering signal of outside, and controls described data sink, image accordingly Processor and the duty of data logger；
Described image processor, it is for processing image；Described image processor includes a white balance permanent circuit, It is for according to the parameter preset, carrying out the fixed adjustment of white balance；
Described data logger, its view data after processing exports；
Described first signal conversion chip includes: controller, data reader, signal format converter, serializer, data Follower；
Described controller, its for receive outside triggering signal, and control data reader, signal format converter, Serializer and the work of data logger；
Described data reader, it transmits signal for the bt1120 receiving outside, and sends to signal format converter；
Described signal format converter, it for being converted to the vision signal of lvds by bt1120 vision signal, and sends extremely Serializer；
Described serializer, it is used for converting parallel data into serial data, and sends to data logger；
Described data logger, for exporting lvds signal data to secondary signal conversion chip；
Described secondary signal conversion chip includes: controller, data reader, signal format converter, deserializer, number According to follower；
Described controller, its for receive outside triggering signal, and control data reader, signal format converter, Deserializer and the work of data logger；
Described data reader, it is for the lvds video transfer signal of the first signal conversion chip, and sends to signal lattice Formula converter；
Described signal format converter, it for being converted to the vision signal of bt1120 by lvds vision signal, and sends extremely Deserializer；
Described deserializer, it is used for converting serial data into parallel data, and sends to data logger；
Described data logger, for exporting bt1120 video signal data；
Described image enhaucament chip includes: data sink, controller, static memory, image intensifier, data are defeated Go out device and clock generator；
Described data sink, it is used for receiving viewdata signal, and sends to this image intensifier；
Described controller, it is used for receiving outer triggering signal, and controls data sink, its sum of image enhaucament accordingly Duty according to follower；
Described static memory, it is for storing the driving data of image intensifier, to drive the work of this image intensifier；
Described image intensifier, it includes an image border intensifier circuit；Described image border intensifier circuit is used for strengthening figure Definition as edge；
Described data logger, it is for receiving the view data after image intensifier processes, and carries out data output；
Described clock generator, it is for producing clock signal for image enhaucament chip；
Described video record chip includes: data sink, video encoder, Video Decoder, data logger and processor；
Described data sink, for receiving the vision signal of outside, and sends to video encoder；
Described video encoder, for recording encoding video signal；
Described Video Decoder, for playing back decoding video signal；
Described data logger, for exporting vision signal；
Described processor, for controlling the work of data sink, video encoder, Video Decoder and data logger；
Described display driver chip includes: receiver of the analog signal, digit signal receiver, analog-digital converter, multiplexer, defeated Go out format converter, data logger and controller；
Described receiver of the analog signal, is used for receiving analog signal, and sends to analog-digital converter；
Described analog-digital converter, is used for converting analog signals into data-signal, and sends to multiplexer；
Described data signal receiver, is used for receiving data-signal, and sends to multiplexer；
Described multiplexer, for being integrated by two paths of signals, and carries out exporting to output format converter；
Described output format converter, for signal format being changed, and exports to data logger；
Described data logger, exports signal, and shows；
Described controller, be used for controlling receiver of the analog signal, digit signal receiver, analog-digital converter, multiplexer, Output format converter and the work of data logger.
Video acquisition process, video record and the display circuit of medical endoscope the most according to claim 1, it is characterised in that:
Described video capture processor also includes a frequency multiplier, and it carries out doubling process for the frequency triggering signal inputted outside, Retransmit the controller to described video capture processor；
Described picture processing chip also includes a frequency multiplier, and it carries out doubling process for the frequency triggering signal inputted outside, Retransmit the master controller to described picture processing chip；
Described first signal conversion chip also includes a phase-locked loop, respectively with the signal format converter of the first signal conversion chip Connect with serializer, for unified integration clock signal；
Described secondary signal conversion chip also includes a phase-locked loop, respectively with the signal format converter of secondary signal conversion chip Connect with serializer, for unified integration clock signal；
Described image enhaucament chip also includes a de-noising processor；The image that the data sink of described image enhaucament chip receives Data-signal, the de-noising processor sending extremely described image enhaucament chip carries out noise reduction process, then is forwarded to image enhaucament core The image intensifier of sheet；
Described video record chip also includes an image processor, for regarding of being received the data sink of video record chip Frequency processes, and the image after processing sends to the video encoder of video record chip；
Described display driver chip also includes a Video Decoder, field flyback data processor and memory；
Described Video Decoder, for the analog signal that the receiver of the analog signal of display driver chip receives is decoded, and Send to field flyback data processor；
Described field flyback data processor, for decoded analog signal is inserted data row, and transmission to described memory enters Row storage；
Described memory, for storage data after field flyback data processor processes, and send to display driver chip defeated Go out format converter.
Video acquisition process, video record and the display circuit of medical endoscope the most according to claim 2, it is characterised in that:
Image processor in described picture processing chip also includes an exposure gain circuit, is used for increasing exposure gain size；
Described first signal conversion chip also includes a clock data restorer, itself and the data reader of the first signal conversion chip Connect, for recovering data from the distortion and noise of transmission channel；
Described secondary signal conversion chip also includes a clock data restorer, itself and the data reader of secondary signal conversion chip Connect, for recovering data from the distortion and noise of transmission channel；
Described image enhaucament chip also includes a dynamic memory；Image after the de-noising processor process of described image enhaucament chip Data, the dynamic memory first sent to image enhaucament chip stores, then the image being forwarded to image enhaucament chip increases Strong device；
The image processor of described video record chip includes edge intensifier circuit and the interference circuit that abates the noise；
Described display driver chip also includes an image border smoothing processor, for receiving the letter of the restorer of display driver chip Number, and the edge of video image is smoothed, retransmit the format converter to display driver chip.
Video acquisition process, video record and the display circuit of medical endoscope the most according to claim 3, it is characterised in that:
The image processor of described picture processing chip also includes an optical detection circuit and flash detection circuit, and it is used for detecting figure The brightness of picture and flashing state, and result of detection is sent to described exposure gain circuit；
Described image enhaucament chip also includes a pixel self adaptation proofreading equipment；At the image intensifier of described image enhaucament chip is first incited somebody to action View data after reason sends to described pixel self adaptation proofreading equipment, this pixel self adaptation proofreading equipment carry out pixel and adapt to school Right, retransmit the data logger to image enhaucament chip.
Video acquisition process, video record and the display circuit of medical endoscope the most according to claim 4, it is characterised in that:
It is provided with outside described video capture processor: for receiving the power port of supply voltage, for exporting the video of vision signal Signal port, for export row field signal row field signal port, for receive reference voltage electricity frequency reference signal port With one for receiving the clock signal port of external timing signal；
It is provided with outside described picture processing chip: for receiving the power port of supply voltage, for receiving picture signal Receiver port, for export vision signal video signal port, for export row field signal row field signal port, For receive external timing signal clock signal port, for receive storage data data receiver port and be used for connecing Receive the PORT COM of external communication order；
It is provided with outside described first signal conversion chip: for receiving the power port of supply voltage, for receiving bt1120 The receiver port of vision signal, for exporting the video signal port of lvds vision signal and for exporting row field signal Row field signal port；
It is provided with outside described secondary signal conversion chip: for receiving the power port of supply voltage, for receiving lvds The receiver port of vision signal and for exporting the video signal port of bt1120 vision signal；
Described image enhaucament chip exterior is provided with: for receiving the power port of supply voltage, for receiving picture signal Receiver port, for export vision signal video signal port, for export row field signal row field signal port, For receiving the clock signal port of external timing signal and for receiving the data receiver port of storage data；
Described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM； Described video input port is connected with the data sink of this video record chip internal, for receiving the video data of outside； Described video-out port, is connected with described data logger, is used for exporting video data；Described PORT COM, with institute State processor to connect, for receiving the serial port command of outside；
It is provided with outside described display driver chip: power port, video reception port and VT mouth； Described video reception port is connected with the receiver of the analog signal within display driver chip and data signal receiver；Institute State video-out port to be connected with the data logger within display driver chip.
Video acquisition process, video record and the display circuit of medical endoscope the most according to claim 5, it is characterised in that:
The power port of described video capture processor is circumscribed with one for the filter circuit of voltage stabilizing；Described filter circuit includes an electricity Sense and at least one electric capacity；Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, described The other end of each electric capacity and ground connection；Power port is accessed in one end that described inductance is connected with electric capacity；
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing；Described filter circuit includes one Individual inductance and at least one electric capacity；Described inductance one end is connected with external power source, the other end respectively with one end of each electric capacity Connect, the other end ground connection of described each electric capacity；Power port is accessed in one end that described inductance is connected with electric capacity；
The power port of described video record chip is circumscribed with a filter circuit；Described filter circuit includes a magnetic bead and at least One electric capacity；Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity；Described power port is connected to Between magnetic bead and electric capacity；
Described display driver chip power port is circumscribed with a filter circuit；Described filter circuit includes a magnetic bead and at least Individual electric capacity；Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity；Described power port is connected to magnetic Between pearl and electric capacity.
Video acquisition process, video record and the display circuit of medical endoscope the most according to claim 5, it is characterised in that:
The row field signal port of described video capture processor is circumscribed with one for providing the resistance of signal strength signal intensity.
Video acquisition process, video record and the display circuit of medical endoscope the most according to claim 5, it is characterised in that:
The reference signal port of described video capture processor is circumscribed with the electric capacity as voltage electricity frequency reference data.
Video acquisition process, video record and the display circuit of medical endoscope the most according to claim 5, it is characterised in that:
The external clock circuit of clock signal port of described video capture processor, it includes that a clock shakes chip；Described clock shakes chip Power end is connected with power supply by a filter circuit, the shake output of chip of this clock debugs circuit and described clock by one Signal port connects；Described filter circuit is made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, The other end is connected with electric capacity, and the other end ground connection of this electric capacity；The shake power end of chip of described clock is connected to inductance and electric capacity Between；Described debugging electricity routing resistance and electric capacity composition；One end of the resistance of this debugging circuit is connected with the output of Zhong Zhen, The other end is connected with electric capacity, and the other end ground connection of this electric capacity；Described clock signal port be connected to this resistance and electric capacity it Between；
The described external clock circuit of picture processing chip clock signal port, it includes that a clock shakes chip；Described clock shakes core The power end of sheet is connected with power supply by a filter circuit, this clock shake chip output by one debug circuit and described time Clock signal port connects；Described filter circuit is made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, The other end is connected with electric capacity, and the other end ground connection of this electric capacity；The shake power end of chip of described clock is connected to inductance and electric capacity Between；Described debugging electricity routing resistance and electric capacity composition；One end of the resistance of this debugging circuit is connected with the output of Zhong Zhen, The other end is connected with electric capacity, and the other end ground connection of this electric capacity；Described clock signal port be connected to this resistance and electric capacity it Between；
The external clock circuit of clock signal port of described image enhaucament chip, it includes that a clock shakes chip；Described clock shakes The power end of chip is connected with power supply by a filter circuit, and this clock shakes the output of chip and described clock signal port company Connect；Described filter circuit is made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, the other end and electricity Hold and connect, and the other end ground connection of this electric capacity.
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CN110300247B (en) * 2019-07-03 2021-07-09 豪威科技(上海)有限公司 Endoscope control circuit and endoscope
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