CN204887167U - Reinforcing of medical endoscope's image processing , video is recorded and display circuit - Google Patents
Reinforcing of medical endoscope's image processing , video is recorded and display circuit Download PDFInfo
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- CN204887167U CN204887167U CN201520474046.7U CN201520474046U CN204887167U CN 204887167 U CN204887167 U CN 204887167U CN 201520474046 U CN201520474046 U CN 201520474046U CN 204887167 U CN204887167 U CN 204887167U
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Abstract
The utility model relates to a reinforcing of medical endoscope's image processing, video is recorded and display circuit, record chip and display driving chip including image manipulation chip, signal conversion chip, image enhancement chip, video, signal conversion chip includes a signal conversion chip and the 2nd signal conversion chip, image signal after image manipulation chip will handle sends to the first signal conversion chip to send to the 2nd signal conversion chip by this the first signal conversion chip, the 2nd signal conversion chip sends the chip to image enhancement after with signal conversion, the image enhancement chip carries out the humidifying treatment with the video image who receives to sent simultaneously records chip and display driving chip to the video, records the chip by this video and records, is play in real time by this display driving chip, the video is recorded chip completion video and is recorded the back, sends to display driving chip, carries out the video playback.
Description
Technical field
The utility model relates to a kind of image processing circuit, particularly a kind of image procossing for medical endoscope strengthen, video record and display circuit.
Background technology
Endoscope is a kind of conventional medicine equipment, is become by flexible part, light source and an arrangement of mirrors head group.Through the natural hole of human body, or the minimal incision * that underwent operative is done enters in human body, during use, endoscope is imported the organ of preliminary examination, directly can spy on the change of relevant portion.
When endoscope is at inside of human body, is divided by the camera lens part of this endoscope and carry out video acquisition, and the transmission of video after gathering is carried out image procossing to main frame backstage, and play in real time.Then, because doctor is in surgical procedure, may need to repeat viewing to some pictures or video.
Wherein, the quality of picture quality directly affects the result of use of endoscope.Existing general use fujinon electronic video endoscope is observed, and the treatment system image after observation being sent to outside connection carries out image procossing.But, during owing to carrying out IMAQ in human body, can due to a variety of causes of inside of human body, and cause occurring noise jamming, brightness cannot regulate or cause due to the color of light image to occur aberration automatically, so cause in the image procossing in later stage, being difficult to the image of rediscover, making doctor be difficult to identification when observing.Therefore need to provide one to be specifically designed to enhancing picture quality, and record the circuit of the video that endoscope gathers.
Utility model content
The utility model is that the shortcoming overcoming prior art is with not enough, provides a kind of image procossing for medical endoscope to strengthen and records circuit.
The utility model is achieved through the following technical solutions: a kind of image procossing of medical endoscope strengthens, video record and display circuit, it is characterized in that: comprise picture processing chip, signal conversion chip, image enhaucament chip, video record chip and display driver chip; Described signal conversion chip comprises the first signal conversion chip and secondary signal conversion chip; Described first signal conversion chip is used for bt1120 signal to be converted to lvds signal; Described secondary signal conversion chip is used for lvds signal to be converted to bt1120 signal;
Picture signal after process is sent to the first signal conversion chip by described picture processing chip, and is sent to secondary signal conversion chip by this first signal conversion chip;
Described secondary signal conversion chip is sent to image enhaucament chip after being changed by signal;
The video image of reception is carried out enhancing process by described image enhaucament chip, and is sent to video record chip and display driver chip simultaneously, is recorded, play in real time by this display driver chip by this video record chip;
After described video record chip completes video record, be sent to display driver chip, carry out video playback.
Compared to prior art, the utility model is by increasing by a picture processing chip in camera lens part, the image gathered is processed, main frame backstage increases an image enhaucament chip, carry out level image enhancing, make the last image exported more clear, be finally sent to video record chip and display driver chip respectively again, carry out video record and play in real time; And video record chip is connected with driving display chip, playing back videos can be carried out by this driving display chip.
First, in picture processing chip, be divided into multiple functional module, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Then, in image enhaucament chip, be also divided into multiple functional module, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
In addition, in order to improve the stability of Signal transmissions, the utility model is by being first converted to lvds signal by bt1120 signal, thus stable transmission, and there is low noise ability.Then, be bt1120 signal by lvds signals revivification, thus ensure that the quality of the picture of follow-up play.
As further improvement of the utility model, described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described first signal conversion chip comprises: controller, data reader, signal format converter, serializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, serializer and data logger;
---described data reader, it for receiving outside bt1120 signal transmission, and is sent to signal format converter;
---described signal format converter, it for bt1120 vision signal being converted to the vision signal of lvds, and is sent to serializer;
---described serializer, it for parallel data is converted to serial data, and is sent to data logger;
---described data logger, for exporting lvds signal data to secondary signal conversion chip;
Described secondary signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;
---described data reader, it for the lvds video transfer signal of the first signal conversion chip, and is sent to signal format converter;
---described signal format converter, it for lvds vision signal being converted to the vision signal of bt1120, and is sent to deserializer;
---described deserializer, it for serial data is converted to parallel data, and is sent to data logger;
---described data logger, for bt1120 video signal data is exported;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking;
Described video record chip comprises: data sink, video encoder, Video Decoder, data logger and processor;
---described data sink, for receiving outside vision signal, and is sent to video encoder;
---described video encoder, for recording encoding video signal;
---described Video Decoder, for decoding video signal playback;
---described data logger, for exporting vision signal;
---described processor, for the work of control data receiver, video encoder, Video Decoder and data logger;
Described display driver chip comprises: receiver of the analog signal, digit signal receiver, analog to digital converter, multiplexer, output format transducer, data logger and controller;
---described receiver of the analog signal, for receiving analog signal, and is sent to analog to digital converter;
---described analog to digital converter, for analog signal is converted to data-signal, and is sent to multiplexer;
---described data signal receiver, for receiving data-signal, and is sent to multiplexer;
---described multiplexer, for being integrated by two paths of signals, line output of going forward side by side is to output format transducer;
---described output format transducer, for signal format being changed, and exports data logger to;
---described data logger, exports signal, and shows;
---described controller, for the work of control simulation signal receiver, digit signal receiver, analog to digital converter, multiplexer, output format transducer and data logger.
As further improvement of the utility model, described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller;
Described first signal conversion chip also comprises a phase-locked loop, is connected respectively, for unified integration clock signal with signal format converter and serializer;
Described secondary signal conversion chip also comprises a phase-locked loop, is connected respectively with signal format converter and serializer, for unified integration clock signal;
Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier;
Described video record chip also comprises an image processor, processes for the video received data sink, and the image after process is sent to video encoder;
Described display driver chip also comprises a Video Decoder, field flyback data processor and memory;
Described Video Decoder, decodes for the analog signal received by receiver of the analog signal, and is sent to field flyback data processor;
Described field flyback data processor, for by capable for decoded analog signal data inserting, and be sent to described memory and store;
Described memory, for storing the data after field flyback data processor processes, and is sent to output format transducer.
As further improvement of the utility model, described image processor also comprises an exposure gain circuit, for increasing exposure gain size;
Described first signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described secondary signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier;
The image processor of described video record chip comprises edge intensifier circuit and the interfered circuit that abates the noise;
Described display driver chip also comprises an image border smoothing processor, for receiving the signal of restorer, and to the smoothing process in the edge of video image, then is sent to format converter.
As further improvement of the utility model, described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit;
Described image enhaucament chip also comprises a pixel self adaptation proofreading equipment; View data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger by this pixel self adaptation proofreading equipment.
As further improvement of the utility model, described image enhaucament chip also comprises a vision signal multiplier and a storage signal multiplier; Described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
As further improvement of the utility model, described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receive bt1120 vision signal receiver port, for exporting the video signal port of lvds vision signal and the row field signal port for exporting row field signal;
Described secondary signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receiving the receiver port of lvds vision signal and the video signal port for exporting bt1120 vision signal;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving;
Described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM; Described video input port is connected with the data sink of this video record chip internal, for receiving outside video data; Described video-out port, is connected with described data logger, for output video data; Described PORT COM, is connected with described processor, for receiving outside serial port command;
Described display driver chip outside is provided with: power port, video input port, video-out port and PORT COM; Described video input port is connected with the data sink of this video record chip internal, for receiving outside video data; Described video-out port, is connected with described data logger, for output video data; Described PORT COM, is connected with described processor, for receiving outside serial port command.
As further improvement of the utility model, the power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described video record chip is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at least one electric capacity; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected between magnetic bead and electric capacity;
Described display driver chip power port is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at least one electric capacity; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected between magnetic bead and electric capacity.
As further improvement of the utility model, the external clock circuit of clock signal port of described picture processing chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of clock signal port of described image enhaucament chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
As further improvement of the utility model, the data receiver port of described picture processing chip is circumscribed with a memory circuitry, it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
In order to understand better and implement, describe the utility model in detail below in conjunction with accompanying drawing.
Accompanying drawing explanation
Fig. 1 is chip connection diagram of the present utility model.
Fig. 2 is the internal module connection diagram of picture processing chip.
Fig. 3 is the circuit module schematic diagram of the image processor of picture processing chip.
Fig. 4 is the voltage segment circuit diagram of picture processing chip.
Fig. 5 is the outside port circuit diagram of picture processing chip.
Fig. 6 is the circuit diagram of the filter circuit of the 3.3V voltage of picture processing chip.
Fig. 7 is the circuit diagram of the filter circuit of the 1.8V voltage of picture processing chip.
Fig. 8 is the circuit diagram of the filter circuit of the 1.2V voltage of picture processing chip.
Fig. 9 is the partial enlarged drawing of the receiver port of picture processing chip.
Figure 10 is the partial enlarged drawing of the video signal port of picture processing chip.
Figure 11 is the partial enlarged drawing of the row field signal port of picture processing chip.
Figure 12 is the schematic diagram of the clock circuit of picture processing chip.
Figure 13 is the schematic diagram of the memory circuit of picture processing chip.
Figure 14 is the partial enlarged drawing of the PORT COM of picture processing chip.
Figure 15 is the internal components connection diagram of the first signal conversion chip.
Figure 16 is the internal module connection diagram of secondary signal conversion chip.
Figure 17 is the outside port connection diagram of the first signal conversion chip.
Figure 18 is the close-up schematic view of the power port of the first signal conversion chip.
Figure 19 is the partial enlarged drawing of the receiver port of the first signal conversion chip.
Figure 20 is the partial enlarged drawing of the video signal port of the first signal conversion chip.
Figure 21 is the partial enlarged drawing of the row field signal port of the first signal conversion chip.
Figure 22 is the outside connecting circuit figure of secondary signal conversion chip.
Figure 23 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.
Figure 24 is the partial enlarged drawing of the video signal port of secondary signal conversion chip.
Figure 25 is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.
Figure 26 is the internal module connection diagram of image enhaucament chip.
Figure 27 is the outside connecting circuit figure of Part I of image enhaucament chip.
Figure 28 is the outside connecting circuit figure of Part II of image enhaucament chip.
Figure 29 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltage of image enhaucament chip.
Figure 30 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.8V.
Figure 31 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.2V.
Figure 32 is the partial enlarged drawing of the receiver port of image enhaucament chip.
Figure 33 a is the partial enlarged drawing of the video signal port Part I of image enhaucament chip.
Figure 33 b is the partial enlarged drawing of the video signal port Part II of image enhaucament chip.
Figure 34 is the circuit diagram of the clock circuit of image enhaucament chip.
Figure 35 is the partial enlarged drawing of the row field signal port of image enhaucament chip.
Figure 36 is the internal components connection diagram of video record chip.
Figure 37 is the video input circuit figure of video record chip.
Figure 38 is the video output circuit figure of video record chip.
Figure 39 be video record chip with communication input circuit figure.
Figure 40 is the partial enlarged drawing of the power port of video record chip.
Figure 41 is the partial enlarged drawing of the PORT COM of video record chip.
Figure 42 is the internal components connection diagram of display driver chip.
Figure 43 is the external signal input circuit figure of display driver chip.
Figure 44 is the external signal output circuit figure of display driver chip.
Figure 45 is the partial enlarged drawing of the power port of display driver chip.
Figure 46 is the partial enlarged drawing of the video input port of display driver chip.
Figure 47 is the partial enlarged drawing of the video-out port of display driver chip.
Embodiment
Refer to Fig. 1, it is chip connection diagram of the present utility model.The image procossing that the utility model provides a kind of medical endoscope strengthens, video record and display circuit, comprises picture processing chip 10, signal conversion chip 20 and image enhaucament chip 30; Described signal conversion chip 20 comprises the first signal conversion chip 21 and secondary signal conversion chip 22; Described first signal conversion chip 21 is for being converted to lvds signal by bt1120 signal; Described secondary signal conversion chip 22 is for being converted to bt1120 signal by lvds signal; Picture signal after process is sent to the first signal conversion chip 21 by described picture processing chip 10, and is sent to secondary signal conversion chip 22 by this first signal conversion chip 21; Described secondary signal conversion chip 22 is sent to image enhaucament chip 30 after being changed by signal.
Refer to Fig. 2, it is the internal module connection diagram of picture processing chip.Described picture processing chip comprises: data sink 11, master controller 12, image processor 13, data logger 14.
Described data sink 11, it is for receiving outside view data;
Described master controller 12, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
Described image processor 13, it is for processing image.
Described data logger 14, it is for exporting the view data after process.
Further, described picture processing chip also comprises a frequency multiplier 15, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller 12.
Refer to Fig. 3, it is the circuit module schematic diagram of the image processor of picture processing chip.Concrete, described image processor 13 comprises a Lens Shading Compensation circuit 131, optical detection circuit 132, flash detection circuit 133, exposure gain circuit 134 and white balance permanent circuit 135.
Described Lens Shading Compensation circuit 131, it compensates process for the shade produced by camera lens.
Described optical detection circuit 132 and flash detection circuit 133, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.
Described exposure gain circuit 134, for increasing exposure gain size.
Described white balance permanent circuit 135, it, for according to the parameter preset, carries out the fixed adjustment of white balance.
Please refer to Fig. 4 and Fig. 5, it is respectively voltage segment and other outside port circuit diagrams of picture processing chip.In addition, in order to adapt to the application of this picture processing chip, be provided with in described picture processing chip outside further: for receive supply power voltage power port 101, for receive picture signal receiver port 102, for outputting video signal video signal port 103, for export row field signal row field signal port one 04, for receive external timing signal clock signal port 105, for receive store data data receiver port 106 and one for receiving the PORT COM 107 of external communication order.
Refer to Fig. 6-8, it is respectively the circuit diagram of 3.3V, 1.8V and 1.2V of picture processing chip.Further, described power port 101 is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Concrete, the external voltage of described picture processing chip comprises: 3.3V, 1.8V and 1.2V tri-kinds.Wherein, 3.3V voltage place in circuit comprises 2 electric capacity, and 1.8V voltage place in circuit comprises 5 electric capacity, and the voltage place in circuit of 1.2V comprises 6 electric capacity, to filter the interference signal of different frequency respectively.
Refer to Fig. 9, it is the partial enlarged drawing of the receiver port of picture processing chip.Described receiver port 102 comprises 8 pins, for receiving outside video signal.
Refer to Figure 10, it is the partial enlarged drawing of the video signal port of picture processing chip.Described video signal port 103 comprises the vision signal of two groups of different-formats, carries out doubleway output, plays in real time respectively to facilitate and records.
Refer to Figure 11, it is the partial enlarged drawing of the row field signal port of picture processing chip.Described row field signal port one 04 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 12, it is the schematic diagram of the clock circuit of picture processing chip.The external clock circuit of described clock signal port 105, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Refer to Figure 13, it is the schematic diagram of the memory circuit of picture processing chip.Further, described data receiver port 106 is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
Refer to Figure 14, it is the partial enlarged drawing of the PORT COM of picture processing chip.Described PORT COM 107, for receiving the trigger command of external transmission, carries out work with what trigger this picture processing chip.
Refer to Figure 15, it is the internal components connection diagram of the first signal conversion chip.Described first signal conversion chip 21 comprises: controller 211, data reader 212, signal format converter 213, serializer 214, data logger 215, phase-locked loop 216 and clock data restorer 217;
Described controller 211, it is for receiving outside triggering signal, and the work of control data reader 212, signal format converter 213, serializer 214 and data logger 215;
Described data reader 212, it for receiving outside bt1120 signal transmission, and is sent to signal format converter;
Described signal format converter 213, it for bt1120 vision signal being converted to the vision signal of lvds, and is sent to serializer;
Described serializer 214, it for parallel data is converted to serial data, and is sent to data logger;
Described data logger 215, for exporting lvds signal data to secondary signal conversion chip.
Described phase-locked loop 216, is connected with signal format converter and serializer respectively, for unified integration clock signal.
Described clock data restorer 217, it is connected with data reader, for recovering data from the distortion and noise of transmission channel.
Refer to Figure 16, it is the internal module connection diagram of secondary signal conversion chip.Described secondary signal conversion chip 22 comprises: controller 221, data reader 222, signal format converter 223, deserializer 224, data logger 225, phase-locked loop 226 and clock data restorer 227;
Described controller 221, it is for receiving outside triggering signal, and the work of control data reader 222, signal format converter 223, deserializer 224 and data logger 225;
Described data reader 222, it for the lvds video transfer signal of the first signal conversion chip, and is sent to signal format converter;
Described signal format converter 223, it for lvds vision signal being converted to the vision signal of bt1120, and is sent to deserializer 224;
Described deserializer 224, it for serial data is converted to parallel data, and is sent to data logger;
Described data logger 225, for exporting bt1120 video signal data.
Described phase-locked loop 226, is connected with signal format converter and deserializer respectively, for unified integration clock signal.
Described clock data restorer 227, it is connected with data reader 222, for recovering data from the distortion and noise of transmission channel.
Refer to Figure 17, it is the outside port connection diagram of the first signal conversion chip.Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port 2101, for receive bt1120 vision signal receiver port 2102, for exporting the video signal port 2103 of lvds vision signal and the row field signal port 2104 for exporting row field signal.
Please refer to Figure 18, it is the close-up schematic view of the power port of the first signal conversion chip.Described power port 2101 place is circumscribed with the electric capacity for filtering alternating current.
Refer to Figure 19, it is the partial enlarged drawing of the receiver port of the first signal conversion chip.Described receiver port 2102, it is connected with described data reader 21; Concrete, this receiver port includes 20 pins, for receiving the vision signal of outside bt1120.
Refer to Figure 20, it is the partial enlarged drawing of the video signal port of the first signal conversion chip.Described video signal port 2103 includes 4 output pins, and for exporting lvds vision signal, and this video signal port is connected with this data logger.
Refer to Figure 21, it is the partial enlarged drawing of the row field signal port of the first signal conversion chip.Described row field signal port 2104 includes a line signal output pin and a field signal output pin; Described row field signal port 2104 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 22, it is the outside connecting circuit figure of secondary signal conversion chip.Described secondary signal conversion chip outside is provided with: for receive lvds vision signal receiver port 2201, for exporting video signal port 2202 and the row field signal port 2203 of bt1120 vision signal.
Refer to Figure 23, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip.Described receiver port 2201, it is connected with described data reader 221; Concrete, this receiver port includes 4 pins, for receiving the lvds vision signal that the first signal conversion chip exports.
Refer to Figure 24, it is the partial enlarged drawing of the video signal port of secondary signal conversion chip.Described video signal port 2202 includes 20 output pins, and for exporting bt1120 vision signal, and this video signal port is connected with this data logger.
Refer to Figure 25, it is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.Described row field signal port 2203 includes a line signal output pin and a field signal output pin; Described row field signal port 2104 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 26, it is the internal module connection diagram of image enhaucament chip.Described image enhaucament chip comprises: data sink 31, de-noising processor 32, dynamic memory 33, image intensifier 34, pixel self adaptation proofreading equipment 35, data logger 36, static memory 37, controller 38, vision signal multiplier 39, storage signal multiplier 310, clock generator 311.
Described data sink 31, it is for receiving viewdata signal, and is sent to de-noising processor 32;
The viewdata signal that described data sink 31 receives, is sent to de-noising processor 32 and carries out noise reduction process, then be forwarded to dynamic memory 33.
After the view data of described dynamic memory 33 after receiving de-noising processor 22 process, then be forwarded to image intensifier 34.
Described image intensifier 34, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border.Further, the view data after process is first sent to described pixel self adaptation proofreading equipment 35 by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger 36 by this pixel self adaptation proofreading equipment 35.
Described data logger 36, it for receiving the view data after image intensifier process, and carries out data output;
Described static memory 37, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller 38, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
Described clock generator 311, it is for being image enhaucament chip clocking.Further, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier 29 and storage signal multiplier 310, and by this vision signal multiplier 39, clock signal is sent to data sink, by this storage signal multiplier 310, clock signal is sent to dynamic memory and static memory.
Please refer to Figure 27 and Figure 28, it is respectively the outside connecting circuit figure of image enhaucament chip.
Further, described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port 301, for outputting video signal video signal port 302, for receive external timing signal clock signal port 303, for exporting the row field signal port 304 of row field signal.
Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and 1.2V tri-kinds of voltages.Refer to Figure 29, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Refer to Figure 30-31, it is respectively the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively the voltage of 1.8V and 1.2V.Concrete, described power-switching circuit comprises a power conversion chip; The voltage of the input access 3.3V of described power conversion chip, output exports the voltage of 1.8V and 1.2V respectively, to power to image enhaucament chip.
Refer to Figure 32, it is the partial enlarged drawing of the receiver port of image enhaucament chip.Described receiver port 301 comprises 20 signal pins, is connected with the data sink 31 of inside, for receiving the picture signal of input.
Refer to Figure 33 a and 33b, it is respectively the Part I of the video signal port of image enhaucament chip and the partial enlarged drawing of Part II.Described video signal port 302 comprises 20 signal pins, and it is connected, for output image signal with inner data logger 36.
Refer to Figure 34, it is the circuit diagram of the clock circuit of image enhaucament chip.Further, the external clock circuit of described clock signal port 303, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Refer to Figure 35, it is the partial enlarged drawing of the row field signal port of image enhaucament chip.Described row field signal port 304 comprises a row signal pins and a field signal pin.Described row field signal port 304 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 36, it is the internal components connection diagram of video record chip.Described video record chip comprises: data sink 41, image processor 42, video encoder 43, Video Decoder 44, data logger 45 and processor 46;
Described data sink 41, for receiving outside vision signal, and is sent to image processor;
Described image processor 42, the video sent for receiving data sink carries out, and processes video image, then is sent to video encoder; Wherein, described image processor comprises the edge intensifier circuit of the definition for strengthening image border and the interfered circuit that abates the noise for erasure signal interference.
Described video encoder 43, for recording encoding video signal;
Described Video Decoder 44, for decoding video signal playback;
Described data logger 45, for exporting vision signal;
Described processor 46, for the work of control data receiver 41, image processor 42, video encoder 43, Video Decoder 44 and data logger 45.
Refer to Figure 37-39, it is the video input of video record chip, video frequency output and communication input circuit figure.Further, described video record chip exterior is provided with: power port 401, video input port 402, video-out port 403 and PORT COM 404.Described video input port is connected with the data sink of this video record chip internal, for receiving outside video data; Described video-out port, is connected with described data logger, for output video data; Described PORT COM, is connected with described processor, for receiving outside serial port command.
Refer to Figure 40, it is the partial enlarged drawing of the power port of video record chip.Described power port 401 is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at least one electric capacity; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected between magnetic bead and electric capacity.
Refer to Figure 41, it is the partial enlarged drawing of the PORT COM of video record chip.Described PORT COM 404 includes two pins, carries out communication as serial ports and external command.By the mode of serial communication, the data wire of use is few, can save communications cost.
Refer to Figure 42, it is the internal components connection diagram of display driver chip.Described display driver chip comprises: receiver of the analog signal 51, digit signal receiver 52, analog to digital converter 53, multiplexer 54, image border smoothing processor 55, Video Decoder 56, field flyback data processor 57, memory 58, output format transducer 59, data logger 510 and controller 511.
Described receiver of the analog signal 51, for receiving analog signal, and is sent to analog to digital converter 53;
Described data signal receiver 52, for receiving data-signal, and is sent to multiplexer 54;
Described analog to digital converter 53, for analog signal is converted to data-signal, and is sent to multiplexer 54;
Described multiplexer 54, for being integrated by two paths of signals, line output of going forward side by side is to output image edge-smoothing processor 55;
Described image border smoothing processor 55, for receiving the signal of restorer, and to the smoothing process in the edge of video image, then is sent to format converter 59.
Described Video Decoder 56, decodes for the analog signal received by receiver of the analog signal, and is sent to field flyback data processor 57;
Described field flyback data processor 57, for by capable for decoded analog signal data inserting, and be sent to described memory 58 and store;
Described memory 58, for storing the data after field flyback data processor processes, and is sent to output format transducer 59.
Described output format transducer 59, for signal format being changed, and exports data logger 510 to;
Described data logger 510 carries out color simultaneously and exports and the output of lvds vision signal.
Described controller 511, for the work of control simulation signal receiver 51, digit signal receiver 52, analog to digital converter 53, multiplexer 54, image border smoothing processor 55, Video Decoder 56, field flyback data processor 57, memory 58, output format transducer 59 and data logger 510.
Refer to Figure 43 and Figure 44, it is respectively external signal input circuit figure and the signal output apparatus figure of display driver chip.Further, the outside of described display driver chip is provided with: power port 501, video reception port 502 and VT mouth 503; Receiver of the analog signal 51 and the data signal receiver 52 of described video reception port 502 and display driver chip inside are connected; Described video-out port 503 is connected with the data logger 510 of display driver chip inside.
Refer to Figure 45, it is the partial enlarged drawing of the power port of display driver chip.Described power port 501 comprises the power pins of a 1.2V and the power pins of 3.3V; Described 1.2V pin is circumscribed with two electric capacity in parallel, for filtering AC signal; Described 3.3V is circumscribed with 5 shunt capacitances, for filtering the AC signal of different frequency.
Refer to Figure 46, it is the partial enlarged drawing of the video input port of display driver chip.Described video input port 502 comprises two groups of pins, and record the recording signal of circuit for receiving for one group, another group is for receiving the vision signal play in real time.Wherein, pin B5 ~ B8, A5 ~ A8 record the recording signal of circuit for receiving, and pin B1 ~ B4, A1 ~ A4 are for receiving the vision signal play in real time.
Refer to Figure 47, it is the partial enlarged drawing of the video-out port of display driver chip.Described video-out port 503 comprises 12 groups of pins, is connected respectively with data logger, for exporting playback video signal and real time video signals.
Below the course of work of image processing circuit of the present utility model is described:
S1: will to this picture processing chip, the first signal conversion chip, secondary signal conversion chip, and the outside port of image enhaucament chip carries out circuit access according to above-mentioned requirement;
S2: when picture processing chip is energized, first carries out multiplication by this frequency multiplier by input voltage frequency and regulates, to adapt to current operating frequency;
S3: first receive outside view data by the data sink 11 of picture processing chip 10;
S4: described image processor 13 pairs of images process.Specifically respectively by described Lens Shading Compensation circuit 131, the shade that camera lens produces is compensated process; By brightness and the flashing state of described optical detection circuit 132 and flash detection circuit 133 detection image, and result of detection is sent to exposure gain circuit; Then exposure gain size is increased by described exposure gain circuit 134.Last again by described white balance permanent circuit 35 according to default parameter, carry out the fixed adjustment of white balance.
S5: the view data after process is carried out output first signal conversion chip by described data logger 14.
S6: the data reader 212 of described first signal conversion chip receives the bt1120 signal transmission of picture processing chip output, and is sent to signal format converter;
S7: bt1120 vision signal is converted to the vision signal of lvds by described signal format converter 213, and is sent to serializer 214;
S8: parallel data is converted to serial data by described serializer 214, and is sent to data logger;
S9: described data logger 215, for exporting lvds signal data to secondary signal conversion chip.
S10: by the lvds video transfer signal of the data reader 222 in secondary signal conversion chip by the first signal conversion chip, and be sent to signal format converter;
S11: lvds vision signal is converted to the vision signal of bt1120 by described signal format converter 223, and is sent to deserializer;
S12: serial data is converted to parallel data by described deserializer 224, and is sent to data logger;
S13: described data logger 225 exports bt1120 video signal data to image enhaucament chip.
S14: receive outside view data by the data sink 31 of image enhaucament chip;
S15: described data sink 31, receives viewdata signal, and is sent to de-noising processor 32;
S16: described de-noising processor 32 carries out noise reduction process, then is forwarded to dynamic memory 33.
S17: after the view data of described dynamic memory 33 after receiving de-noising processor 32 process, then be forwarded to image intensifier 34.
S18: described image intensifier 34, it comprises an image border intensifier circuit; Described image border intensifier circuit strengthens the definition of image border.View data after process is first sent to described pixel self adaptation proofreading equipment 35 by described image intensifier.
S19: described pixel self adaptation proofreading equipment 35 carries out pixel and adapts to check and correction, then is sent to data logger 36.
S20: described data logger 36 exports the view data after process to video record chip 40 and display driver chip 50 respectively.
S21: by the described data sink 41 of video record chip 40 in receiving outside vision signal, and be sent to image processor 42;
S22: the video that described image processor 42 receives data sink transmission carries out, and processes video image, then is sent to video encoder 43; Wherein, described image processor comprises the edge intensifier circuit of the definition for strengthening image border and the interfered circuit that abates the noise for erasure signal interference.
S23: described video encoder 43 pairs of encoding video signals are recorded;
S24: when receiving external communication order, the 44 pairs of decoding video signal playback of described Video Decoder, and be sent to data logger 45;
S25: described data logger 45 pairs of vision signals export display driver chip to.
S26: the receiver of the analog signal 51 of described display driver chip receives analog signal, and is sent to analog to digital converter 53;
S27: described data signal receiver 52 receives data-signal, and is sent to multiplexer 54;
S28: analog signal is converted to data-signal by described analog to digital converter 53, and is sent to multiplexer 54;
S29: two paths of signals is integrated by described multiplexer 54, line output of going forward side by side is to output image edge-smoothing processor 55;
S39: described image border smoothing processor 55 receives the signal of restorer, and to the smoothing process in the edge of video image, then be sent to format converter 59.
S31: the analog signal that receiver of the analog signal receives is decoded by described Video Decoder 56, and is sent to field flyback data processor 57;
S32: described field flyback data processor 57, for by capable for decoded analog signal data inserting, and be sent to described memory 58 and store;
S33: described memory 58 stores the data after field flyback data processor processes, and is sent to output format transducer 59.
S34: described output format transducer 59, for signal format being changed, and exports data logger 510 to;
S35: described data logger 510 carries out color simultaneously and exports and the output of lvds vision signal.
Compared to prior art, the utility model, by increasing by a picture processing chip in camera lens part, processes the image gathered, main frame backstage increases an image enhaucament chip, carries out level image enhancing, makes the last image exported more clear.
First, in picture processing chip, be divided into multiple functional module, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Then, in image enhaucament chip, be also divided into multiple functional module, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
In addition, in order to improve the stability of Signal transmissions, the utility model is by being first converted to lvds signal by bt1120 signal, thus stable transmission, and there is low noise ability.Then, be bt1120 signal by lvds signals revivification, thus ensure that the quality of the picture of follow-up play.
The utility model is not limited to above-mentioned execution mode, if do not depart from spirit and scope of the present utility model to various change of the present utility model or distortion, if these are changed and distortion belongs within claim of the present utility model and equivalent technologies scope, then the utility model is also intended to comprise these changes and distortion.
Claims (10)
1. the image procossing of medical endoscope strengthen, video record and a display circuit, it is characterized in that: comprise picture processing chip, signal conversion chip, image enhaucament chip, video record chip and display driver chip; Described signal conversion chip comprises the first signal conversion chip and secondary signal conversion chip; Described first signal conversion chip is used for bt1120 signal to be converted to lvds signal; Described secondary signal conversion chip is used for lvds signal to be converted to bt1120 signal;
Picture signal after process is sent to the first signal conversion chip by described picture processing chip, and is sent to secondary signal conversion chip by this first signal conversion chip;
Described secondary signal conversion chip is sent to image enhaucament chip after being changed by signal;
The video image of reception is carried out enhancing process by described image enhaucament chip, and is sent to video record chip and display driver chip simultaneously, is recorded, play in real time by this display driver chip by this video record chip;
After described video record chip completes video record, be sent to display driver chip, carry out video playback.
2. according to claim 1 the image procossing of medical endoscope strengthen, video record and display circuit, it is characterized in that:
Described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described first signal conversion chip comprises: controller, data reader, signal format converter, serializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, serializer and data logger;
---described data reader, it for receiving outside bt1120 signal transmission, and is sent to signal format converter;
---described signal format converter, it for bt1120 vision signal being converted to the vision signal of lvds, and is sent to serializer;
---described serializer, it for parallel data is converted to serial data, and is sent to data logger;
---described data logger, for exporting lvds signal data to secondary signal conversion chip;
Described secondary signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;
---described data reader, it for the lvds video transfer signal of the first signal conversion chip, and is sent to signal format converter;
---described signal format converter, it for lvds vision signal being converted to the vision signal of bt1120, and is sent to deserializer;
---described deserializer, it for serial data is converted to parallel data, and is sent to data logger;
---described data logger, for bt1120 video signal data is exported;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking;
Described video record chip comprises: data sink, video encoder, Video Decoder, data logger and processor;
---described data sink, for receiving outside vision signal, and is sent to video encoder;
---described video encoder, for recording encoding video signal;
---described Video Decoder, for decoding video signal playback;
---described data logger, for exporting vision signal;
---described processor, for the work of control data receiver, video encoder, Video Decoder and data logger;
Described display driver chip comprises: receiver of the analog signal, digit signal receiver, analog to digital converter, multiplexer, output format transducer, data logger and controller;
---described receiver of the analog signal, for receiving analog signal, and is sent to analog to digital converter;
---described analog to digital converter, for analog signal is converted to data-signal, and is sent to multiplexer;
---described data signal receiver, for receiving data-signal, and is sent to multiplexer;
---described multiplexer, for being integrated by two paths of signals, line output of going forward side by side is to output format transducer;
---described output format transducer, for signal format being changed, and exports data logger to;
---described data logger, exports signal, and shows;
---described controller, for the work of control simulation signal receiver, digit signal receiver, analog to digital converter, multiplexer, output format transducer and data logger.
3. according to claim 2 the image procossing of medical endoscope strengthen, video record and display circuit, it is characterized in that:
Described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller;
Described first signal conversion chip also comprises a phase-locked loop, is connected respectively, for unified integration clock signal with signal format converter and serializer;
Described secondary signal conversion chip also comprises a phase-locked loop, is connected respectively with signal format converter and serializer, for unified integration clock signal;
Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier;
Described video record chip also comprises an image processor, processes for the video received data sink, and the image after process is sent to video encoder;
Described display driver chip also comprises a Video Decoder, field flyback data processor and memory;
Described Video Decoder, decodes for the analog signal received by receiver of the analog signal, and is sent to field flyback data processor;
Described field flyback data processor, for by capable for decoded analog signal data inserting, and be sent to described memory and store;
Described memory, for storing the data after field flyback data processor processes, and is sent to output format transducer.
4. according to claim 3 the image procossing of medical endoscope strengthen, video record and display circuit, it is characterized in that:
Described image processor also comprises an exposure gain circuit, for increasing exposure gain size;
Described first signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described secondary signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier;
The image processor of described video record chip comprises edge intensifier circuit and the interfered circuit that abates the noise;
Described display driver chip also comprises an image border smoothing processor, for receiving the signal of restorer, and to the smoothing process in the edge of video image, then is sent to format converter.
5. according to claim 4 the image procossing of medical endoscope strengthen, video record and display circuit, it is characterized in that:
Described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit;
Described image enhaucament chip also comprises a pixel self adaptation proofreading equipment; View data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger by this pixel self adaptation proofreading equipment.
6. according to claim 5 the image procossing of medical endoscope strengthen, video record and display circuit, it is characterized in that:
Described image enhaucament chip also comprises a vision signal multiplier and a storage signal multiplier; Described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
7. according to claim 1 the image procossing of medical endoscope strengthen, video record and display circuit, it is characterized in that:
Described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receive bt1120 vision signal receiver port, for exporting the video signal port of lvds vision signal and the row field signal port for exporting row field signal;
Described secondary signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receiving the receiver port of lvds vision signal and the video signal port for exporting bt1120 vision signal;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving;
Described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM; Described video input port is connected with the data sink of this video record chip internal, for receiving outside video data; Described video-out port, is connected with described data logger, for output video data; Described PORT COM, is connected with described processor, for receiving outside serial port command;
Described display driver chip outside is provided with: power port, video input port, video-out port and PORT COM; Described video input port is connected with the data sink of this video record chip internal, for receiving outside video data; Described video-out port, is connected with described data logger, for output video data; Described PORT COM, is connected with described processor, for receiving outside serial port command.
8. according to claim 7 the image procossing of medical endoscope strengthen, video record and display circuit, it is characterized in that:
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described video record chip is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at least one electric capacity; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected between magnetic bead and electric capacity;
Described display driver chip power port is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at least one electric capacity; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected between magnetic bead and electric capacity.
9. according to claim 8 the image procossing of medical endoscope strengthen, video record and display circuit, it is characterized in that:
The external clock circuit of clock signal port of described picture processing chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of clock signal port of described image enhaucament chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
10. according to claim 9 the image procossing of medical endoscope strengthen, video record and display circuit, it is characterized in that:
The data receiver port of described picture processing chip is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108124087A (en) * | 2017-12-21 | 2018-06-05 | 上海瑞烁信息科技有限公司 | A kind of ultra-fine soft electronic endoscopic images processing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108124087A (en) * | 2017-12-21 | 2018-06-05 | 上海瑞烁信息科技有限公司 | A kind of ultra-fine soft electronic endoscopic images processing method |
| CN108124087B (en) * | 2017-12-21 | 2022-01-28 | 上海瑞烁信息科技有限公司 | Image processing method of superfine flexible electronic endoscope |
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