CN204887157U - A image processing and intensifier circuit for medical endoscope - Google Patents
A image processing and intensifier circuit for medical endoscope Download PDFInfo
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- CN204887157U CN204887157U CN201520470722.3U CN201520470722U CN204887157U CN 204887157 U CN204887157 U CN 204887157U CN 201520470722 U CN201520470722 U CN 201520470722U CN 204887157 U CN204887157 U CN 204887157U
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Abstract
The utility model relates to an image processing and intensifier circuit for medical endoscope, including image manipulation chip and image enhancement chip, image manipulation chip handles the back to image data, redispatches to the image enhancement chip and carries out the humidifying treatment, image manipulation chip includes: acceptor of data, central controller, image processor, data output unit, the image enhancement chip includes: acceptor of data, controller, static memory, image intensifier, data output unit and clock generator, compared with the prior art, the utility model discloses an increase by an image manipulation chip in camera lens part, handle the image of gathering, increase by an image enhancement chip on the host computer backstage, carry out second grade image enhancement, make the image of last output more clear.
Description
Technical field
The utility model relates to a kind of image processing circuit, particularly a kind of for the image processing and enhancement circuit for medical endoscope.
Background technology
Endoscope is a kind of conventional medicine equipment, is become by flexible part, light source and an arrangement of mirrors head group.Through the natural hole of human body, or the minimal incision * that underwent operative is done enters in human body, during use, endoscope is imported the organ of preliminary examination, directly can spy on the change of relevant portion.
Wherein, the quality of picture quality directly affects the result of use of endoscope.Existing general use fujinon electronic video endoscope is observed, and the treatment system image after observation being sent to outside connection carries out image procossing.But, during owing to carrying out IMAQ in human body, can due to a variety of causes of inside of human body, and cause occurring noise jamming, brightness cannot regulate or cause due to the color of light image to occur aberration automatically, so cause in the image procossing in later stage, being difficult to the image of rediscover, making doctor be difficult to identification when observing.
Utility model content
The utility model is that the shortcoming overcoming prior art is with not enough, provides a kind of for the image processing and enhancement circuit for medical endoscope.
The utility model is achieved through the following technical solutions: a kind of image processing and enhancement circuit for medical endoscope, comprises picture processing chip and image enhaucament chip; After described picture processing chip processes view data, then be sent to image enhaucament chip carry out enhancing process;
Described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking.
Compared to prior art, the utility model, by increasing by a picture processing chip in camera lens part, processes the image gathered, main frame backstage increases an image enhaucament chip, carries out level image enhancing, makes the last image exported more clear.
First, in picture processing chip, be divided into multiple functional module, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Then, in image enhaucament chip, be also divided into multiple functional module, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
Further, described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller;
Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
Further, the image processor of described picture processing chip also comprises an exposure gain circuit, for increasing exposure gain size;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier.
Further, the image processor of described picture processing chip also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.
Further, described image enhaucament chip also comprises a pixel self adaptation proofreading equipment; View data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger by this pixel self adaptation proofreading equipment.
Further, described image enhaucament chip also comprises a vision signal multiplier and a storage signal multiplier; Described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
Further, described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving.
Further, the power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described image enhaucament chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Further, the external clock circuit of clock signal port of described picture processing chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of described picture processing chip clock signal port, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Further, the data receiver port of described picture processing chip is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
In order to understand better and implement, describe the utility model in detail below in conjunction with accompanying drawing.
Accompanying drawing explanation
Fig. 1 is the connection diagram of picture processing chip of the present utility model and image enhaucament chip.
Fig. 2 is the internal module connection diagram of picture processing chip.
Fig. 3 is the circuit module schematic diagram of the image processor of picture processing chip.
Fig. 4 is the voltage segment circuit diagram of picture processing chip.
Fig. 5 is the outside port circuit diagram of picture processing chip.
Fig. 6 is the circuit diagram of the filter circuit of the 3.3V voltage of picture processing chip.
Fig. 7 is the circuit diagram of the filter circuit of the 1.8V voltage of picture processing chip.
Fig. 8 is the circuit diagram of the filter circuit of the 1.2V voltage of picture processing chip.
Fig. 9 is the partial enlarged drawing of the receiver port of picture processing chip.
Figure 10 is the partial enlarged drawing of the video signal port of picture processing chip.
Figure 11 is the partial enlarged drawing of the row field signal port of picture processing chip.
Figure 12 is the schematic diagram of the clock circuit of picture processing chip.
Figure 13 is the schematic diagram of the memory circuit of picture processing chip.
Figure 14 is the partial enlarged drawing of the PORT COM of picture processing chip.
Figure 15 is the internal module connection diagram of image enhaucament chip.
Figure 16 is the outside connecting circuit figure of Part I of image enhaucament chip.
Figure 17 is the outside connecting circuit figure of Part II of image enhaucament chip.
Figure 18 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltage of image enhaucament chip.
Figure 19 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.8V.
Figure 20 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.2V.
Figure 21 is the partial enlarged drawing of the receiver port of image enhaucament chip.
Figure 22 is the partial enlarged drawing of the video signal port of image enhaucament chip.
Figure 23 is the circuit diagram of the clock circuit of image enhaucament chip.
Figure 24 is the partial enlarged drawing of the row field signal port of image enhaucament chip.
Embodiment
Refer to Fig. 1, it is the connection diagram of picture processing chip of the present utility model and image enhaucament chip.The utility model provides a kind of image processing and enhancement circuit for medical endoscope, comprise picture processing chip 10 and image enhaucament chip 20, after video data after gathering is carried out coagulation by described picture processing chip 10, then be sent to image enhaucament chip 20 and carry out two stage treatment.
Refer to Fig. 2, it is the internal module connection diagram of picture processing chip.Described picture processing chip comprises: data sink 11, master controller 12, image processor 13, data logger 14.
Described data sink 11, it is for receiving outside view data;
Described master controller 12, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
Described image processor 13, it is for processing image.
Described data logger 14, it is for exporting the view data after process.
Further, described picture processing chip also comprises a frequency multiplier 15, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller 12.
Refer to Fig. 3, it is the circuit module schematic diagram of the image processor of picture processing chip.Concrete, described image processor 13 comprises a Lens Shading Compensation circuit 131, optical detection circuit 132, flash detection circuit 133, exposure gain circuit 134 and white balance permanent circuit 135.
Described Lens Shading Compensation circuit 131, it compensates process for the shade produced by camera lens.
Described optical detection circuit 132 and flash detection circuit 133, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.
Described exposure gain circuit 134, for increasing exposure gain size.
Described white balance permanent circuit 135, it, for according to the parameter preset, carries out the fixed adjustment of white balance.
Please refer to Fig. 4 and Fig. 5, it is respectively voltage segment and other outside port circuit diagrams of picture processing chip.In addition, in order to the application in order to adapt to this picture processing chip, be provided with in described picture processing chip outside further: for receive supply power voltage power port 101, for receive picture signal receiver port 102, for outputting video signal video signal port 103, for export row field signal row field signal port one 04, for receive external timing signal clock signal port 105, for receive store data data receiver port 106 and one for receiving the PORT COM 107 of external communication order.
Refer to Fig. 6-8, it is respectively the circuit diagram of 3.3V, 1.8V and 1.2V of picture processing chip.Further, described power port 101 is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Concrete, the external voltage of described picture processing chip comprises: 3.3V, 1.8V and 1.2V tri-kinds.Wherein, 3.3V voltage place in circuit comprises 2 electric capacity, and 1.8V voltage place in circuit comprises 5 electric capacity, and the voltage place in circuit of 1.2V comprises 6 electric capacity, to filter the interference signal of different frequency respectively.
Refer to Fig. 9, it is the partial enlarged drawing of the receiver port of picture processing chip.Described receiver port 102 comprises 8 pins, for receiving outside video signal.
Refer to Figure 10, it is the partial enlarged drawing of the video signal port of picture processing chip.Described video signal port 103 comprises the vision signal of two groups of different-formats, carries out doubleway output, plays in real time respectively to facilitate and records.
Refer to Figure 11, it is the partial enlarged drawing of the row field signal port of picture processing chip.Described row field signal port one 04 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 12, it is the schematic diagram of the clock circuit of picture processing chip.The external clock circuit of described clock signal port 105, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Refer to Figure 13, it is the schematic diagram of the memory circuit of picture processing chip.Further, described data receiver port 106 is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
Refer to Figure 14, it is the partial enlarged drawing of the PORT COM of picture processing chip.Described PORT COM 107, for receiving the trigger command of external transmission, carries out work with what trigger this picture processing chip.
Refer to Figure 15, it is the internal module connection diagram of image enhaucament chip.Described image enhaucament chip comprises: data sink 21, de-noising processor 22, dynamic memory 23, image intensifier 24, pixel self adaptation proofreading equipment 25, data logger 26, static memory 27, controller 28, vision signal multiplier 29, storage signal multiplier 210, clock generator 211.
Described data sink 21, it is for receiving viewdata signal, and is sent to de-noising processor 22;
The viewdata signal that described data sink 21 receives, is sent to de-noising processor 22 and carries out noise reduction process, then be forwarded to dynamic memory 23.
After the view data of described dynamic memory 23 after receiving de-noising processor 22 process, then be forwarded to image intensifier 24.
Described image intensifier 24, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border.Further, the view data after process is first sent to described pixel self adaptation proofreading equipment 25 by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger 26 by this pixel self adaptation proofreading equipment 25.
Described data logger 26, it for receiving the view data after image intensifier process, and carries out data output;
Described static memory 27, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller 28, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
Described clock generator 211, it is for being image enhaucament chip clocking.Further, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier 29 and storage signal multiplier 210, and by this vision signal multiplier 29, clock signal is sent to data sink, by this storage signal multiplier 210, clock signal is sent to dynamic memory and static memory.
Please refer to Figure 16 and Figure 17, it is respectively the outside connecting circuit figure of image enhaucament chip.
Further, described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port 201, for outputting video signal video signal port 202, for receive external timing signal clock signal port 203, for exporting the row field signal port 204 of row field signal.
Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and 1.2V tri-kinds of voltages.Refer to Figure 18, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Refer to Figure 19-20, it is respectively the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively the voltage of 1.8V and 1.2V.Concrete, described power-switching circuit comprises a power conversion chip; The voltage of the input access 3.3V of described power conversion chip, output exports the voltage of 1.8V and 1.2V respectively, to power to image enhaucament chip.
Refer to Figure 21, it is the partial enlarged drawing of the receiver port of image enhaucament chip.Described receiver port 201 comprises 20 signal pins, is connected with the data sink 1 of inside, for receiving the picture signal of input.
Refer to Figure 22, it is the partial enlarged drawing of the video signal port of image enhaucament chip.Described video signal port 202 comprises 20 signal pins, and it is connected, for output image signal with inner data logger 6.
Refer to Figure 23, it is the circuit diagram of the clock circuit of image enhaucament chip.Further, the external clock circuit of described clock signal port 203, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Refer to Figure 24, it is the partial enlarged drawing of the row field signal port of image enhaucament chip.Described row field signal port 204 comprises a row signal pins and a field signal pin.Described row field signal port one 04 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Below the course of work of image processing circuit of the present utility model is described:
S1: carry out circuit access according to above-mentioned requirement by the outside port of this picture processing chip and image enhaucament chip;
S2: when picture processing chip is energized, first carries out multiplication by this frequency multiplier by input voltage frequency and regulates, to adapt to current operating frequency;
S3: first receive outside view data by the data sink 11 of picture processing chip 10;
S4: described image processor 13 pairs of images process.Specifically respectively by described Lens Shading Compensation circuit 131, the shade that camera lens produces is compensated process; By brightness and the flashing state of described optical detection circuit 132 and flash detection circuit 133 detection image, and result of detection is sent to exposure gain circuit; Then exposure gain size is increased by described exposure gain circuit 134.Last again by described white balance permanent circuit 35 according to default parameter, carry out the fixed adjustment of white balance.
S5: the view data after process exports by described data logger 14.
S6: receive outside view data by the data sink 21 of image enhaucament chip;
S3: described data sink 21, receives viewdata signal, and is sent to de-noising processor 22;
S4: described de-noising processor 22 carries out noise reduction process, then is forwarded to dynamic memory 23.
S5: after the view data of described dynamic memory 23 after receiving de-noising processor 22 process, then be forwarded to image intensifier 24.
S6: described image intensifier 24, it comprises an image border intensifier circuit; Described image border intensifier circuit strengthens the definition of image border.View data after process is first sent to described pixel self adaptation proofreading equipment 25 by described image intensifier.
S7: described pixel self adaptation proofreading equipment 25 carries out pixel and adapts to check and correction, then is sent to data logger 26.
S8: the view data after process exports by described data logger 26.
Compared to prior art, the utility model, by increasing by a picture processing chip in camera lens part, processes the image gathered, main frame backstage increases an image enhaucament chip, carries out level image enhancing, makes the last image exported more clear.
First, in picture processing chip, be divided into multiple functional module, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Then, in image enhaucament chip, be also divided into multiple functional module, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
The utility model is not limited to above-mentioned execution mode, if do not depart from spirit and scope of the present utility model to various change of the present utility model or distortion, if these are changed and distortion belongs within claim of the present utility model and equivalent technologies scope, then the utility model is also intended to comprise these changes and distortion.
Claims (10)
1. for an image processing and enhancement circuit for medical endoscope, it is characterized in that: comprise picture processing chip and image enhaucament chip; After described picture processing chip processes view data, then be sent to image enhaucament chip carry out enhancing process;
Described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking.
2. according to claim 1 for the image processing and enhancement circuit of medical endoscope, it is characterized in that: described picture processing chip also comprises a frequency multiplier, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller;
Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
3. according to claim 2 for the image processing and enhancement circuit of medical endoscope, it is characterized in that: the image processor of described picture processing chip also comprises an exposure gain circuit, for increasing exposure gain size;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier.
4. according to claim 3 for the image processing and enhancement circuit of medical endoscope, it is characterized in that: the image processor of described picture processing chip also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.
5. according to claim 4 for the image processing and enhancement circuit of medical endoscope, it is characterized in that: described image enhaucament chip also comprises a pixel self adaptation proofreading equipment; View data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger by this pixel self adaptation proofreading equipment.
6. according to claim 5 for the image processing and enhancement circuit of medical endoscope, it is characterized in that: described image enhaucament chip also comprises a vision signal multiplier and a storage signal multiplier; Described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
7. according to claim 1 for the image processing and enhancement circuit of medical endoscope, it is characterized in that: described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving.
8. according to claim 7 for the image processing and enhancement circuit of medical endoscope, it is characterized in that: the power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described image enhaucament chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
9. according to claim 7 for the image processing and enhancement circuit of medical endoscope, it is characterized in that: the external clock circuit of clock signal port of described picture processing chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of clock signal port of described image enhaucament chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
10. according to claim 7 for the image processing and enhancement circuit of medical endoscope, it is characterized in that: the data receiver port of described picture processing chip is circumscribed with a memory circuitry, it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
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| CN201520470722.3U CN204887157U (en) | 2015-06-30 | 2015-06-30 | A image processing and intensifier circuit for medical endoscope |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105391915A (en) * | 2015-06-30 | 2016-03-09 | 广东实联医疗器械有限公司 | Image processing and enhancing circuit for medical endoscope |
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2015
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105391915A (en) * | 2015-06-30 | 2016-03-09 | 广东实联医疗器械有限公司 | Image processing and enhancing circuit for medical endoscope |
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