CN105100548B - A kind of image procossing for medical endoscope enhances circuit - Google Patents
A kind of image procossing for medical endoscope enhances circuit Download PDFInfo
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- CN105100548B CN105100548B CN201510385952.4A CN201510385952A CN105100548B CN 105100548 B CN105100548 B CN 105100548B CN 201510385952 A CN201510385952 A CN 201510385952A CN 105100548 B CN105100548 B CN 105100548B
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Abstract
The present invention relates to a kind of image procossings for medical endoscope to enhance circuit, including picture processing chip, signal conversion chip and image enhancement chip；The signal conversion chip includes the first signal conversion chip and second signal conversion chip；The first signal conversion chip is used to bt1120 signals being converted to lvds signals；The second signal conversion chip is used to lvds signals being converted to bt1120 signals；By treated, picture signal is sent to the first signal conversion chip to described image processing chip, and is sent to second signal conversion chip by the first signal conversion chip；The second signal conversion chip is sent to image enhancement chip after converting signal.Compared with the prior art, the present invention handles the image of acquisition, increases by an image enhancement chip on host backstage, carry out level image enhancing, the image finally exported is made to be more clear by increasing by a picture processing chip in camera lens part.
Description
Technical field
The present invention relates to a kind of image processing circuit, especially a kind of image procossing for for medical endoscope enhances
Circuit.
Background technology
Endoscope is a kind of common medical instrument, is made of bendable portion, light source and one group of camera lens.Day through human body
The small notch that right duct or underwent operative are done enters in human body, and endoscope is imported to when use the organ of preliminary examination, can be direct
Pry through the variation in relation to position.
Wherein, the quality of picture quality directly affects the using effect of endoscope.It is existing generally using being peeped in electronics
Mirror is observed, and the image after observation is sent to the processing system progress image procossing of external connection.However, due in people
When carrying out Image Acquisition in vivo, can due to a variety of causes of inside of human body, and cause noise jamming occur, brightness can not adjust automatically
Section causes image aberration occur due to the color of light, so causes in the image procossing in later stage, it is difficult to which reduction is true
Image, make doctor observation when be difficult to recognize.
Invention content
The invention reside in, with deficiency, provided a kind of for being used at the image of medical endoscope the shortcomings that overcoming the prior art
Reason enhancing circuit.
The invention is realized by the following technical scheme：A kind of image procossing for medical endoscope enhances circuit, including
Picture processing chip, signal conversion chip and image enhancement chip；The signal conversion chip includes the first signal conversion chip
With second signal conversion chip；The first signal conversion chip is used to bt1120 signals being converted to lvds signals；Described
Binary signal conversion chip is used to lvds signals being converted to bt1120 signals；Described image processing chip by treated, believe by image
Number it is sent to the first signal conversion chip, and second signal conversion chip is sent to by the first signal conversion chip；Described
Binary signal conversion chip is sent to image enhancement chip after converting signal.
Compared with the prior art, the present invention is in camera lens part by increasing by a picture processing chip, to the image of acquisition into
Row processing, increases by an image enhancement chip on host backstage, carries out level image enhancing, keeps the image finally exported more clear
It is clear.
First, it is divided into multiple function modules in picture processing chip, is coordinated respectively and independently by each function module
Work, can realize low-power consumption, low-light (level), and can be the picture more high definition of output.Meanwhile further at the image
A white balance permanent circuit is set in reason device, for the white balance parameter to be fixed, without carrying out white balance at work
Adjusting, to prevent aberration interference the phenomenon that.
Then, it is also divided into multiple function modules in image enhancement chip, is assisted respectively and independently by each function module
Work is adjusted, can realize the enhancing processing to image.Meanwhile image border enhancing is further set in the image intensifier
Circuit, to enhance the clarity of image border.
In addition, in order to improve the stability of signal transmission, the present invention by the way that bt1120 signals are first converted to lvds signals,
To the transmission stablized, and there is low noise ability.Then, it is being bt1120 signals by lvds signals revivifications, to ensure that
The quality of the picture of follow-up play.
As a further improvement on the present invention, described image processing chip includes：Data sink, master controller, figure
As processor, data logger；
--- the data sink is used to receive external image data；
--- the master controller is used to receive external trigger signal, and accordingly control the data sink,
The working condition of image processor and data logger；
--- described image processor is used to handle image；Described image processor is solid including a white balance
Determine circuit, is used to carry out the fixed adjustment of white balance according to preset parameter；
--- the data logger is used for that image data to export by treated；
The first signal conversion chip includes：Controller, data reader, signal format converter, serializer, data
Follower；
--- the controller is used to receive external trigger signal, and controls data reader, signal format conversion
The work of device, serializer and data logger；
--- the data reader is used to receive external bt1120 transmission signals, and is sent to signal format and turns
Parallel operation；
--- the signal format converter is used to be converted to bt1120 vision signals the vision signal of lvds, and
It is sent to serializer；
--- the serializer is used to convert parallel data into serial data, and is sent to data logger；
--- the data logger, for exporting lvds signal datas to second signal conversion chip；
The second signal conversion chip includes：Controller, data reader, signal format converter, deserializer, data
Follower；
--- the controller is used to receive external trigger signal, and controls data reader, signal format conversion
The work of device, deserializer and data logger；
--- the data reader is used for the lvds video transfer signals of the first signal conversion chip, and is sent to
Signal format converter；
--- the signal format converter is used to be converted to lvds vision signals the vision signal of bt1120, and
It is sent to deserializer；
--- the deserializer is used to convert serial data into parallel data, and is sent to data logger；
--- the data logger, for bt1120 video signal datas to be exported；
Described image enhances chip：Data sink, controller, static memory, image intensifier, data output
Device and clock generator；
--- the data sink is used to receive viewdata signal, and is sent to the image intensifier；
--- the controller is used to receive outer triggering signal, and accordingly control data sink, image enhancement its
With the working condition of data logger；
--- the static memory is used to store the driving data of image intensifier, to drive the image intensifier
Work；
--- described image booster a comprising image border enhances circuit；Described image edge enhancing circuit is used for
Enhance the clarity of image border；
--- the data logger is used to receive image intensifier treated image data, and it is defeated to carry out data
Go out；
--- the clock generator is used to generate clock signal for image enhancement chip.
As a further improvement on the present invention, described image processing chip further includes a frequency multiplier, and being used for will be external defeated
The frequency of the trigger signal entered carries out doubling processing, retransmits to master controller；
The first signal conversion chip further includes a phase-locked loop, is connected respectively with signal format converter and serializer
It connects, is used for unified integration clock signal；
The second signal conversion chip further includes a phase-locked loop, is connected respectively with signal format converter and serializer
It connects, is used for unified integration clock signal；
It further includes a de-noising processor that described image, which enhances chip,；Picture number that the data sink receives it is believed that
Number, it is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
As a further improvement on the present invention, described image processor further includes an exposure gain circuit, is exposed for increasing
Gain of light size；
The first signal conversion chip further includes a clock data restorer, is connect with data reader, for from
Restore data in the distortion of transmission channel and noise；
The second signal conversion chip further includes a clock data restorer, is connect with data reader, for from
Restore data in the distortion of transmission channel and noise；
It further includes a dynamic memory that described image, which enhances chip,；The de-noising processor treated image data, first
It is sent to dynamic memory to be stored, then is forwarded to image intensifier.
As a further improvement on the present invention, described image processor further includes an optical detection circuit and flash detection electricity
Road is used for brightness and the flashing state of detection image, and result of detection is sent to exposure gain circuit；
It further includes the adaptive proofreading equipment of a pixel that described image, which enhances chip,；Described image booster first will treated figure
As data are sent to the adaptive proofreading equipment of the pixel, pixel is carried out by the adaptive proofreading equipment of the pixel and adapts to check and correction, is retransmited
To data logger.
As a further improvement on the present invention, described image enhancing chip further includes a vision signal multiplier and a storage
Signal multiplier；The clock signal of generation is respectively sent to vision signal multiplier and storage signal by the clock generator
Multiplier, and clock signal is sent to data sink by the vision signal multiplier, by the storage signal multiplier by when
Clock signal is sent to dynamic memory and static memory.
As a further improvement on the present invention, it is equipped with outside described image processing chip：Electricity for receiving supply voltage
Source port, the receiver port for receiving picture signal, the video signal port for exporting vision signal, for exporting
The row field signal port of row field signal, the clock signal port for receiving external timing signal store data for receiving
Data receiver port and a PORT COM for receiving external communication order；
It is equipped with outside the first signal conversion chip：The center processing chip exterior is equipped with：For receiving power supply electricity
The power port of pressure, the receiver port for receiving bt1120 vision signals, the video for exporting lvds vision signals
Signal port and row field signal port for exporting row field signal；
It is equipped with outside the second signal conversion chip：The center processing chip exterior is equipped with：It is supplied for receiving
The power port of piezoelectric voltage, the receiver port for receiving lvds vision signals and for exporting bt1120 vision signals
Video signal port；
Described image enhancing chip exterior is equipped with：For receiving the power port of supply voltage, for receiving picture signal
Receiver port, the video signal port for exporting vision signal, the row field signal port for exporting row field signal,
Clock signal port for receiving external timing signal and the data receiver port for receiving storage data.
As a further improvement on the present invention, the power port of described image processing chip is circumscribed with a filter for voltage stabilizing
Wave circuit；The filter circuit includes an inductance and at least one capacitance；Described inductance one end is connect with external power supply, another
End respectively with each capacitance connection, the other end of each capacitance and ground connection；One end of the inductance and capacitance connection is accessed
Power port；
The power port of described image processing chip is circumscribed with a filter circuit for voltage stabilizing；The filter circuit includes
One inductance and at least one capacitance；Described inductance one end is connect with external power supply, the other end respectively with each capacitance connection, institute
State the other end and the ground connection of each capacitance；Power port is accessed in one end of the inductance and capacitance connection.
As a further improvement on the present invention, the external clock circuit in the clock signal port of described image processing chip,
It includes that a clock shakes chip；The shake power end of chip of the clock is connect by a filter circuit with power supply, which shakes the defeated of chip
Outlet is connect by a debug circuit with the clock signal port；The filter circuit includes by an inductance and capacitance series connection group
At one end of the inductance is connect with power supply, the other end and capacitance connection, and the other end ground connection of the capacitance；The clock shakes core
Between the power end and connection and inductance and capacitance of piece；The debug circuit is made of resistance and capacitance；The electricity of the debug circuit
One end of resistance and the output end of Zhong Zhen connect, the other end and capacitance connection, and the other end ground connection of the capacitance；The clock signal
Port is connected between the resistance and capacitance；
Described image enhances the external clock circuit in clock signal port of chip comprising a clock shakes chip；The clock
The power end of chip of shaking is connect by a filter circuit with power supply, which shakes the output end of chip and the clock signal port connects
It connects；The filter circuit includes being composed in series by an inductance and capacitance, and one end of the inductance is connect with power supply, the other end and electricity
Hold connection, and the other end ground connection of the capacitance.
As a further improvement on the present invention, the data receiver port of described image processing chip is circumscribed with memory electricity
Road comprising a memory, be connected to the memory voltage port filter circuit, and be connected to the output of the memory
The resistance of port.
In order to better understand and implement, the invention will now be described in detail with reference to the accompanying drawings.
Description of the drawings
Fig. 1 is the chip connection diagram of the present invention.
Fig. 2 is the internal module connection diagram of picture processing chip.
Fig. 3 is the circuit module schematic diagram of the image processor of picture processing chip.
Fig. 4 is the voltage segment circuit diagram of picture processing chip.
Fig. 5 is the outside port circuit diagram of picture processing chip.
Fig. 6 is the circuit diagram of the filter circuit of the 3.3V voltages of picture processing chip.
Fig. 7 is the circuit diagram of the filter circuit of the 1.8V voltages of picture processing chip.
Fig. 8 is the circuit diagram of the filter circuit of the 1.2V voltages of picture processing chip.
Fig. 9 is the partial enlarged view of the receiver port of picture processing chip.
Figure 10 is the partial enlarged view of the video signal port of picture processing chip.
Figure 11 is the partial enlarged view of the row field signal port of picture processing chip.
Figure 12 is the schematic diagram of the clock circuit of picture processing chip.
Figure 13 is the schematic diagram of the storage circuit of picture processing chip.
Figure 14 is the partial enlarged view of the PORT COM of picture processing chip.
Figure 15 is the internal components connection diagram of the first signal conversion chip.
Figure 16 is the internal module connection diagram of second signal conversion chip.
Figure 17 is the outside port connection diagram of the first signal conversion chip.
Figure 18 is the close-up schematic view of the power port of the first signal conversion chip.
Figure 19 is the partial enlarged view of the receiver port of the first signal conversion chip.
Figure 20 is the partial enlarged view of the video signal port of the first signal conversion chip.
Figure 21 is the partial enlarged view of the row field signal port of the first signal conversion chip.
Figure 22 is the external connection circuit diagram of second signal conversion chip.
Figure 23 is the partial enlarged view of the receiver port of second signal conversion chip.
Figure 24 is the partial enlarged view of the video signal port of second signal conversion chip.
Figure 25 is the partial enlarged view of the row field signal port of second signal conversion chip.
Figure 26 is the internal module connection diagram of image enhancement chip.
Figure 27 is first part's external connection circuit diagram of image enhancement chip.
Figure 28 is the second part external connection circuit diagram of image enhancement chip.
Figure 29 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltages of image enhancement chip.
Figure 30 is that the 3.3V of image enhancement chip is converted to the power-switching circuit figure of 1.8V.
Figure 31 is that the 3.3V of image enhancement chip is converted to the power-switching circuit figure of 1.2V.
Figure 32 is the partial enlarged view of the receiver port of image enhancement chip.
Figure 33 a are the partial enlarged views of the video signal port first part of image enhancement chip.
Figure 33 b are the partial enlarged views of the video signal port second part of image enhancement chip.
Figure 34 is the circuit diagram of the clock circuit of image enhancement chip.
Figure 35 is the partial enlarged view of the row field signal port of image enhancement chip.
Specific implementation mode
Referring to Fig. 1, its chip connection diagram for the present invention.The present invention provides a kind of for medical endoscope
Image procossing enhances circuit, including picture processing chip 10, signal conversion chip 20 and image enhancement chip 30；The signal turns
It includes the first signal conversion chip 21 and second signal conversion chip 22 to change chip 20；The first signal conversion chip 21 is used for
Bt1120 signals are converted into lvds signals；The second signal conversion chip 22 is used to lvds signals being converted to bt1120 letters
Number；Described image processing chip 10 will treated picture signal is sent to the first signal conversion chip 21, and first believed by this
Number conversion chip 21 is sent to second signal conversion chip 22；The second signal conversion chip 22 is sent to after converting signal
Image enhancement chip 30.
Referring to Fig. 2, it is the internal module connection diagram of picture processing chip.Described image processing chip includes：
Data sink 11, master controller 12, image processor 13, data logger 14.
The data sink 11 is used to receive external image data；
The master controller 12 is used to receive external trigger signal, and accordingly controls the data sink, figure
As the working condition of processor and data logger；
Described image processor 13 is used to handle image.
The data logger 14, is used for that image data to export by treated.
Further, described image processing chip further includes a frequency multiplier 15, is used for externally input trigger signal
Frequency carries out doubling processing, retransmits to master controller 12.
Referring to Fig. 3, its circuit module schematic diagram for the image processor of picture processing chip.Specifically, the figure
As processor 13 includes a Lens Shading Compensation circuit 131, optical detection circuit 132, flash detection circuit 133, exposure gain
Circuit 134 and white balance permanent circuit 135.
The Lens Shading Compensation circuit 131 is used to the shade that camera lens generates compensating processing.
The optical detection circuit 132 and flash detection circuit 133 are used for brightness and the flashing state of detection image,
And result of detection is sent to exposure gain circuit.
The exposure gain circuit 134, for increasing exposure gain size.
The white balance permanent circuit 135 is used to carry out the fixed adjustment of white balance according to preset parameter.
It is respectively the voltage segment and other outside port circuits of picture processing chip please refer to Fig. 4 and Fig. 5
Figure.In addition, in order in order to adapt to the application of the picture processing chip, further it is equipped with outside described image processing chip：With
In the power port 101 of reception supply voltage, the receiver port 102 for receiving picture signal, for exporting video letter
Number video signal port 103, the row field signal port 104 for exporting row field signal, for receiving external timing signal
Clock signal port 105 is used to receive the logical of external communication order for receiving the data receiver port 106 and one of storage data
Interrogate port 107.
Fig. 6-8 is please referred to, is respectively the circuit diagram of 3.3V, 1.8V and 1.2V of picture processing chip.Further, described
Power port 101 is circumscribed with a filter circuit for voltage stabilizing；The filter circuit includes an inductance and at least one capacitance；
Described inductance one end is connect with external power supply, the other end respectively with each capacitance connection, the other end of each capacitance with connect
Ground；Power port is accessed in one end of the inductance and capacitance connection.Specifically, the external voltage packet of described image processing chip
It includes：Tri- kinds of 3.3V, 1.8V and 1.2V.Wherein, 3.3V voltages access circuit includes 2 capacitances, and it includes 5 that 1.8V voltages, which access circuit,
The voltage access circuit of a capacitance, 1.2V includes 6 capacitances, to filter the interference signal of different frequency respectively.
Referring to Fig. 9, its partial enlarged view for the receiver port of picture processing chip.The receiver port
102 include 8 pins, for receiving external video signal.
Referring to Fig. 10, its partial enlarged view for the video signal port of picture processing chip.The vision signal end
Mouth 103 includes the vision signal of two groups of different-formats, carries out doubleway output, is played and recorded in real time respectively to facilitate.
1 is please referred to Fig.1, is the partial enlarged view of the row field signal port of picture processing chip.The row field signal end
Frequencies and sequence of the mouth 104 for controlling video output.Such as：The display frequency of vision signal on the screen can be controlled and shown
Show sequence, can be the often row output under upper, can also be to export from left to right.
2 are please referred to Fig.1, is the schematic diagram of the clock circuit of picture processing chip.The clock signal port 105 is external
One clock circuit a comprising clock shakes chip；The shake power end of chip of the clock is connect by a filter circuit with power supply, the clock
The output end of chip of shaking is connect by a debug circuit with the clock signal port；The filter circuit include by an inductance and
Capacitance is composed in series, and one end of the inductance is connect with power supply, the other end and capacitance connection, and the other end ground connection of the capacitance；
The clock shake chip power end and connection and inductance and capacitance between；The debug circuit is made of resistance and capacitance；The tune
The output end of one end and Zhong Zhen for trying the resistance of circuit connects, the other end and capacitance connection, and the other end ground connection of the capacitance；Institute
Clock signal port is stated to be connected between the resistance and capacitance.
3 are please referred to Fig.1, is the schematic diagram of the storage circuit of picture processing chip.Further, the data receiver port
106 are circumscribed with a memory circuit comprising a memory, be connected to the memory voltage port filter circuit, and
It is connected to the resistance of the output port of the memory.
4 are please referred to Fig.1, is the partial enlarged view of the PORT COM of picture processing chip.The PORT COM 107 is used for
It receives the external trigger command transmitted, to trigger the picture processing chip work.
5 are please referred to Fig.1, is the internal components connection diagram of the first signal conversion chip.The first signal conversion
Chip 21 includes：Controller 211, data reader 212, signal format converter 213, serializer 214, data logger 215,
Phase-locked loop 216 and clock data restorer 217；
The controller 211 is used to receive external trigger signal, and controls data reader 212, signal format turn
The work of parallel operation 213, serializer 214 and data logger 215；
The data reader 212 is used to receive external bt1120 transmission signals, and is sent to signal format conversion
Device；
The signal format converter 213 is used to be converted to bt1120 vision signals the vision signal of lvds, concurrently
It send to serializer；
The serializer 214 is used to convert parallel data into serial data, and is sent to data logger；
The data logger 215, for exporting lvds signal datas to second signal conversion chip.
The phase-locked loop 216, connect with signal format converter and serializer respectively, believes for unified integration clock pulse
Number.
The clock data restorer 217, connect with data reader, for from the distortion and noise of transmission channel
Restore data.
6 are please referred to Fig.1, is the internal module connection diagram of second signal conversion chip.The second signal conversion
Chip 22 includes：Controller 221, data reader 222, signal format converter 223, deserializer 224, data logger 225,
Phase-locked loop 226 and clock data restorer 227；
The controller 221 is used to receive external trigger signal, and controls data reader 222, signal format turn
The work of parallel operation 223, deserializer 224 and data logger 225；
The data reader 222, is used for the lvds video transfer signals of the first signal conversion chip, and is sent to letter
Number format converter；
The signal format converter 223 is used to be converted to lvds vision signals the vision signal of bt1120, concurrently
It send to deserializer 224；
The deserializer 224 is used to convert serial data into parallel data, and is sent to data logger；
The data logger 225, for exporting bt1120 video signal datas.
The phase-locked loop 226, connect with signal format converter and deserializer respectively, believes for unified integration clock pulse
Number.
The clock data restorer 227 is connect with data reader 222, for from transmission channel distortion and make an uproar
Restore data in sound.
7 are please referred to Fig.1, is the outside port connection diagram of the first signal conversion chip.The first signal conversion
Chip exterior is equipped with：The center processing chip exterior is equipped with：For receiving the power port 2101 of supply voltage, for receiving
It the receiver port 2102 of bt1120 vision signals, the video signal port 2103 for exporting lvds vision signals and is used for
Export the row field signal port 2104 of row field signal.
It is the close-up schematic view of the power port of the first signal conversion chip please refer to Figure 18.The electricity
The capacitance for filtering alternating current is circumscribed at source port 2101.
9 are please referred to Fig.1, is the partial enlarged view of the receiver port of the first signal conversion chip.The signal connects
Receiving end mouth 2102 is connect with the data reader 21；Specifically, the receiver port includes 20 pins, it is used for
Receive the vision signal of external bt1120.
Figure 20 is please referred to, is the partial enlarged view of the video signal port of the first signal conversion chip.The video letter
Number port 2103 includes 4 output pins, and for exporting lvds vision signals, and the video signal port is exported with the data
Device connects.
Figure 21 is please referred to, is the partial enlarged view of the row field signal port of the first signal conversion chip.The row field letter
Number port 2104 includes a line signal output pin and a field signal output pin；The row field signal port 2104 is for controlling
The frequency and sequence of video output processed.Such as：The display frequency and display order of vision signal on the screen can be controlled, it can be with
It is the often row output under upper, can also be to export from left to right.
Figure 22 is please referred to, is the external connection circuit diagram of second signal conversion chip.The second signal conversion
Chip exterior is equipped with：For receiving the receiver port 2201 of lvds vision signals, for exporting bt1120 vision signals
Video signal port 2202 and row field signal port 2203.
Figure 23 is please referred to, is the partial enlarged view of the receiver port of second signal conversion chip.The signal connects
Receiving end mouth 2201 is connect with the data reader 221；Specifically, the receiver port includes 4 pins, it is used for
Receive the lvds vision signals of the first signal conversion chip output.
Figure 24 is please referred to, is the partial enlarged view of the video signal port of second signal conversion chip.The video letter
Number port 2202 includes 20 output pins, for exporting bt1120 vision signals, and the video signal port and the data
Follower connects.
Figure 25 is please referred to, is the partial enlarged view of the row field signal port of second signal conversion chip.The row field letter
Number port 2203 includes a line signal output pin and a field signal output pin；The row field signal port 2104 is for controlling
The frequency and sequence of video output processed.Such as：The display frequency and display order of vision signal on the screen can be controlled, it can be with
It is the often row output under upper, can also be to export from left to right.
Figure 26 is please referred to, is the internal module connection diagram of image enhancement chip.Described image enhances chip：
The adaptive proofreading equipment 35 of data sink 31, de-noising processor 32, dynamic memory 33, image intensifier 34, pixel, data are defeated
Go out device 36, static memory 37, controller 38, vision signal multiplier 39, storage signal multiplier 310, clock generator
311。
The data sink 31 is used to receive viewdata signal, and is sent to de-noising processor 32；
The viewdata signal that the data sink 31 receives is sent to de-noising processor 32 and carries out noise reduction process,
It is forwarded to dynamic memory 33 again.
The dynamic memory 33 is after receiving de-noising processor 22 treated image data, then is forwarded to image increasing
Strong device 34.
Described image booster 34 a comprising image border enhances circuit；Described image edge enhancing circuit is for increasing
The clarity of strong image border.Further, first by treated, image data is sent to the pixel certainly to described image booster
Proofreading equipment 35 is adapted to, carrying out pixel by the adaptive proofreading equipment 35 of the pixel adapts to check and correction, retransmits to data logger 36.
The data logger 36 is used to receive image intensifier treated image data, and carries out data output；
The static memory 37 is used to store the driving data of image intensifier, to drive the image intensifier
Work；
The controller 38, is used to receive outer triggering signal, and accordingly control data sink, image enhancement itself and
The working condition of data logger；
The clock generator 311 is used to generate clock signal for image enhancement chip.Further, the clock hair
The clock signal of generation is respectively sent to vision signal multiplier 29 and storage signal multiplier 310 by raw device, and by the video
Clock signal is sent to data sink by signal multiplier 39, is sent to clock signal by the storage signal multiplier 310
Dynamic memory and static memory.
It is respectively the external connection circuit diagram of image enhancement chip please refer to Figure 27 and Figure 28.
Further, described image enhancing chip exterior is equipped with：For receiving the power port of supply voltage, being used for reception figure
As the receiver port 301 of signal, the video signal port 302 for exporting vision signal, for receiving external clock letter
Number clock signal port 303, the row field signal port 304 for exporting row field signal.
Specifically, in the present embodiment, the external voltage of the power port includes tri- kinds of electricity of 3.3V, 1.8V and 1.2V
Pressure.Figure 29 is please referred to, is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltages.The filter circuit is including an inductance and extremely
A few capacitance；Described inductance one end is connect with external power supply, the other end respectively with each capacitance connection, each capacitance
The other end and ground connection；Power port is accessed in one end of the inductance and capacitance connection.
Figure 30-31 is please referred to, is respectively that 3.3V is converted to the power-switching circuit figure of 1.8V and 3.3V is converted to 1.2V
Conversion circuit figure.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is respectively converted into 1.8V and 1.2V
Voltage.Specifically, the power-switching circuit includes a power conversion chip；The input terminal of the power conversion chip accesses
The voltage of 3.3V, output end export the voltage of 1.8V and 1.2V respectively, to be powered to image enhancement chip.
Figure 32 is please referred to, is the partial enlarged view of the receiver port of image enhancement chip.The signal receiving end
Mouth 301 includes 20 signal pins, is connect with internal data sink 31, the picture signal for receiving input.
Please refer to Figure 33 a and 33b, be respectively the video signal port of image enhancement chip first part and second
The partial enlarged view divided.The video signal port 302 includes 20 signal pins, is connected with internal data logger 36
It connects, for exporting picture signal.
Figure 34 is please referred to, is the circuit diagram of the clock circuit of image enhancement chip.Further, the clock signal port
A 303 external clock circuits a comprising clock shakes chip；The shake power end of chip of the clock passes through a filter circuit and power supply and connects
It connects, the shake output end of chip of the clock is connect with the clock signal port；The filter circuit includes by an inductance and capacitance string
Connection composition, one end of the inductance are connect with power supply, the other end and capacitance connection, and the other end ground connection of the capacitance.
Figure 35 is please referred to, is the partial enlarged view of the row field signal port of image enhancement chip.The row field signal end
Mouth 304 includes a row signal pins and a field signal pin.The row field signal port 304 is used to control video output
Frequency and sequence.Such as：The display frequency and display order of vision signal on the screen can be controlled, can be every under upper
Row output, can also be to export from left to right.
The course of work of the image processing circuit of the present invention is described below：
S1：It will be to the picture processing chip, the first signal conversion chip, second signal conversion chip and image enhancement core
The outside port of piece carries out circuit access according to above-mentioned requirement；
S2：It when picture processing chip is powered, first passes through the frequency multiplier and input voltage frequency is subjected to multiplication adjusting, with suitable
Should before working frequency；
S3：The data sink 11 for first passing through picture processing chip 10 receives external image data；
S4：Described image processor 13 handles image.Specifically pass through the Lens Shading Compensation circuit 131 respectively
The shade that camera lens generates is compensated into processing；Pass through 133 detection image of the optical detection circuit 132 and flash detection circuit
Brightness and flashing state, and result of detection is sent to exposure gain circuit；Then increased by the exposure gain circuit 134
Exposure gain size.Finally again by the white balance permanent circuit 35 according to preset parameter, carries out the fixed of white balance and adjust
It is whole.
S5：By treated, image data carries out the first signal conversion chip of output to the data logger 14.
S6：The bt1120 that the data reader 212 of the first signal conversion chip receives picture processing chip output is passed
Defeated signal, and it is sent to signal format converter；
S7：Bt1120 vision signals are converted to the vision signal of lvds by the signal format converter 213, and are sent to
Serializer 214；
S8：The serializer 214 converts parallel data into serial data, and is sent to data logger；
S9：The data logger 215, for exporting lvds signal datas to second signal conversion chip.
S10：The lvds videos of the first signal conversion chip are passed by the data reader 222 in second signal conversion chip
Defeated signal, and it is sent to signal format converter；
S11：Lvds vision signals are converted to the vision signal of bt1120 by the signal format converter 223, and are sent
To deserializer；
S12：The deserializer 224 converts serial data into parallel data, and is sent to data logger；
S13：The data logger 225 exports bt1120 video signal datas to image enhancement chip.
S14：External image data is received by the data sink 31 of image enhancement chip；
S15：The data sink 31 receives viewdata signal, and is sent to de-noising processor 32；
S16：The de-noising processor 32 carries out noise reduction process, then is forwarded to dynamic memory 33.
S17：The dynamic memory 33 is after receiving de-noising processor 32 treated image data, then is forwarded to figure
Image intensifier 34.
S18：Described image booster 34 a comprising image border enhances circuit；Described image edge enhances circuit and increases
The clarity of strong image border.Described image booster first will treated that image data is sent to the pixel adaptively proofreads
Device 35.
S19：The adaptive proofreading equipment 35 of pixel carries out pixel and adapts to check and correction, retransmits to data logger 36.
S20：By treated, image data exports the data logger 36.
Compared with the prior art, the present invention is in camera lens part by increasing by a picture processing chip, to the image of acquisition into
Row processing, increases by an image enhancement chip on host backstage, carries out level image enhancing, keeps the image finally exported more clear
It is clear.
First, it is divided into multiple function modules in picture processing chip, is coordinated respectively and independently by each function module
Work, can realize low-power consumption, low-light (level), and can be the picture more high definition of output.Meanwhile further at the image
A white balance permanent circuit is set in reason device, for the white balance parameter to be fixed, without carrying out white balance at work
Adjusting, to prevent aberration interference the phenomenon that.
Then, it is also divided into multiple function modules in image enhancement chip, is assisted respectively and independently by each function module
Work is adjusted, can realize the enhancing processing to image.Meanwhile image border enhancing is further set in the image intensifier
Circuit, to enhance the clarity of image border.
In addition, in order to improve the stability of signal transmission, the present invention by the way that bt1120 signals are first converted to lvds signals,
To the transmission stablized, and there is low noise ability.Then, it is being bt1120 signals by lvds signals revivifications, to ensure that
The quality of the picture of follow-up play.
The invention is not limited in the above embodiments, if the various changes or deformation to the present invention do not depart from the present invention
Spirit and scope, if these changes and deformation belong within the scope of the claim and equivalent technologies of the present invention, then this hair
It is bright to be also intended to comprising these changes and deformation.
Claims (9)
1. a kind of image procossing for medical endoscope enhances circuit, it is characterised in that：Turn including picture processing chip, signal
Change chip and image enhancement chip；The signal conversion chip includes the first signal conversion chip and second signal conversion chip；
The first signal conversion chip is used to bt1120 signals being converted to lvds signals；The second signal conversion chip is used for will
Lvds signals are converted to bt1120 signals；By treated, picture signal is sent to the conversion of the first signal to described image processing chip
Chip, and second signal conversion chip is sent to by the first signal conversion chip；The second signal conversion chip is by signal
Image enhancement chip is sent to after conversion；
Described image processing chip includes：Data sink, master controller, image processor, data logger；
--- the data sink is used to receive external image data；
--- the master controller is used to receive external trigger signal, and accordingly controls the data sink, image
The working condition of processor and data logger；
--- described image processor is used to handle image；Described image processor includes that a white balance fixes electricity
Road is used to carry out the fixed adjustment of white balance according to preset parameter；
--- the data logger is used for that image data to export by treated；
The first signal conversion chip includes：Controller, data reader, signal format converter, serializer, data output
Device；
--- the controller is used to receive external trigger signal, and control data reader, signal format converter,
The work of serializer and data logger；
--- the data reader is used to receive external bt1120 transmission signals, and is sent to signal format converter；
--- the signal format converter is used to be converted to bt1120 vision signals the vision signal of lvds, and sends
To serializer；
--- the serializer is used to convert parallel data into serial data, and is sent to data logger；
--- the data logger, for exporting lvds signal datas to second signal conversion chip；
The second signal conversion chip includes：Controller, data reader, signal format converter, deserializer, data output
Device；
--- the controller is used to receive external trigger signal, and control data reader, signal format converter,
The work of deserializer and data logger；
--- the data reader is used for the lvds video transfer signals of the first signal conversion chip, and is sent to signal
Format converter；
--- the signal format converter is used to be converted to lvds vision signals the vision signal of bt1120, and sends
To deserializer；
--- the deserializer is used to convert serial data into parallel data, and is sent to data logger；
--- the data logger, for bt1120 video signal datas to be exported；
Described image enhances chip：Data sink, controller, static memory, image intensifier, data logger and
Clock generator；
--- the data sink is used to receive viewdata signal, and is sent to the image intensifier；
--- the controller is used to receive outer triggering signal, and accordingly controls data sink, image enhancement its sum number
According to the working condition of follower；
--- the static memory is used to store the driving data of image intensifier, to drive the work of the image intensifier
Make；
--- described image booster a comprising image border enhances circuit；Described image edge enhancing circuit is for enhancing
The clarity of image border；
--- the data logger is used to receive image intensifier treated image data, and carries out data output；
--- the clock generator is used to generate clock signal for image enhancement chip.
2. being used for the image procossing of medical endoscope according to claim 1 enhances circuit, it is characterised in that：At described image
It further includes a frequency multiplier to manage chip, is used to carry out the frequency of externally input trigger signal to double processing, retransmit into
Heart controller；
The first signal conversion chip further includes a phase-locked loop, is connect respectively with signal format converter and serializer, is used
In unified integration clock signal；
The second signal conversion chip further includes a phase-locked loop, is connect respectively with signal format converter and serializer, is used
In unified integration clock signal；
It further includes a de-noising processor that described image, which enhances chip,；The viewdata signal that the data sink receives, hair
It send to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
3. being used for the image procossing of medical endoscope according to claim 1 enhances circuit, it is characterised in that：At described image
It further includes an exposure gain circuit to manage device, for increasing exposure gain size；
The first signal conversion chip further includes a clock data restorer, is connect with data reader, is used for from transmission
Restore data in the distortion of channel and noise；
The second signal conversion chip further includes a clock data restorer, is connect with data reader, is used for from transmission
Restore data in the distortion of channel and noise；
It further includes a dynamic memory that described image, which enhances chip,；The de-noising processor treated image data, first sends
It is stored to dynamic memory, then is forwarded to image intensifier.
4. being used for the image procossing of medical endoscope according to claim 2 enhances circuit, it is characterised in that：At described image
It further includes an optical detection circuit and flash detection circuit to manage device, is used for brightness and the flashing state of detection image, and will visit
It surveys result and is sent to exposure gain circuit；
It further includes the adaptive proofreading equipment of a pixel that described image, which enhances chip,；Described image booster first will treated picture number
According to the adaptive proofreading equipment of the pixel is sent to, pixel is carried out by the adaptive proofreading equipment of the pixel and adapts to check and correction, is retransmited to number
According to follower.
5. being used for the image procossing of medical endoscope according to claim 4 enhances circuit, it is characterised in that：Described image increases
Strong chip further includes a vision signal multiplier and a storage signal multiplier；The clock generator believes the clock of generation
It number is respectively sent to vision signal multiplier and storage signal multiplier, and is sent clock signal by the vision signal multiplier
To data sink, clock signal is sent to dynamic memory and static memory by the storage signal multiplier.
6. being used for the image procossing of medical endoscope according to claim 1 enhances circuit, it is characterised in that：At described image
Reason chip exterior is equipped with：For receiving the power port of supply voltage, the receiver port for receiving picture signal, being used for
Export the video signal port of vision signal, the row field signal port for exporting row field signal, for receiving external clock letter
Number clock signal port, the data receiver port for receiving storage data and one is for receiving the communication of external communication order
Port；
It is equipped with outside the first signal conversion chip：The center processing chip exterior is equipped with：For receiving supply voltage
Power port, the receiver port for receiving bt1120 vision signals, the vision signal for exporting lvds vision signals
Port and row field signal port for exporting row field signal；
It is equipped with outside the second signal conversion chip：The center processing chip exterior is equipped with：For receiving power supply electricity
The power port of pressure, the receiver port for receiving lvds vision signals and the video for exporting bt1120 vision signals
Signal port；
Described image enhancing chip exterior is equipped with：Power port for receiving supply voltage, the letter for receiving picture signal
Number receiving port, the row field signal port for exporting row field signal, is used for the video signal port for exporting vision signal
Receive the clock signal port of external timing signal and the data receiver port for receiving storage data.
7. being used for the image procossing of medical endoscope according to claim 6 enhances circuit, it is characterised in that：At described image
The power port of reason chip is circumscribed with a filter circuit for voltage stabilizing；The filter circuit includes an inductance and at least one
Capacitance；Described inductance one end is connect with external power supply, the other end respectively with each capacitance connection, the other end of each capacitance
With ground connection；Power port is accessed in one end of the inductance and capacitance connection；
The power port of described image processing chip is circumscribed with a filter circuit for voltage stabilizing；The filter circuit includes one
Inductance and at least one capacitance；Described inductance one end is connect with external power supply, and the other end is described every respectively with each capacitance connection
The other end of a capacitance and ground connection；Power port is accessed in one end of the inductance and capacitance connection.
8. being used for the image procossing of medical endoscope according to claim 6 enhances circuit, it is characterised in that：At described image
Manage the external clock circuit in clock signal port of chip comprising a clock shakes chip；The shake power end of chip of the clock passes through
One filter circuit is connect with power supply, and the shake output end of chip of the clock is connect by a debug circuit with the clock signal port；
The filter circuit includes being composed in series by an inductance and capacitance, and one end of the inductance is connect with power supply, the other end and capacitance
Connection, and the other end ground connection of the capacitance；The clock shake chip power end and connection and inductance and capacitance between；The debugging
Electric routing resistance and capacitance composition；One end of the resistance of the debug circuit and the output end of Zhong Zhen connect, and the other end connects with capacitance
It connects, and the other end ground connection of the capacitance；The clock signal port is connected between the resistance and capacitance；
Described image enhances the external clock circuit in clock signal port of chip comprising a clock shakes chip；The clock shakes core
The power end of piece is connect by a filter circuit with power supply, and the shake output end of chip of the clock is connect with the clock signal port；
The filter circuit includes being composed in series by an inductance and capacitance, and one end of the inductance is connect with power supply, the other end and capacitance
Connection, and the other end ground connection of the capacitance.
9. being used for the image procossing of medical endoscope according to claim 6 enhances circuit, it is characterised in that：At described image
The data receiver port of reason chip is circumscribed with a memory circuit comprising a memory, the voltage end for being connected to the memory
The filter circuit of mouth, and it is connected to the resistance of the output port of the memory.
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