CN103607545A - High definition video acquisition device and working method thereof - Google Patents
High definition video acquisition device and working method thereof Download PDFInfo
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- CN103607545A CN103607545A CN201310582461.XA CN201310582461A CN103607545A CN 103607545 A CN103607545 A CN 103607545A CN 201310582461 A CN201310582461 A CN 201310582461A CN 103607545 A CN103607545 A CN 103607545A
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Abstract
The invention provides a high definition video acquisition device and a working method thereof. A front-end sensor performs video acquisition, and an acquired analog image signal is transmitted to an AD conversion chip; the AD conversion chip acquires CCD analog data, analog-to-digital conversion is performed via sampling, and the converted digital signal is transmitted to an FPGA; and the received signal is decoded by the FPGA, and a video signal is outputted via format conversion after the white balance and gamma correction processing. Various high definition resolution acquisition videos can be configured, and high definition acquisition is applied with respect to defects in aspects of resolution, contrast ratio and the like of a standard definition video acquisition device so that higher contrast ratio and resolution can be obtained.
Description
Technical field
The present invention relates to a kind of high definition video collecting device and method of work thereof, particularly relate to a kind of high definition video collecting device and method of work thereof that is applicable to video acquisition field.
Background technology
Along with socio-economic development, video acquisition device is widely used in all trades and professions.Meanwhile, video acquisition device is constantly to the development of high definition field, and high definition video collecting progressively replaces SD harvester, and this has become the place of the trend trend of market development.Especially at high definition CCD, the development of CMOS and high-speed high capacity FPGA technology, making high definition video collecting obtain large-area applications becomes possibility.
The present invention is the deficiency on resolution and contrast etc. mainly for SD video acquisition device, uses high definition collection, obtains higher contrast, resolution etc.
Summary of the invention
The technical problem to be solved in the present invention is to provide high definition video collecting device and the method for work thereof that a kind of configurable multiple high definition resolution gathers video.
The technical solution used in the present invention is as follows: a kind of high definition video collecting device, is characterized in that: comprise that connected successively front end sensors, transducer drive and AD modular converter, FPGA module and power management module; Described front end sensors is connected with power management module again; Described transducer drives and is connected with power management module again with AD modular converter.
As the present invention is further improved, described front end sensors adopts ccd sensor more than 1080p pixel.
As the present invention is further improved, described transducer drives with AD modular converter and adopts integrated AD conversion and CCD to drive chip.
As the present invention is further improved, described power management module comprises power supply control chip and gating switch chip; Described power supply control chip adopts programmable power supply control chip; Described gating switch chip adopts programmable switch chip.
The method of work of above-mentioned high definition video collecting device, concrete grammar step is: one, front end sensors is carried out video acquisition, and the analog picture signal obtaining is passed to AD conversion chip; Two, AD conversion chip obtains CCD analogue data, by sampling, carries out analog-to-digital conversion, sends the digital signal after conversion to FPGA; Three, FPGA decodes the signal of reception and carries out after white balance and gamma correction processing, through format conversion outputting video signal.In described step 2, adopt LVDS form to send FPGA to the digital signal after conversion.
As the present invention is further improved, in described step 3, FPGA is bt601 form through the vision signal of format conversion output, optionally wherein each 10 of 30 difference or optional 24 each 8, as R, G, the output of B signal, optional 2 each 1 the synchronous and field sync signal output as row, is left for output clock position.
As the present invention is further improved, in described step 3, FPGA is bt656 form through the vision signal of format conversion output, optionally wherein each 10 of 30 difference or optional 24 each 8, as R, G, the output of B signal, as clock, to export for optional 1, all the other holding wires retain.
As the present invention is further improved, described step also comprises, power management module is programmed to power supply control chip by spi bus, controls the electrifying timing sequence of CCD and AD chip by switch chip, and concrete control method is: a, power supply control chip reset; B, power supply control chip enable to power on to esd protection, to protect CCD; C, power supply control chip power on to CCD pedestal; D, power supply control chip configuration CCD gain; E, wait FPGA configuration AD chip; F, power supply control chip enable to power on and postpone 500ms to CCD row clock voltage; G, power supply control chip enable to power on to CCD field clock voltage.
Compared with prior art, the invention has the beneficial effects as follows: the configurable multiple high definition resolution of the present invention gathers video, and the deficiency for SD video acquisition device on resolution and contrast etc., is used high definition collection, can obtain higher contrast, resolution.
Accompanying drawing explanation
Fig. 1 is the principle schematic of apparatus of the present invention.
Fig. 2 is the wherein FPGA interior video data flow diagram of an embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing), unless narration especially all can be replaced by other equivalences or the alternative features with similar object.That is,, unless narration especially, each feature is an example in a series of equivalences or similar characteristics.
As shown in Figure 1, a kind of high definition video collecting device, comprises that connected successively front end sensors, transducer drive and AD modular converter, FPGA module and power management module; Described front end sensors is connected with power management module again; Described transducer drives and is connected with power management module again with AD modular converter.
FPGA module, as system control core, comprises data decode, and signal is processed, format conversion, and power management, resets and controls, and Synchronization Control drives control etc.Adopt FPGA as controlling processing center, adopted the chip of programmable integrated AD conversion and driven CCD, by FPGA, configure this chip and carry out AD conversion and drive with CCD; Adopt programmable power supply control chip to control CCD electrifying timing sequence.
Described front end sensors adopts ccd sensor more than 1080p pixel, carries out video acquisition, and will obtain analog image and pass to AD conversion chip as sensor devices.
Described transducer drives with AD modular converter and adopts integrated AD conversion and CCD to drive chip, this chip drives as CCD, control the capable field synchronization control signal of CCD and obtain CCD analogue data, by sampling, carry out analog-to-digital conversion, send digital signal after conversion to FPGA.
Described power management module comprises power supply control chip and gating switch chip; Described power supply control chip adopts programmable power supply control chip; Described gating switch chip adopts programmable switch chip.
The method of work of above-mentioned high definition video collecting device, in this specific embodiment, concrete grammar step is: one, front end ccd sensor carries out the analog video collection of Bayer form, and the analog picture signal obtaining is passed to AD conversion chip; Two, AD is converted to digital signal by this analog signal, simultaneously with LVDS formatted output; Three, FPGA receives after LVDS signal, first carries out the decoding of LVDS form in inside, then realizes the decoding of this Bayer format signal, and carries out white balance, and the processing such as gamma correction, finally by format video signals such as format conversion output bt601, bt656.
Adopt LVDS interface, increase anti-interference and general ability.
As shown in Figure 2, by spi bus, to AD, chip design drives and configures related register to FPGA, data-signal after conversion is processed, simultaneously according to rear end equipment demand, externally export high-definition digital signal, utilize that SPI system bus is multiplexing carries out power supply chip control simultaneously, with universal I/O port, carry out other logic controls (as: indicator light etc.).
In this specific embodiment, wherein, configurability for output high-definition signal form, according to main flow interface on the market at present, design 33 holding wires (can at present compatible all signal format) as the configurable output pin of whole module, according to rear end, need signal format, in FPGA inside, carry out format conversion and pin configuration.
As: if adopt bt601 form, can be optionally each 10 or optional 24 each 8 of 30 difference wherein, as R, G, the output of B signal, optional 2 each 1 as row synchronous and field sync signal export, be left for output clock position.
If adopt bt656 form, can be optionally each 10 or optional 24 each 8 of 30 difference wherein, as R, G, the output of B signal, optional 1 as clock output, all the other holding wires retain.
Other output format signal configures are similar.FPGA adopts configurable 33 holding wires as the output of rear end video format, by FPGA Code Design, can not need to change on hardware foundation, can need to export corresponding video format according to rear end.Configuration by change FPGA internal form conversion program and pin carrys out compatible different user demands.
Described step also comprises, power management module is programmed to power supply control chip by spi bus, controls the electrifying timing sequence of CCD and AD chip by switch chip, and concrete control method is: a, power supply control chip reset; B, power supply control chip enable to power on to esd protection, to protect CCD; C, power supply control chip power on to CCD pedestal; D, power supply control chip configuration CCD gain; E, wait FPGA configuration AD chip; F, power supply control chip enable to power on and postpone 500ms to CCD row clock voltage; G, power supply control chip enable to power on to CCD field clock voltage.
Claims (9)
1. a high definition video collecting device, is characterized in that: comprise that connected successively front end sensors, transducer drive and AD modular converter, FPGA module and power management module; Described front end sensors is connected with power management module again; Described transducer drives and is connected with power management module again with AD modular converter.
2. harvester according to claim 1, is characterized in that: described front end sensors adopts ccd sensor more than 1080p pixel.
3. harvester according to claim 2, is characterized in that: described transducer drives with AD modular converter and adopts integrated AD conversion and CCD to drive chip.
4. harvester according to claim 1, is characterized in that: described power management module comprises power supply control chip and gating switch chip; Described power supply control chip adopts programmable power supply control chip; Described gating switch chip adopts programmable switch chip.
5. the method for work of harvester according to claim 1, concrete grammar step is: one, front end sensors is carried out video acquisition, and the analog picture signal obtaining is passed to AD conversion chip; Two, AD conversion chip obtains CCD analogue data, by sampling, carries out analog-to-digital conversion, sends the digital signal after conversion to FPGA; Three, FPGA decodes the signal of reception and carries out after white balance and gamma correction processing, through format conversion outputting video signal.
6. method of work according to claim 1, in described step 2, adopts LVDS form to send FPGA to the digital signal after conversion.
7. method of work according to claim 1, in described step 3, FPGA is bt601 form through the vision signal of format conversion output, optionally wherein each 10 of 30 difference or optional 24 each 8, as R, G, the output of B signal, optional 2 each 1 the synchronous and field sync signal output as row, is left for output clock position.
8. method of work according to claim 1, in described step 3, FPGA is bt656 form through the vision signal of format conversion output, optionally wherein each 10 of 30 difference or optional 24 each 8, as R, G, the output of B signal, as clock, to export for optional 1, all the other holding wires retain.
9. method of work according to claim 1, described step also comprises, power management module is programmed to power supply control chip by spi bus, controls the electrifying timing sequence of CCD and AD chip by switch chip, and concrete control method is: a, power supply control chip reset; B, power supply control chip enable to power on to esd protection, to protect CCD; C, power supply control chip power on to CCD pedestal; D, power supply control chip configuration CCD gain; E, wait FPGA configuration AD chip; F, power supply control chip enable to power on and postpone 500ms to CCD row clock voltage; G, power supply control chip enable to power on to CCD field clock voltage.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935895A (en) * | 2015-06-30 | 2015-09-23 | 广东实联医疗器械有限公司 | Video capturing and processing circuit for medical endoscope |
| CN105049675A (en) * | 2015-06-30 | 2015-11-11 | 广东实联医疗器械有限公司 | Image processing enhancing and display driving circuit for medical endoscope |
| CN105100548A (en) * | 2015-06-30 | 2015-11-25 | 广东实联医疗器械有限公司 | Image processing enhancement circuit for medical endoscope |
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| CN101783008A (en) * | 2009-10-13 | 2010-07-21 | 上海海事大学 | Real-time processing platform for ultra high resolution remote sensing images based on functions of FPGA and DSP |
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| CN101783008A (en) * | 2009-10-13 | 2010-07-21 | 上海海事大学 | Real-time processing platform for ultra high resolution remote sensing images based on functions of FPGA and DSP |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935895A (en) * | 2015-06-30 | 2015-09-23 | 广东实联医疗器械有限公司 | Video capturing and processing circuit for medical endoscope |
| CN105049675A (en) * | 2015-06-30 | 2015-11-11 | 广东实联医疗器械有限公司 | Image processing enhancing and display driving circuit for medical endoscope |
| CN105100548A (en) * | 2015-06-30 | 2015-11-25 | 广东实联医疗器械有限公司 | Image processing enhancement circuit for medical endoscope |
| CN104935895B (en) * | 2015-06-30 | 2018-08-07 | 广东实联医疗器械有限公司 | A kind of video acquisition processing circuit for medical endoscope |
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