CN101783008A - Real-time processing platform for ultra high resolution remote sensing images based on functions of FPGA and DSP - Google Patents
Real-time processing platform for ultra high resolution remote sensing images based on functions of FPGA and DSP Download PDFInfo
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Abstract
The invention discloses a real-time processing platform for ultra high resolution remote sensing images based on functions of an FPGA and a DSP. The real-time processing platform mainly comprises an image acquisition module, an image preprocessing module and a remote sensing image core processing module, wherein the image acquisition module consists of a fiber coupling sensor and a Cmos image sensor; the image preprocessing module consists of a field programmable gate array (FPGA) chip, an SRAM memory and a Flash memory, and the SRAM memory and the Flash memory are connected on the FPGA chip; and the remote sensing image core processing module consists of a digital signal microprocessor (DSP) chip, a high-speed SDRAM memory and a Flash memory, and the high-speed SDRAM memory and the Flash memory are connected on the DSP chip. The invention supports high resolution images; because of high integrated level control, the effectiveness and instantaneity of the system are greatly improved; the hardware adopted by the invention has simple and flexible framework and stronger generality, and is suitable for modular design, thereby being capable of improving the efficiency of the algorithm; and simultaneously, the invention has short development period and the system which is easy to be maintained and expanded, and is specially suitable for high-speed real-time image signal processing.
Description
Technical field:
The present invention relates to a kind of remote sensing images real-time processing platform, the in particular a kind of remote sensing image processing platform that can gather in real time and handle high-resolution remote sensing image.
Background technology:
At present, in existing remote sensing images real-time processing platform, can support that the scanning imaging system of high-resolution is very not many, moreover, can be supported in the real-time processing platform phoenix feathers and unicorn horns especially that pixel on the one dimension direction reaches the remote sensing images of the ultrahigh resolution more than 6000, almost not find to have the product of this type at home.
Existing remote sensing image processing platform and camera installation (remote sensor) all are two relatively independent complete equipments mostly, therefore the processing platform of remote sensing images just can not well carry out effectively control in real time to camera installation (as functions such as exposure, gains), to such an extent as to its interlock is poor, stability is also lower.And except that above-mentioned 2, many resolution higher the remote sensing images real-time processing platform substantially all be based on traditional computer and come work operation, owing to lack special-purpose operational processes system, just the time-delay phenomenon can be when view data is handled, occurred, and the requirement of image processing platform can not be well satisfied the real-time aspect.
Summary of the invention:
The present invention is directed in the at present existing remote sensing images real-time processing platform, image resolution ratio is lower, remote sensing image processing platform and camera installation (remote sensor) are all relatively independent mostly, can not control effectively, and a series of problems such as speed is slow, real-time difference can appear when Flame Image Process, for this has carried out rational improvement to it, thereby reach the purpose that reduces cost and improve its usability.
In order to achieve the above object, the present invention adopts following technical scheme to realize:
A kind of real-time processing platform for ultra high resolution remote sensing images based on FPGA and DSP function, described remote sensing images real-time processing platform mainly comprises image capture module, image pretreatment module and remote sensing images core processing module;
Described image capture module comprises the optical fiber coupling sensor that obtains image by the transformation of light signal, and is used for remote sensing images are converted to from light signal the Cmos imageing sensor of digital signal;
Described image pretreatment module comprises that the picture signal with the Bayer form converts the on-site programmable gate array FPGA chip of luminance signal to, and SRAM reservoir that serves as the fpga chip image data buffer that links to each other with described fpga chip and the Flash reservoir that is used to solidify the fpga chip code.
Described remote sensing images core processing module comprises carries out the microprocessor dsp chip that ultrahigh resolution is handled image processing algorithm and output with view data, and being used for of linking to each other with described dsp chip is as the high speed SDRAM reservoir of dsp chip view data buffer storage be used to solidify the Flash reservoir of DSP code;
Described optical fiber coupling sensor links to each other with described Cmos imageing sensor, the data output end of described Cmos imageing sensor links to each other with described on-site programmable gate array FPGA chip, described on-site programmable gate array FPGA chip links to each other with described digital signal microprocessor dsp chip, and described digital signal microprocessor dsp chip links to each other with the control end of described Cmos imageing sensor.
Described fpga chip is realized the pre-service of image by following steps:
(101) carry out from left to right shifting function earlier, first row, the 8 bit image data of input are deposited among first pushup storage FIFO by first three shift register FD;
(102) after depositing first line data in, proceed shifting function, the second row view data of input is deposited among first pushup storage FIFO by first three shift register FD, and meanwhile, first line data among first pushup storage FIFO that is stored in begins to be delivered to the 4th shift register FD, and deposits among second pushup storage FIFO through shifting function;
(103) after first and second line data is stored fully, proceed shifting function, the third line view data of input is carried and deposited among the 3rd the shift register FD;
(104) read view data in the output port of the 3rd shift register FD and two pushup storage FIFO, form one group 3 * 3 image data matrix, calculate rgb signal by the linear interpolation computing formula then.
Described dsp chip is realized treatment of picture by following steps:
(201) gather earlier the fibre bundle view data of those face formation formulas that get to the conversion of face battle array through linear arrays from the optical fiber coupling sensor;
(202) adopt bimodulus plate value filtering device that the fiber optic hub in the fibre bundle image of gained is carried out coarse localization, and each fiber optic hub in the whole optical fiber beam images all is determined in 5 * 5 the image block scope of being approximately;
(203) in order to reduce the operand of next step operation, the image that obtains in the previous step is corroded and the cutting edge technical finesse, obtain the bianry image that background is a black;
(204) in above-mentioned bianry image,, obtain the position coordinates table of all optical fiber in whole the battle array optical fiber image by carrying out Z font search to bright;
(205) according to the position coordinates table face battle array optical fiber image of each width of cloth scanning is carried out image information and extract, the two field picture that fibre bundle is gone out end is reduced into the delegation in the original object image, the conversion between finished surface battle array and the linear array;
(206) a series of linear array images that will obtain are spliced into a complete scan image.
The present invention can overcome remote sensing images real-time processing platform above-mentioned multinomial defective, that realize ultrahigh resolution for a kind of.This platform can transmit 2592 * 1944 high-definition picture in real time, and can handle the remote sensing images that on one dimension direction pixel reaches 6000 above ultrahigh resolutions in real time, in addition platform is also supported running parameters such as the exposure of camera installation and gain are adjusted comparatively easily and controlled, and guarantees extendability, reliability and the real-time of system with this.
Description of drawings:
The invention will be further described below in conjunction with accompanying drawing.
Fig. 1 is the system architecture block scheme among the present invention.
Fig. 2 is a Key Circuit connection layout among the present invention.
Fig. 3 is the algorithm template process flow diagram of FIFO_FD among the present invention.
Fig. 4 is a whole fibre bundle imaging algorithm template process flow diagram among the present invention.
Embodiment:
For technological means, creation characteristic that the present invention is realized, reach purpose and effect is easy to understand, below in conjunction with concrete diagram, further set forth the present invention.
As shown in Figure 1, the technical solution used in the present invention is: build a kind of embedded remote sensing images real-time processing platform based on FPGA and DSP function, this platform mainly is divided into three functional blocks: image capture module, image pretreatment module and remote sensing images core processing module.
Image capture module comprises by light signal and changes the optical fiber coupling sensor that obtains image, and is used for remote sensing images are converted to from light signal the Cmos imageing sensor of digital signal; And realize tentatively obtaining of remote sensing images and carry out data-switching with convenient function of dsp chip being carried out image data transmission by these two function elements.
The image pretreatment module comprises that the picture signal with the Bayer form converts the on-site programmable gate array FPGA chip of luminance signal to, comes to carry out the calculated amount of some image pre-service with the core algorithm of dsp chip after reducing with this.And fpga chip also is connected with the SRAM reservoir that serves as the fpga chip image data buffer, and is used to solidify the Flash reservoir of fpga chip code.
And the remote sensing images core processing module is mainly finished the sensed image signal that will gather converts ultrahigh resolution image to through the ultrahigh resolution imaging algorithm function.This module peripherals mainly comprises dsp chip, and dsp chip also is connected with high speed SDRAM storer that is used for the image buffers storage and the Flash reservoir that solidifies the dsp chip code.
In whole workbench, the optical fiber coupling sensor links to each other with the Cmos imageing sensor, the data output end of Cmos imageing sensor links to each other with the on-site programmable gate array FPGA chip, the on-site programmable gate array FPGA chip links to each other with the digital signal microprocessor dsp chip, and the digital signal microprocessor dsp chip also links to each other with the control end of Cmos imageing sensor; And the on-site programmable gate array FPGA chip transmits chip by coupled USB, and the ultrahigh resolution image data signal transmission that obtains after platform processes is finished is to host computer.So just, can realize the normal operation of workbench so that workbench epigraph acquisition module, image pretreatment module and remote sensing images core processing module and USB transport module link together.
During the invention process, as shown in Figure 2, the Cmos imageing sensor that image acquisition, pre-service and transfer function piece are adopted is the five mega pixel Cmos sensor MT9T001 that MICRON company produces; Fpga chip is a field programmable gate array chip, employing be the Spartan III series of X C3S1500-4FG456C chip of Xilinx company; What the SRAM reservoir adopted is the IS64LV51216 chip that ISSI company produces, the XCF08PV0G48C chip of the Xilinx company that the FLASH reservoir uses.And the use of corresponding USB transmission chip is the CY7C68013 chip of CYPRESS company.
The data-out port of Cmos imageing sensor MT9T001 links to each other with the pin in the Bank6 of FPGA and Bank7 district, to obtain the sensed image signal that the optical fiber coupling sensor is transmitted.In order to reduce the complexity of system, the I of Cmos imageing sensor
2The C control port is the I with dsp chip DM642
2It is seamless continuous that the C control port directly carries out the two wires.
SRAM reservoir IS64LV51216 chip links to each other with Bank0, the Bank1 of fpga chip and the pin in Bank2 district by address bus and data bus as the buffer of view data in the fpga chip.
FLASH reservoir XCF08PV0G48C chip has adopted two kinds of configurations of main string pattern and JTAG pattern to be connected with FPGA.The JTAG pattern is mainly used in the on-line debugging source program, and after system's power down, the content of configuration will be lost, and main string pattern is mainly used in the curing of later stage program.
USB CY7C68013 transmission chip links to each other with the pin in the Bank3 district of fpga chip, and this chip operates mainly under the Slave fifo mode, and promptly from pattern, it mainly is responsible for view data is encapsulated and be uploaded to host computer according to usb protocol.
Dsp chip in the remote sensing images core processing module, what select for use is the TMS320DM642 chip that TI company produces.This DM642 chip is a kind of digital signal microprocessor that view data is carried out ultrahigh resolution image algorithm process and output, though its inside is provided with the one-level program buffer memory of 16KB, the one-level metadata cache of 16KB and the routine data of 256KB are shared L2 cache.But system for this direct image data processing, these buffer memorys are far from being enough, especially remote sensing images of gathering in the native system, one width of cloth view data stool and urine can be up to about 5M, therefore native system is expanded the data-carrier store that the SDRAM reservoir MT48LC8M32B2 chip that has connected two Micron companies is total to 64MB, has also expanded the Am29LV800B chip of the FLASH reservoir AMD of a slice 8MB and has deposited application program and partial data.Two SDRAM reservoirs are mapped to the external address space of dsp chip, be (the 0x80000000～0x8fffffff), and the Flash reservoir maps to the pairing 256M address space of the EMIFA CE1 of dsp chip (among the 0x90000000～0x9fffffff) of the pairing 256M address space of EMIFA CE0 in the dsp chip.
Data-interface between fpga chip and the dsp chip adopts the Vport interface mode.It is the Vport1 port that fpga chip view data output terminal is connected to dsp chip.Dsp chip collection port is selected to be operated in the 8Bit_Raw pattern for the image output format that cooperates fpga chip in native system.Therefore also need to write the driving that dsp chip is gathered port with reference to the little driving of video port that TI provides.Wait to handle after the data, dsp chip is sent to fpga chip with the 8Bit_Raw pattern of data by Vport0 again.
Because Cmos imageing sensor output is the Bayer image, for the ease of carrying out communicating by letter of data with follow-up dsp chip and reduce the computing workload of dsp chip, fpga chip also needs to convert the picture signal of Bayer form to luminance signal.The data volume of this algorithm process is big, the requirement height of processing speed, but the computing structure is relatively simple, only relies on the fpga chip computing just can realize.And, in fpga chip, intend adopting the algorithm template (the specific algorithm model is referring to Fig. 3) of FIFO_FD in order to realize this algorithm.The concrete implementation of this FIFO_FD algorithm template is as follows:
The first step, carry out the operation of shift LD from left to right earlier, 8 bit image signals of first row that is about to obtain are delivered in first shift register, deposit in the first left pushup storage 4192_Byte_FIFO from first three shift register FD through shifting function then.
Second step, after depositing first line data in, deposit second view data of sending into of going in first left pushup storage FIFO through shifting function from shift register FD, first line data that before had been stored in simultaneously first pushup storage FIFO begins to be transferred to the 4th FD, deposits second pushup storage FIFO in through shifting function again.
In the 3rd step, after waiting first and second row view data all having stored, just the third line view data of importing can be sent to the 3rd shift register FD by shift transport.
The 4th step, read the view data of output port among the 3rd shift register FD and former and later two pushup storages FIFO simultaneously, and, just can calculate rgb signal then according to the linear interpolation computing formula with the image data matrix of one 3 * 3 of it composition.
The benefit of this FIFO FD algorithm is to make the remote sensing images real-time processing platform, can carry out the processing and the transmission of real-time image information, avoids a series of problems such as its travelling speed is slow, real-time difference with this.
And what adopt in the dsp chip is the fibre bundle imaging algorithm of writing especially in order to realize function of the present invention, its juche idea is: the fibre bundle view data of the face formation formula that is obtained to the conversion of face battle array by linear array in the optical fiber coupling sensor of elder generation's collection specific arrangement, the face system of battle formations that to gather in dsp chip then looks like to convert to linear array images, more a series of linear array images is spliced into a complete data scanning image afterwards.Its calculating process is as shown in Figure 4:
The step I receives earlier from the optical fiber coupling sensor fibre bundle view data of the face formation formula that gets to the conversion of face battle array through linear array, obtains a complete fibre bundle image.
Because these fibre bundle face battle arrays go out to hold image, form by the optical fiber image piece that is approximately 9 * 9 sizes one by one, therefore also need the center of optical fiber is found out, and calibrate for the fiber optic hub position, could realize that the face system of battle formations that will collect converts linear array figure to by this process.The scaling algorithm step of this core the most is as follows:
The step II, for bright figure of the fiber optic hub that forms, at first, adopt bimodulus plate value filtering device that coarse localization is carried out in the center of optical fiber in the optical fiber image that receives, promptly utilize 93 * 3 little templates that image is handled, calculate pixel in each little template brightness and, if when the brightness of front template be maximum in 9 little templates, and minimum brightness is 255 with this template assignment then during greater than a certain threshold value, is 0 with other little template assignment.The center of each optical fiber can be determined at thus in 5 * 5 the image block scope of being approximately.
The step III in order to reduce the operand of next step operation, is corroded and the cutting edge technical finesse the image that obtains in the previous step, and to obtain background by this operation be black (being 0 value) bianry image.
The step IV is searched for bright, obtains the center of optical fiber by search.Consider the characteristics that optical fiber image is exclusive, adopt Z font search procedure among the present invention, search for the coordinate of first root optical fiber by adopting oblique 45 ° of orders, when promptly searching bright of first optical fiber, represent the center of optical fiber with this geometric center position of bright, obtain the coordinate of first optical fiber thus, utilize the priori of optical fiber afterwards, be that distance between the optical fiber is that some threshold values (being that size is about 9 pixels) are carried out step-searching, can obtain the position coordinates table of all optical fiber in whole the battle array optical fiber image thus.
The step V is carried out image information according to the position coordinates table to the face battle array optical fiber image of each width of cloth scanning and is extracted, and the two field picture that fibre bundle is gone out end is reduced into the delegation in the original object image, the conversion between finished surface battle array and the linear array.
The step VI is spliced into a complete data scanning image with a series of linear array images that obtain.
By the whole fibre bundle imaging algorithm that above dsp chip adopted, can make the remote sensing images core processing module realize that perfectly the sensed image signal that will gather converts the ultrahigh resolution image function to by the ultrahigh resolution imaging algorithm, solve in the remote sensing images real-time processing platform commonly used now, problems such as image resolution ratio is lower, and is fuzzy.
When the present invention used, its main flow process was as follows:
1. earlier pass through I by dsp chip
2The C port sends control command to the Cmos imageing sensor, adjusts the resolution of the view data of Cmos imageing sensor output, exposure rate etc.
2. then, the optical fiber coupling sensor converts light signal to remote sensing signal, and be sent in the fpga chip after converting the remote sensing images that collect to digital signal by imageing sensor, by fpga chip image is carried out pre-service again, the Bayer picture signal that is about to the output of Cmos imageing sensor converts luminance signal or rgb signal to alleviate the computational burden of dsp chip, make the workload of dsp chip can be used for core algorithm effectively, the image after will being handled by fpga chip more afterwards is sent to the Vport1 port of dsp chip.
3. after, dsp chip is carried to by the Vport1 port view data high speed SDRAM reservoir of chip exterior from FIFO, and the data of gathering are carried out the ultrahigh resolution image algorithm process, afterwards with the data handled again through Vport0 oral instructions deliver to fpga chip.
4. follow, fpga chip is finished the function that view data is cushioned by the FIFO computing template of portion's setting within it, and adds that before each frame image data the data head of 512 0x88 extracts view data to make things convenient for host computer.And the Empty signal of the FIFO template of fpga chip by detecting 68013 FlagB pin (promptly expiring signal pin) and fpga chip is simultaneously controlled view data and whether is write to USB and transmit in the chip.Afterwards, finish the encapsulation of USB transmission chip data by 68013 and will encapsulate after data be sent to host computer.
5. last, host computer C++ program is obtained the view data that USB transmission chip sends by corresponding interface function in DeviceIoControl function and the USB general driving, and when extracting each frame image data, all extract image according to the data head that originally adds by fpga chip.
Advantage of the present invention is many-sided: at first, this device is the system equipment that collection image acquisition, Flame Image Process and an image are transmitted as one, this device is supported the input of high-definition picture, support is carried out effective integrated control to camera installation, and this device can integrated various high performance image processing algorithms owing to using high-powered DSP.Owing to the high integration of functional module among the present invention, improved the validity and the real-time of total system greatly; Secondly, the hardware structure that the present invention adopts fpga chip to combine with dsp chip, this architectural configurations is flexible, and stronger versatility is arranged, and is applicable to modular design, thereby can improve efficiency of algorithm; Its construction cycle of while is shorter, and system is easy to maintenance and expansion, is particularly suitable for the high-speed real-time picture signal and handles.
More than show and described ultimate principle of the present invention and principal character and advantage of the present invention.The technician of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the instructions just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (3)
1. the real-time processing platform for ultra high resolution remote sensing images based on FPGA and DSP function is characterized in that, described remote sensing images real-time processing platform mainly comprises image capture module, image pretreatment module and remote sensing images core processing module;
Described image capture module comprises the optical fiber coupling sensor that obtains image by the transformation of light signal, and is used for remote sensing images are converted to from light signal the Cmos imageing sensor of digital signal;
Described image pretreatment module comprises that the picture signal with the Bayer form converts the on-site programmable gate array FPGA chip of luminance signal to, and SRAM reservoir that serves as the fpga chip image data buffer that links to each other with described fpga chip and the Flash reservoir that is used to solidify the fpga chip code.
Described remote sensing images core processing module comprises carries out view data that the ultrahigh resolution image Processing Algorithm is handled and the microprocessor dsp chip of output, and being used for of linking to each other with described dsp chip is as the high speed SDRAM reservoir of dsp chip view data buffer storage be used to solidify the Flash reservoir of DSP code;
Described optical fiber coupling sensor links to each other with described Cmos imageing sensor, the data output end of described Cmos imageing sensor links to each other with described on-site programmable gate array FPGA chip, described on-site programmable gate array FPGA chip links to each other with described digital signal microprocessor dsp chip, and described digital signal microprocessor dsp chip links to each other with the control end of described Cmos imageing sensor.
2. a kind of real-time processing platform for ultra high resolution remote sensing images based on FPGA and DSP function according to claim 1 is characterized in that, described fpga chip is realized the pre-service of image by following steps:
(101) carry out from left to right shifting function earlier, first row, the 8 bit image data of input are deposited among first pushup storage FIFO by first three shift register FD;
(102) after depositing first line data in, proceed shifting function, the second row view data of input is deposited among first pushup storage FIFO by first three shift register FD, and meanwhile, first line data among first pushup storage FIFO that is stored in begins to be delivered to the 4th shift register FD, and deposits among second pushup storage FIFO through shifting function;
(103) after first and second line data is stored fully, proceed shifting function, the third line view data of input is carried and deposited among the 3rd the shift register FD;
(104) read view data in the output port of the 3rd shift register FD and two pushup storage FIFO, form one group 3 * 3 image data matrix, calculate rgb signal by the linear interpolation computing formula then.
3. a kind of real-time processing platform for ultra high resolution remote sensing images based on FPGA and DSP function according to claim 1 is characterized in that described dsp chip is realized treatment of picture by following steps:
(201) gather earlier the fibre bundle view data of those face formation formulas that get to the conversion of face battle arrays through linear arrays from the optical fiber coupling sensor;
(202) adopt bimodulus plate value filtering device that the fiber optic hub in the fibre bundle image of gained is carried out coarse localization, and each fiber optic hub in the whole optical fiber beam images is determined in 5 * 5 the image block scope of being approximately;
(203) in order to reduce the operand of next step operation, the image that obtains in the previous step is corroded and the cutting edge technical finesse, obtain the bianry image that background is a black;
(204) in above-mentioned bianry image,, obtain the position coordinates table of all optical fiber in whole the battle array optical fiber image by carrying out Z font search to bright;
(205) according to the position coordinates table face battle array optical fiber image of each width of cloth scanning is carried out image information and extract, the two field picture that fibre bundle is gone out end is reduced into the delegation in the original object image, the conversion between finished surface battle array and the linear array;
(206) a series of linear array images that will obtain are spliced into a complete scan image.
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