CN201937742U - High-speed image acquisition system - Google Patents
High-speed image acquisition system Download PDFInfo
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- CN201937742U CN201937742U CN2010206585213U CN201020658521U CN201937742U CN 201937742 U CN201937742 U CN 201937742U CN 2010206585213 U CN2010206585213 U CN 2010206585213U CN 201020658521 U CN201020658521 U CN 201020658521U CN 201937742 U CN201937742 U CN 201937742U
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Abstract
The utility model provides a high-speed image acquisition system, which comprises a CMOS (complementary metal oxide semiconductor) sensor, an FPGA (field programmable gate array) chip, an SDRAM (synchronous dynamic random access memory) chip and a USB (universal serial bus) controller. The CMOS sensor is connected with the FPGA chip, the SDRAM chip is connected with the FPGA chip, and the USB controller is connected with the FPGA chip. Compared with the prior art, the high-speed image acquisition system solves problems of high power consumption and cost of a traditional image acquisition system by means of adopting the CMOS sensor as an image sensor. The FPGA chip is used as an image acquisition and processing module and has the advantages of high integration and field programmable logic functions, accordingly a core functional module is realized, a circuit for realizing functions of peripheral control, decoding, interference and the like can be further integrated inside the FPGA, and all control logics are completed by hardware. In addition, the high-speed image acquisition system solves the problem of insufficient speed for processing image at high speed due to the fact that processing speed of the hardware can be higher than that of software by multiple times. Furthermore, the FPGA chip has the advantage of flexibility and convenience in programming, logical edition and modification can be realized according to needs of different fields, image processing functions for all needs can be flexibly and conveniently realized, needed original logics can be reserved during the logical edition and modification, and repeated development operation is reduced. The high-speed SDRAM chip with high capacity is used as an image storage module, and is favorable for acquiring real-time image data at high speed for a long time and realizing intelligent processing of various images at a front end.
Description
Technical field
The utility model relates to electronic circuit field, relates in particular to a kind of high-speed image sampling system.
Background technology
The occasion that needs the high-definition picture collection for high-precision optical measurement, satellite remote sensing etc., need large scale, high-resolution imageing sensor, at present the high-definition camera of industrial circle adopts ccd image sensor mostly, however this class ccd image sensor but have power consumption high and low owing to the finished product yield, need ward off transmission channel in addition and add the high shortcoming of cost of manufacture that peripheral circuit such as ADC causes.Thereby to use the cmos sensor with characteristics such as manufacture craft is simpler, low in energy consumption, integrated level height be present developing direction in large scale, high-resolution industrial picture acquisition system.
Thereby but, large scale, high-resolution industrial picture acquisition system require the implementation that has high speed image to handle because having the image data amount is big, real-time performance is high characteristics, and most of image processing work of industrial picture acquisition system are at present all realized by software, be difficult to reach the requirement of processing speed, thereby also almost be in blank at present based on the industrial picture acquisition system application-specific integrated circuit (ASIC) more than 9,000,000 pixels of cmos image sensor.
The utility model content
In order to solve the problem of power consumption height of the prior art, cost of manufacture height and high pixel image processing processing speed deficiency, the utility model provides a kind of high-speed image sampling system, comprises imageing sensor, IMAQ and processing module, image memory module, and USB controller; Described imageing sensor adopts cmos sensor, and described data acquisition and processing (DAP) module adopts fpga chip, and described image memory module adopts the SDRAM chip; Described cmos sensor is connected with described fpga chip, and described SDRAM chip is connected with described fpga chip, and described USB controller is connected with described fpga chip.
The further improvement that the utility model is done is: described fpga chip comprises main control module, sensor interface control module, USB interface control module and sdram controller module; Described sensor interface control module is connected with described cmos sensor and is connected with described main control module; Described USB interface control module is connected with described USB controller and is connected with described main control module; Described sdram controller module is connected with described SDRAM chip and is connected with described main control module.
The further improvement that the utility model is done is: described main control module comprises Clock management module, command analysis and control module, Data Control module and FIFO; Described Clock management module is connected with each functional module on the described fpga chip and provides clock signal for being attached thereto each functional module that connects; Described command analysis is connected with described USB interface control module with control module and is connected with described sensor interface control module; Described Data Control module is connected with the sensor interface control module, is connected with described FIFO and is connected with described sdram controller module; Described FIFO comprises input FIFO and output FIFO, described input FIFO is connected with described sensor interface control module and is connected with described Data Control module, and described output FIFO is connected with described USB interface control module and is connected with described Data Control module.
The further improvement that the utility model is done is: described sensor interface control module comprises I
2C interface control module and video interface control module; Described I
2The C interface control module is connected with described cmos sensor and is connected with control module with described command analysis; Described video interface control module is connected with described cmos sensor, is connected with described input FIFO and is connected with described Data Control module.
The further improvement that the utility model is done is: described I
2The C interface control module is connected by SCLK clock line and SDATA data wire with described cmos sensor; Described video interface control module is connected by the capable useful signal line of LINE_VALID, FRAME_VALID frame useful signal line, PIX_CLK pixel clock line and PIX_DATA pixel data line with described cmos sensor.
The further improvement that the utility model is done is: described USB controller, described USB interface control module, described command analysis and control module, described I
2C interface control module and described cmos sensor connect to form by configuration and the control channel of host computer to described cmos sensor; Described cmos sensor, described video interface control module, described input FIFO, described Data Control module, described sdram controller module, described SDRAM chip, described output FIFO, described USB interface control module and described USB controller connect to form the video Data Transmission passage.
The further improvement that the utility model is done is: described USB interface control module is connected by DATA data/address bus, IFCLK interface clock line, SLOE enable signal line, SLRD reading signal lines, SLWR write signal line, FIFOADR bus select signal line, PKTEND bag ED holding wire, FLAGA marking signal line able to programme, FLAGB full scale will holding wire and the empty marking signal line of FLAGC with described USB controller.
With respect to prior art, the high-speed image sampling system in the utility model adopts cmos sensor as imageing sensor, has solved power consumption height, problem that cost is high; Adopted fpga chip as IMAQ and processing module, because fpga chip has the characteristics of integrated level height and logic function field-programmable, except realizing corn module, can also realize peripheral control in inside, circuit such as decoding and interface, thereby all control logic is finished by hardware, and hardware process speed can reach more than the several times of software processes, thereby solved the problem of high speed image processing speed deficiency, fpga chip has the flexible characteristics of programming in addition, can carry out the edit-modify of logic according to different on-the-spot needs, thereby can realize the image processing function of various needs flexibly and easily, and when updating the modification logic, can keep the former logic that need use, reduced the work of overlapping development; Adopt big capacity, high-speed SDRAM chip as the image memory module, help for a long time at high speed the images acquired real time data and carry out various intelligent images at front end and handle; Adopt subordinate fifo mode data transmission scheme in addition between fpga chip and the USB controller, help the high rate data transmission of data.
Description of drawings
Fig. 1 is the structural representation of the utility model high-speed image sampling system.
Fig. 2 is the work-based logic block diagram of the utility model high-speed image sampling system.
Embodiment
Below in conjunction with description of drawings and embodiment the utility model is further specified.
As depicted in figs. 1 and 2, the high-speed image sampling system in the utility model comprises imageing sensor, IMAQ and processing module, image memory module, and USB controller 4; Imageing sensor adopts cmos sensor 1, and the data acquisition and processing (DAP) module adopts fpga chip 2, and data memory module adopts SDRAM chip 3; Cmos sensor 1 is connected with fpga chip 2, and SDRAM chip 3 is connected with fpga chip 2, and USB controller 4 is connected with fpga chip 2.
Fpga chip 2 comprises main control module, sensor interface control module 21, USB interface control module 24 and sdram controller module 23 (being used to control the storage mode of SDRAM chip 3); Sensor interface control module 21 is connected with cmos sensor 1 and is connected with main control module; USB interface control module 24 is connected with USB controller 4 and is connected with main control module; Sdram controller module 23 is connected and is connected with main control module with described SDRAM chip 3.
Main control module has mainly been realized mutual, the data allocations of whole system of foundation, each functional module of control signal and the storage and the transmission of processing and data, and it comprises Clock management module 221, command analysis and control module 222, Data Control module 223 and FIFO; The Clock management module is connected with each functional module on the fpga chip 2 and provides required clock signal for being attached thereto each functional module that connects; Command analysis and control module 222 resolved from the USB controller and received the host computer order of coming, and produces corresponding control signal to each functional module, and it is connected with USB interface control module 24 and is connected with sensor interface control module 21; Data allocations and processing that Data Control module 223 is responsible for system (thereby realize various image processing functions, for example proofread and correct, stretch, cut, merge, adjust resolution, saturation, brightness etc.) and the storage and the transmission of data, it is connected with sensor interface control module 21, is connected with FIFO and is connected with sdram controller module 23; (one is outside view data synchronised clock and because the collection of data need be crossed over two clock zones, another is the operation clock of FPGA), so design data buffer memory FIFO is for metadata cache and two effects of clock isolation here, can read and write isolation to data, guarantee the reliability of data, also for ping-pong operation, realize the uninterrupted collection of data, FIFO comprises input FIFO 2241 and output FIFO 2242, input FIFO 2241 is connected with sensor interface control module 21, and be connected with Data Control module 223, output FIFO2242 is connected with USB interface control module 24, and be connected with Data Control module 223.
Sensor interface control module 21 comprises I
2C interface control module 211 and video interface control module 212; I
2C interface control module 211 is connected with cmos sensor 1 and is connected with control module 222 with command analysis; Video interface control module 212 is connected with cmos sensor 1, is connected and is connected with Data Control module 223 with input FIFO 2241.
I
2C interface control module 211 (is transmitted I with cmos sensor 1 by the SCLK clock line
2The clock signal of C universal serial bus is represented this clock signal with SCLK) and SDATA data wire (transmission I
2The data-signal of C universal serial bus is represented this data-signal with SDATA) be connected; Video interface control module 212 is used for the conversion finishing the transmission of video data and finish video data format, video interface control module 212 (is transmitted the row useful signal with described cmos sensor 1 by the capable useful signal line of LINE_VALID, represent this signal with LINE_VALID), FRAME_VALID frame useful signal line (transmission frame useful signal, represent this signal with FRAME_VALID), PIX_CLK pixel clock line (transmission pixel clock signal, represent this signal with PIX_CLK), and PIX_DATA pixel data line (the transmission pixel data signal is represented this signal with PIX_DATA) is connected.
USB controller 4, USB interface control module 24, command analysis and control module 222, I
2C interface control module 211 and cmos sensor 1 connect to form by configuration and the control channel of host computer to cmos sensor, and command analysis and control module 222 are from the configuration data of USB interface control module 24 reception host computers, and generation meets I
2The sequential of C interface, to the configuration and the control channel of cmos sensor the effective configuration data are sent to cmos sensor 1 by host computer by this, in addition the host computer that receives from USB interface control module 24 of command analysis and control module 222 to the order of cmos sensor 1 after resolving also by by this channel transfer to cmos sensor 1; Cmos sensor 1, video interface control module 212, input FIFO 2241, Data Control module 223, sdram controller module 23, SDRAM chip 3, output FIFO 2242, USB interface control module 24, and USB controller 4 connects to form the video Data Transmission passage, after obtaining complete video original frame data, passes through the buffer memory of SDRAM chip 3 this channel transfer to host computer from the view data of cmos sensor 1 retaking of a year or grade with certain framing rule, in this process, when beginning, every frame data judge according to the traffic rate of USB interface whether SDRAM chip 3 can renew the complete data of a frame by the mode of stream, if can then deposit these frame data in SDRAM chip 3, otherwise abandon this frame data, thereby finish automatic frame per second control.
USB interface control module 24 is passed through DATA data/address bus (transmission of data signals with USB controller 4, represent this signal with DATA), IFCLK interface clock line (transmit clock signal, represent this signal with IFCLK), (transmission reads or writes enable signal to SLOE enable signal line, represent this signal with SLOE), SLRD reading signal lines (transmission read signal, represent this signal with SLRD), SLWR write signal line (is made private copy of read signal, represent this signal with SLWR), (transmission FIFO selects signal with being connected of data/address bus to FIFOADR bus select signal line, represent this signal with FIFOADR), the PKTEND bag transmits the end signal line, and (transmission package transmits end signal, represent this signal with PKTEND), FLAGA marking signal line able to programme (transmission programmable levels position signal, represent this signal with FLAGA), FLAGB full scale will holding wire (the full flag bit signal of transmission FIFO, use FLAGB), and the empty marking signal line of FLAGC connects (the empty flag bit signal of transmission FIFO is used FLAGC).Here adopt the transmission design of subordinate fifo mode between the USB interface control module 24 of USB controller 4 and fpga chip 2, help the high rate data transmission of data.
Above content be in conjunction with concrete preferred implementation to further describing that the utility model is done, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field, under the prerequisite that does not break away from the utility model design, can also make some simple deduction or replace, all should be considered as belonging to protection range of the present utility model.
Claims (7)
1. a high-speed image sampling system is characterized in that: comprise imageing sensor, IMAQ and processing module, image memory module, and USB controller; Described imageing sensor adopts cmos sensor, and described data acquisition and processing (DAP) module adopts fpga chip, and described image memory module adopts the SDRAM chip; Described cmos sensor is connected with described fpga chip, and described SDRAM chip is connected with described fpga chip, and described USB controller is connected with described fpga chip.
2. high-speed image sampling according to claim 1 system, it is characterized in that: described fpga chip comprises main control module, sensor interface control module, USB interface control module and sdram controller module; Described sensor interface control module is connected with described cmos sensor and is connected with described main control module; Described USB interface control module is connected with described USB controller and is connected with described main control module; Described sdram controller module is connected with described SDRAM chip and is connected with described main control module.
3. high-speed image sampling according to claim 2 system, it is characterized in that: described main control module comprises Clock management module, command analysis and control module, Data Control module and FIFO; Described Clock management module is connected with each functional module on the described fpga chip and provides clock signal for being attached thereto each functional module that connects; Described command analysis is connected with described USB interface control module with control module and is connected with described sensor interface control module; Described Data Control module is connected with the sensor interface control module, is connected with described FIFO and is connected with described sdram controller module; Described FIFO comprises input FIFO and output FIFO, described input FIFO is connected with described sensor interface control module and is connected with described Data Control module, and described output FIFO is connected with described USB interface control module and is connected with described Data Control module.
4. high-speed image sampling according to claim 3 system, it is characterized in that: described sensor interface control module comprises I
2C interface control module and video interface control module; Described I
2The C interface control module is connected with described cmos sensor and is connected with control module with described command analysis; Described video interface control module is connected with described cmos sensor, is connected with described input FIFO and is connected with described Data Control module.
5. high-speed image sampling according to claim 4 system is characterized in that: described I
2The C interface control module is connected by SCLK clock line and SDATA data wire with described cmos sensor; Described video interface control module is connected by the capable useful signal line of LINE_VALID, FRAME_VALID frame useful signal line, PIX_CLK pixel clock line and PIX_DATA pixel data line with described cmos sensor.
6. high-speed image sampling according to claim 5 system is characterized in that: described USB controller, described USB interface control module, described command analysis and control module, described I
2C interface control module and described cmos sensor connect to form by configuration and the control channel of host computer to described cmos sensor; Described cmos sensor, described video interface control module, described input FIFO, described Data Control module, described sdram controller module, described SDRAM chip, described output FIFO, described USB interface control module and described USB controller connect to form the video Data Transmission passage.
7. high-speed image sampling according to claim 2 system is characterized in that: described USB interface control module is connected by DATA data/address bus, IFCLK interface clock line, SLOE enable signal line, SLRD reading signal lines, SLWR write signal line, FIFOADR bus select signal line, PKTEND bag ED holding wire, FLAGA marking signal line able to programme, FLAGB full scale will holding wire and the empty marking signal line of FLAGC with described USB controller.
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| CN2010206585213U CN201937742U (en) | 2010-12-14 | 2010-12-14 | High-speed image acquisition system |
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| CN2010206585213U CN201937742U (en) | 2010-12-14 | 2010-12-14 | High-speed image acquisition system |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819818A (en) * | 2012-08-14 | 2012-12-12 | 公安部第三研究所 | Method for realizing image processing based on dynamic reconfigurable technology of field programmable gate array (FPGA) chip |
| CN104065937A (en) * | 2014-06-20 | 2014-09-24 | 中国电子科技集团公司第四十四研究所 | Real-time high-speed image pre-processing method for CMOS image sensor |
| CN104363383A (en) * | 2014-10-16 | 2015-02-18 | 青岛歌尔声学科技有限公司 | Image pre-distortion correction method and device |
| CN104426851A (en) * | 2013-08-23 | 2015-03-18 | 北大方正集团有限公司 | Image signal transmission system and method |
| CN104462013A (en) * | 2014-06-26 | 2015-03-25 | 深圳奥比中光科技有限公司 | ASIC chip system special for optical three-dimensional sensing |
| CN106331452A (en) * | 2016-08-24 | 2017-01-11 | 宁波舜宇光电信息有限公司 | Device and method for performing image acquisition by utilizing synchronous slave SLAVEFIFO manner |
| CN106454023A (en) * | 2016-09-07 | 2017-02-22 | 北京凯视佳光电设备有限公司 | USB3.0 CMOS linear array industrial camera |
| CN106851183A (en) * | 2015-12-04 | 2017-06-13 | 宁波舜宇光电信息有限公司 | Multi-channel video processing system and method based on FPGA |
| CN104102601B (en) * | 2014-07-16 | 2017-10-10 | 西安电子科技大学 | A kind of image data acquiring storage system based on FPGA |
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2010
- 2010-12-14 CN CN2010206585213U patent/CN201937742U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819818A (en) * | 2012-08-14 | 2012-12-12 | 公安部第三研究所 | Method for realizing image processing based on dynamic reconfigurable technology of field programmable gate array (FPGA) chip |
| CN104426851A (en) * | 2013-08-23 | 2015-03-18 | 北大方正集团有限公司 | Image signal transmission system and method |
| CN104065937A (en) * | 2014-06-20 | 2014-09-24 | 中国电子科技集团公司第四十四研究所 | Real-time high-speed image pre-processing method for CMOS image sensor |
| CN104065937B (en) * | 2014-06-20 | 2016-01-13 | 中国电子科技集团公司第四十四研究所 | For the real time high-speed image pre-processing method of cmos image sensor |
| CN104462013A (en) * | 2014-06-26 | 2015-03-25 | 深圳奥比中光科技有限公司 | ASIC chip system special for optical three-dimensional sensing |
| CN104102601B (en) * | 2014-07-16 | 2017-10-10 | 西安电子科技大学 | A kind of image data acquiring storage system based on FPGA |
| CN104363383A (en) * | 2014-10-16 | 2015-02-18 | 青岛歌尔声学科技有限公司 | Image pre-distortion correction method and device |
| CN106851183A (en) * | 2015-12-04 | 2017-06-13 | 宁波舜宇光电信息有限公司 | Multi-channel video processing system and method based on FPGA |
| CN106851183B (en) * | 2015-12-04 | 2020-08-21 | 宁波舜宇光电信息有限公司 | Multi-channel video processing system and method based on FPGA |
| CN106331452A (en) * | 2016-08-24 | 2017-01-11 | 宁波舜宇光电信息有限公司 | Device and method for performing image acquisition by utilizing synchronous slave SLAVEFIFO manner |
| CN106454023A (en) * | 2016-09-07 | 2017-02-22 | 北京凯视佳光电设备有限公司 | USB3.0 CMOS linear array industrial camera |
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Granted publication date: 20110817 Termination date: 20121214 |