CN203522895U - SOPC (system-on-a-programmable-chip)-based binocular video stitching device - Google Patents

Abstract

The utility model discloses an SOPC (system-on-a-programmable-chip)-based binocular video stitching device. The SOPC-based binocular video stitching device comprises a video acquisition device, a video fusion device, a video transmission device and an upper computer, wherein a pair of CMOS (complementary metal-oxide-semiconductor transistor) image sensors is connected with a pair of binocular video acquisition modules through an FPGA (field programmable gate array) port respectively; the pair of binocular video acquisition modules is connected with a binocular video storage module; one path of the output end of the binocular video storage module is connected with a binocular video output module through a characteristic extraction co-processor, and the other path is connected with a binocular video display module; the binocular video output module is further connected with a NiosII processor and the upper computer respectively, and the binocular video display module is further connected with a VGA (video graphics array) display. The device combines an SOPC technology with an FPGA, and realizes a binocular synchronous video acquisition and real-time display system based on hardware-software co-design and taking the NiosII processor as a core; a DTFC (data transfer fast channel) composed of a DMA (direct memory access) controller and an Avalon-MM module is used for finishing video data acquisition and output, breaking the bottleneck of a processor and peripherals in data exchange, and realizing real-time binocular video stitching.

Description

Assembled the putting of binocular video based on SOPC

Technical field

The utility model relates to binocular vision technology, specifically a kind of binocular video splicing apparatus based on SOPC.

Background technology

Binocular vision technology, as the important component part of machine vision, is the study hotspot in the fields such as video-splicing, industrial detection and three-dimensional reconstruction always.In recent years along with the development of binocular vision technology, traditional solution based on video frequency collection card and host computer is because the shortcomings such as cost is high, versatility is poor, processing speed is slow cannot have been met consumers' demand, especially at binocular video, gather hop, no matter be to adopt poll or time-multiplexed mode, existing method for designing all cannot meet the designing requirement of system in synchronism and real-time.

Patent document " a kind of two-way video fusion processing unit and fusion method thereof based on SOPC " (patent No. CN102523389A) has proposed a kind of method that realizes two-way video fusion by SOPC system, but it still uses traditional method for designing, by the concurrency of FPGA and SOPC, the advantage in programmability is not brought into play, synchronism and real-time cannot guarantee, two-way video fusion is only used bilinear interpolation, and syncretizing effect is not good.

The most host computer of present stage binocular video splicing apparatus participates in processing, and cannot realize embedded binocular video splicing apparatus truly, and upper computer software is realized video-splicing algorithm again, and execution efficiency is not high, cannot balance in real-time and splicing effect.

Utility model content

The purpose of this utility model is intended to solve above-mentioned technological deficiency.

For this reason, the purpose of this utility model is to propose a kind of FPGA of take as the binocular video splicing apparatus of core based on SOPC, this device is controlled each functional module with the encapsulation of Avalon-MM modular form by NiosII soft-core processor, and the two-way video data collecting is spliced and shown in real time.

Binocular video splicing apparatus based on SOPC of the present utility model, comprise video acquisition device, video fusion device, video frequency transmitter and host computer, it is characterized in that: a pair of cmos image sensor is connected respectively with a pair of binocular video acquisition module by FPGA port; A pair of binocular video acquisition module connects binocular video memory module together; Binocular video memory module output Yi road is connected with binocular video output module through feature extraction coprocessor, and another road is connected with binocular video display module; Binocular video output module also connects respectively NiosII processor and host computer, and binocular video display module also connects VGA display.

Wherein, binocular video acquisition module mainly comprises cmos image sensor initialization controller and Avalon stream mode video acquisition controller, and the two connects by Avalon bus.A pair of binocular video acquisition module is connected to respectively a pair of cmos image sensor CMOS_1 and corresponding dma controller DMA_1 and the DMA_2 of CMOS_2.

Described binocular video display module mainly comprises VGA display timing generator generator and data cached asynchronous FIFO, and the two connects by Avalon bus; VGA display timing generator generator connects VGA display by D/A conversion chip.

Described binocular video output module mainly comprises asynchronous FIFO buffer and the Avalon stream mode video output controller being attached thereto.USB chip is connected with binocular video output module by FPGA port, and it is Slave FIFO slave mode that USB chip is set.

Described binocular video memory module is mainly corresponding two groups of dma controller DMA_1 and the DMA_2 with it of take that two SDRAM are core.Binocular video memory module is connected with two SDRAM by FPGA port.

Described feature is mentioned derived function module, interest value calculating and the non-maximum inhibition of the neighborhood module that coprocessor comprises low-pass filtering module and is linked in sequence thereafter;

Low pass filter blocks adopts the module after improving:

$(1/32)\×\left[\begin{array}{ccccc}0& 1& 1& 1& 0\\ 1& 2& 2& 2& 1\\ 1& 2& 4& 2& 1\\ 1& 2& 2& 2& 2\\ 0& 1& 1& 1& 0\end{array}\right],$

Derived function module adopts the differentiate template of X and Y-direction [1 ,-2,0,2,1] and [1 ,-2,0,2,1] ^t5 * 5 the template being merged into:

$\left[\begin{array}{ccccc}0& 0& -1& 0& 0\\ 0& 0& -2& 0& 0\\ -1& -2& 0& 2& 1\\ 0& 0& -2& 0& 0\\ 0& 0& 1& 0& 0\end{array}\right],$

The non-maximum inhibition of neighborhood 3 Line Buffer of module use of interest value and the d type flip flop array of 3 * 3.

The utility model is by SOPC (System on a Programmable Chip, programmable system on sheet) technology and FPGA (Field Programmable Gate Array, field programmable gate array) combine, binocular synchronization video acquisition and the real-time display system of the Hardware/Software Collaborative Design that a kind of Nios of take II processor is core have been proposed, by DMA (Direct Memory Access, direct memory access) controller and Avalon-MM (Avalon Memory Map, Avalon memory-mapped interface) DTFC (the Data Transfer Fast Channel that module forms, data fast transport passage) complete video data acquiring and output, abolish processor and be located at the bottleneck in exchanges data outward, realize the real-time splicing of binocular video.

Binocular video collector, by a pair of cmos image sensor, form binocular video acquisition module, cmos sensor is according to norm structure (canonical configuration) structural configuration, baseline overlaps with trunnion axis, the optical axis of transducer is parallel, and limit moves to unlimited distance, and polar curve is parallel, between two sensors, at a distance of 5-7 cm distance (imitating human eye spacing), binocular cmos sensor is connected with binocular video acquisition module by FPGA port.

Binocular video memory, the SDRAM that is 64MB by two capacity forms, adopt near-end disposing way in High-speed Board Design, two SDRAM are arranged in parallel on the position equidistant with FPGA, by FPGA port, be connected with binocular video memory module, as system running space and frame buffer (Frame Buffer).

Binocular video display, is connected by FPGA port with binocular video display module, by high-speed d/a conversion chip, two-way video data is converted to analog signal, exports VGA display to and shows.

Binocular video follower, USB2.0 equipment is connected with binocular video output module by FPGA port, it is Slave FIFO slave mode that USB2.0 equipment is set, FPGA can directly access the FIFO corresponding with read/write end points, mode is identical with the common FIFO of read/write, do not relate to any host-host protocol, FPGA produces the required driving signal of transfer of data, handshake (empty/full flag bit etc.) and enable signal as peripheral control unit, support hot plug, realize host computer to SOPC system initialization and acquired data storage.

Fpga core system, comprises fpga chip, EPCS16 memory and jtag interface, and the non-volatile assurance system of EPCS16 can normally be moved after powering on, and need not again download, and jtag interface is for downloading and debugging routine.

Binocular video acquisition module comprises imageing sensor initialization controller and Avalon stream mode video acquisition controller, gatherer process is controlled by NiosII processor, first processor sends sensor initializing signal, two cmos image sensors are carried out to initialization, start Avalon stream mode video acquisition controller and corresponding dma controller receiving after being initialized to function signal, two-way video-signal is gathered to the Framer Buffer to appointment, make full use of the concurrency of FPGA and the programmability of NiosII processor, realize synchronous acquisition and the real-time storage of two-way video data.

Binocular video memory module is mainly that to take two SDRAM be core, coordinate corresponding with it dma controller, realize the table tennis transmission of data, SDRAM can only carry out serial transmission as single port device, cannot data be gathered and be exported simultaneously, if use traditional table tennis Transmission Design method, binocular video transmission needs four SDRAM, and PCB layout difficulty is very big.The advantage of the design's application SOPC on controlled, two groups of dma controllers of operation (DMA_1, DMA_2) coordinate two SDRAM to realize the table tennis transmission of binocular video data.

Binocular video output module comprises asynchronous FIFO buffer and Avalon stream mode video output controller.Because SOPC system clock (120MHz) is higher than USB chip (CY7C68013A) clock (48MHz), so add asynchronous FIFO buffer temporal data, and in control module, introduce Backpressure (Back Push), the almost_full signal of asynchronous FIFO is sent to dma controller as back-pressure signal, dma controller is according to this signal terminating or continue transfer of data, for reaching USB chip maximum transmission rate, USB chip is set to Slave FIFO slave mode, Avalon stream mode video output controller produces and writes USB chip internal FIFO sequential as external piloting control device processed, handshake and output enable signal, its core is a finite state machine (Finite State Machine, FSM), video output module sends enabling signal at NiosII processor, after completing a frame two-way video-signal output, enter wait state, whole process completes automatically, processor is freed and is absorbed in system control from heavy output transmission, through reality, test, more than the output speed of system can reach 40MHz/s, can meet the requirement that host computer shows in real time.

Binocular video display module comprises controls the VGA display timing generator generator of video flowing output and data cached asynchronous FIFO, generation vertical synchronizing signal and the horizontal-drive signal correct according to VGA agreement, signal directly exports VGA display to through FPGA port, and R/G/B stitch data exports the analogue data end of VGA display to after the conversion of high-speed d/a chip.

The aspect that the utility model is additional and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present utility model.

Accompanying drawing explanation

Above-mentioned and/or the additional aspect of the utility model and advantage will become from the following description of the accompanying drawings of embodiments and obviously and easily understand, wherein:

Fig. 1 is the SOPC system connection diagram according to the utility model embodiment;

Fig. 2 is the data fast transport access diagram according to the utility model embodiment;

Fig. 3 is the binocular video acquisition module schematic diagram according to the utility model embodiment;

Fig. 4 is the binocular video acquisition module workflow diagram according to the utility model embodiment;

Fig. 5 is the binocular video display module schematic diagram according to the utility model embodiment;

Fig. 6 is the binocular video output module schematic diagram according to the utility model embodiment;

Fig. 7 controls schematic diagram according to the binocular video output module state of the utility model embodiment;

Fig. 8 is the feature extraction coprocessor schematic diagram according to the utility model embodiment.

Embodiment

Describe embodiment of the present utility model below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the utility model, and can not be interpreted as restriction of the present utility model.

It is core that this device be take the FPGA that a slice altera corp model is EP4CE15F17C8N; Comprise extremely circuit of image acquisition device that the OV7670CAMERACHIP of You Liangpian U.S. Hao Wei company (OmniVision) forms; The SDRAM that is MT48LC32M16A2 by Liang Pianmeigao company (MICRON) model forms, for the binocular video memory of two-way video data ping-pong buffer circuit extremely; The binocular video display being comprised of high-speed d/a chip ADV7123 and VGA interface is circuit extremely; The binocular video follower being comprised of Sai Pulasi (Cypress Semiconducto) the EZ-USB FX2LP family chip CY7C68013A of company and USB2.0 interface is circuit extremely; FPGA system peripherals circuit.

As shown in Figure 1, the input of binocular video memory module is connected with binocular video acquisition module, output is divided into two-way, one tunnel is connected with binocular video output module through feature extraction coprocessor, another road is connected with binocular video display module, NiosII processor, as the system core, completes each module initialization configuration and two buffer memory and controls.

As shown in Figure 2, data fast transport passage comprises binocular video memory module and is attached thereto the dma controller of connection module, two buffer memorys that NiosII processor is realized binocular video data by the destination address of operation dma controller transmit, thereby reach the object of large data fast transport.

As shown in Figure 3, in binocular video splicing apparatus based on SOPC of the present utility model, binocular video acquisition module mainly comprises OV7670 initialization controller and Avalon stream mode video acquisition controller, wherein OV7670 initialization controller is comprised of SCCB_Control module and OV7670_Config module, and gatherer process is controlled by NiosII processor.First processor sends OV7670 processor initializing signal, and two OV7670 imageing sensors are carried out to initialization; Start Avalon stream mode video acquisition controller and corresponding dma controller receiving after being initialized to function signal, two-way video-signal is gathered to the Framer Buffer to appointment; Module combines the concurrency of FPGA with the programmability of NiosII processor, given full play to software and hardware features, below the implementation procedure of each several part is specifically described.

SCCB_Control module produces the sequential of read-write cmos sensor register according to SCCB agreement, SCCB can be operated in (SIO_C under two-wire system pattern, SIO_D), two-wire system SCCB is a kind of I2C agreement of simplification, SIO_C is serial clock signal line, is equivalent to the SCL holding wire of I2C agreement; SIO_D is bidirectional linked list data signal line, is equivalent to the SDA holding wire of I2C agreement, and its work schedule and I2C agreement are basic identical.Typical SCCB bus read-write operation, first main frame sends a start bit, and then sends 8 from device address information, and last address information is read/write flag position (1 represents read operation, and 0 represents write operation); Receiving from device responds signal, 8 bit data are served to data wire, finally send position of rest signal.

OV7670 initialization controller application Verilog HDL hardware description language, according to SCCB bus timing write can be comprehensive Method at Register Transfer Level (RTL) program, OV7670 camera is carried out to initial configuration.OV7670 register address is 0x00～0xC9, introduces, and incite somebody to action in conjunction with test by research OV7670 user's manual and application scenarios, and the register that herein OV7670 need to be configured is condensed into 18, makes the layoutprocedure of OV7670 more clear.

OV7670 initialization controller comprises for generation of the SCCB_Control module of SCCB bus timing with for the OV7670_Config module of initialization of register.OV7670_Config, as top-level module, calls SCCB_Control according to the reiteration of required configuration register, data is write to the register of appointment.

As shown in Figure 4, binocular video acquisition module workflow, the startup of OV7670 initialization controller is passed through OV7670_CONFIG_START signal controlling by NiosII processor, after having configured, return to OV7670_CONFIG_FINISH signal, when NiosII processor receives that after two-way transducer configuration settling signal, system can start video acquisition.

Avalon stream mode video acquisition controller comprises video acquisition timing sequencer and asynchronous FIFO and controller two parts thereof.

Because the work clock (24MHz) of camera and the work clock (120MHz) of NiosII system are in different clock-domains.For guaranteeing two-way video data synchronism, prevent from occurring metastable state in synchronous RTL design, to single-bit control signal, as field (VSYNC), row (HREF), pixel (PCLK) signal can be used after two-stage trigger series connection synchronizer.

To multi-bit data signal, as OV7670 input data need to can be used after the asynchronous FIFO with Gray code address generator.After above-mentioned processing, the mean free error time of system (Mean Time Between Failures, MTBF) can be controlled in tolerance interval, guarantee system reliability and synchronism.

Video acquisition timing sequencer will be uploaded after the data encapsulation framing collecting according to OV7670 output timing, and VSYNC is frame synchronizing signal, and HREF is line synchronizing signal.When VSYNC rising edge being detected, indicate that a frame new image data arrives, trailing edge represents to start a frame image data collection; HREF is high level useful signal, when HREF being detected, is that high level and VSYNC are effective image data while being low level; PCLK is pixel synchronizing signal, and OV7670 exports a unit data at each PCLK trailing edge.When VSYNC is low level, HREF can export high level 480 times, and every frame data comprise 480 row; When HREF is high level, PCLK can export low level 640 times, and every column data comprises 640 pixels; When VSYNC signal occurs again, represent frame VGA (640 * 480) view data end of output, indicate that the output of next frame data starts simultaneously.

Video acquisition module is after completing the configuration of OV7670 imageing sensor, can first receive 20 frame image datas, then just to NiosII processor, send configuration settling signal, this is that view data after this is just thought to stablize available because imageing sensor existed for 10～15 unstable signal periods of frame.

Utilize row (HREF)/frame (VSYNS) synchronizing signal and pixel clock (PCLK) according to the data format of RGB565, the vision signal collecting is carried out to Pixel-level splicing, former and later two 8bit data are spliced into the pixel data of 16 RGB565 forms.Pixel splicing has reduced the read-write number of times of Avalon bus to FIFO, has reduced follow-up data and has processed complexity.

Two parts of packaged video acquisition module exampleizations, are connected to respectively the dma controller that CMOS1/CMOS2 is corresponding.Video acquisition module is as Avalon primary module, under NiosII program control, two-way video data is synchronously uploaded in video storage module to Framer_Buffer separately, compared to traditional PIO transmission, processor is only responsible for configuration dma controller, and whole data transmission procedure is completed automatically by transfer of data express passway, due to the work clock of the SOPC system pixel clock higher than cmos image sensor, so dma controller remains enabled state in transmitting procedure, these are slightly different from the dma controller state of video data output below, there is not the back-pressure of Avalon-MM module to dma controller.

As shown in Figure 5, binocular video display module comprises controls the VGA display timing generator generator of video flowing output and data cached asynchronous FIFO, below the implementation procedure of each several part is specifically described.

VGA (640 * 480) display mode regulation, every frame signal comprises 525 row, the effective display line of 480 behavior wherein, every frame data are synchronous by VSync signal, and VSync is that width is the low level pulse of 2 line periods; Every row signal comprises 800 pixels, and wherein 640 is effective display pixel, and the low level pulse that each row of data is 96 clock cycle by a width is synchronous.Use VerilogHDL design for VSync signal and HSync signal condition machine, by counter, produce the redirect condition between a state.

The generation method of the generation method of Avalon video display controller and Avalon video acquisition control module is similar, main difference is the output port as video data, SOPC system works frequency is higher than the clock frequency of VGA display, and asynchronous FIFO buffer memory cannot be accomplished buffer memory one frame partial data in sheet, if thereby this just causes in data output procedure not and FIFO buffer memory to be done to corresponding processing will produce and overflow the loss that causes video data, for this situation, in design, added Backpressure, by expiring and the dma controller that spacing wave (almost_full/almost_empty) back-pressure is connected with video display controller of asynchronous FIFO, make dma controller (almost_full signal is 1) when FIFO is about to be fully written, automatically stop data output, wait for that when FIFO is about to be read sky, (almost_empty signal is 1) just continues output data, thereby realize the efficient automatic transmission of video data.

As shown in Figure 6, binocular video output module comprises asynchronous FIFO buffer and Avalon stream mode video output controller.Because system clock (120MHz) is higher than USB chip (CY7C68013A) clock (48MHz), so add asynchronous FIFO buffer temporal data.According to video signal data flow transmission feature, after the interior resource of balance FPGA and data transmission bauds, adopting width is that 16 degree of depth are that the asynchronous FIFO of 4096Byte is as buffer memory, and in control module, introduce Backpressure (Back Push), the almost_full signal of asynchronous FIFO is sent to dma controller as back-pressure signal, and dma controller is according to this signal terminating or continue transfer of data.

As shown in Figure 7, in order to reach maximum transmission rate, CY7C68013A is set to Slave FIFO slave mode.Avalon stream mode video output controller produces and writes the inner FIFO sequential of FX2, handshake and output enable signal as external piloting control device processed, and its core is a finite state machine (Finite State Machine, FSM).

The encapsulation process of video output module is to two modules are similar above, video output module through encapsulation is received after the video output order that host computer sends at NiosII processor, two-way video-signal is uploaded through USB2.0 bus, whole process completes automatically, thereby being freed from heavy transfer of data, processor is absorbed in system control, through reality test, more than the output speed of system can reach 40MHz/s, can meet the requirement that host computer shows in real time.

As shown in Figure 8, feature is mentioned coprocessor, comprise that low-pass filtering module, derived function module, interest value are calculated and the non-maximum of neighborhood suppresses module, first by filtration module, reduce noise jamming, then by calculating pixel, put at the gradiometer of X and Y both direction and calculate point of interest, finally by value calculating and the non-maximum of neighborhood suppress to obtain Harris angle point perhaps.

For reaching the object that improves Harris hardware algorithm realizability and reduce FPGA resource overhead, the utility model improves low pass filter operator template, and the template after improvement is:

$(1/32)\×\left[\begin{array}{ccccc}0& 1& 1& 1& 0\\ 1& 2& 2& 2& 1\\ 1& 2& 4& 2& 1\\ 1& 2& 2& 2& 2\\ 0& 1& 1& 1& 0\end{array}\right]$

The circular configuration noise immunity of the template approximate Gaussian filter after improvement is better, can meet algorithm and suppress the requirement to template on noise, coefficients after simultaneously optimizing all can realize by the displacement of register the function of divider, makes algorithm more meet hardware and realize rule when reducing design difficulty and resource overhead.

In order further to improve algorithm performance, in design by the differentiate template of X and Y-direction [1 ,-2,0,2,1] and [1 ,-2,0,2,1] ^t, merge into the template of 5 * 5 and calculate template:

$\left[\begin{array}{ccccc}0& 0& -1& 0& 0\\ 0& 0& -2& 0& 0\\ -1& -2& 0& 2& 1\\ 0& 0& -2& 0& 0\\ 0& 0& 1& 0& 0\end{array}\right]$

The non-maximum of neighborhood of interest value suppresses, the non-maximum inhibition of neighborhood of interest value and above implementation there are differences, it is to complete in the neighborhood of 3 * 3 that the non-maximum of the neighborhood of interest value suppresses, and only need to use 3 Line Buffer and one 's 3 * 3 d type flip flop array in design.The implementation of Data Update part is with identical above, and video data passes in and out three end to end Line Buffer by unit, enters d type flip flop array with the unit of classifying as simultaneously.The data at d type flip flop center compare respectively at its 8 adjacent region datas, if be greater than, export a high level signal, if the data in d type flip flop center are greater than its whole 8 adjacent region datas, this data point is angle point, record this point coordinates, and export the high level of a Cycle.

Although illustrated and described embodiment of the present utility model, for the ordinary skill in the art, be appreciated that in the situation that not departing from principle of the present utility model and spirit and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present utility model is by claims and be equal to and limit.

Claims (6)

1. the binocular video splicing apparatus based on SOPC, comprises video acquisition device, video fusion device, video frequency transmitter and host computer, it is characterized in that: a pair of cmos image sensor is connected respectively with a pair of binocular video acquisition module by FPGA port; A pair of binocular video acquisition module connects binocular video memory module together; Binocular video memory module output Yi road is connected with binocular video output module through feature extraction coprocessor, and another road is connected with binocular video display module; Binocular video output module also connects respectively NiosII processor and host computer, and binocular video display module also connects VGA display.

2. according to the device of claim 1, it is characterized in that: a pair of binocular video acquisition module is connected to respectively a pair of cmos image sensor CMOS_1 and corresponding dma controller DMA_1 and the DMA_2 of CMOS_2; Binocular video acquisition module mainly comprises cmos image sensor initialization controller and Avalon stream mode video acquisition controller, and the two connects by Avalon bus.

3. according to the device of claim 1, it is characterized in that: binocular video display module mainly comprises VGA display timing generator generator and data cached asynchronous FIFO, and the two connects by Avalon bus; VGA display timing generator generator connects VGA display by D/A conversion chip.

4. according to the device of claim 1, it is characterized in that: USB chip is connected with binocular video output module by FPGA port, and it is Slave FIFO slave mode that USB chip is set; Binocular video output module mainly comprises asynchronous FIFO buffer and the Avalon stream mode video output controller being attached thereto.

5. according to the device of claim 1, it is characterized in that: binocular video memory module is connected with two SDRAM by FPGA port; Binocular video memory module is mainly corresponding two groups of dma controller DMA_1 and the DMA_2 with it of take that two SDRAM are core.

6. according to the device of claim 1, it is characterized in that: feature is mentioned derived function module, interest value calculating and the non-maximum inhibition of the neighborhood module that coprocessor comprises low-pass filtering module and is linked in sequence thereafter; Low pass filter blocks adopts the module after improving:

$(1/32)\×\left[\begin{array}{ccccc}0& 1& 1& 1& 0\\ 1& 2& 2& 2& 1\\ 1& 2& 4& 2& 1\\ 1& 2& 2& 2& 2\\ 0& 1& 1& 1& 0\end{array}\right],$

Derived function module adopts the differentiate template of X and Y-direction [1 ,-2,0,2,1] and [1 ,-2,0,2,1] ^t5 * 5 the template being merged into:

$\left[\begin{array}{ccccc}0& 0& -1& 0& 0\\ 0& 0& -2& 0& 0\\ -1& -2& 0& 2& 1\\ 0& 0& -2& 0& 0\\ 0& 0& 1& 0& 0\end{array}\right],$

The non-maximum inhibition of neighborhood 3 Line Buffer of module use of interest value and the d type flip flop array of 3 * 3.

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