CN209881907U

CN209881907U - Image acquisition equipment based on FPGA

Info

Publication number: CN209881907U
Application number: CN201921098322.9U
Authority: CN
Inventors: 黄新俊
Original assignee: Nanjing Yunge Information Technology Co Ltd
Current assignee: Nanjing Yunge Information Technology Co Ltd
Priority date: 2019-07-15
Filing date: 2019-07-15
Publication date: 2019-12-31
Anticipated expiration: 2029-07-15

Abstract

The utility model discloses an image acquisition equipment based on FPGA, including real-time image acquisition system and FPGA treater, real-time image acquisition system and FPGA treater data connection, real-time image acquisition system is including the initialization module that is used for setting for image sensor mode of operation, the storage control module that is used for providing control signal's sampling control module and is used for carrying out the storage to the image data of image sensor output. The utility model discloses in, adopt static memory cell to accomplish the quick read-write of image data, image sensor writes into image data when first memory cell and second memory cell simultaneously and the FPGA treater is when reading the data in first memory cell and the second memory cell, and first memory cell and second memory cell read and write in turn, avoid the read-write conflict of the same address of a chip, realize the rapid processing of image data, accomplish the collection of image.

Description

Image acquisition equipment based on FPGA

Technical Field

The utility model relates to an image acquisition equipment field specifically is an image acquisition equipment based on FPGA.

Background

The FPGA, namely a field programmable array, is a product developed on the basis of a programmable device, and has great advantages in video processing because of the high processing speed of the FPGA, so that the FPGA is widely applied in the field of image videos, and has greater application value compared with a traditional image processing chip adopting a DSP.

Therefore, the image acquisition equipment based on the FPGA is provided.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an image acquisition equipment based on FPGA to it is slow to solve traditional image processing equipment real-time image processing speed, and improves the problem of image processing effect.

In order to achieve the above object, the utility model provides a following technical scheme: the utility model provides an image acquisition equipment based on FPGA, includes real-time image acquisition system and FPGA treater, real-time image acquisition system and FPGA treater data connection, real-time image acquisition system is including the initialization module that is used for setting for image sensor mode, be used for providing control signal's sampling control module for image sensor and be used for carrying out the storage control module that saves to the image data of image sensor output, the FPGA treater includes filtering module and the phase-locked loop circuit who is used for sending control signal for sampling control module, data among the storage control module are passed through filtering module and are transmitted to FPGA treater inside.

Preferably, an a/D conversion circuit is integrated inside the image sensor, and an analog signal output by the image sensor is converted into a digital signal by the a/D conversion circuit and stored in the storage control module, wherein the model of the image sensor is a complementary metal oxide semiconductor OV 9121.

Preferably, the storage control module comprises a first storage unit and a second storage unit, and the image data output ends of the first storage unit and the second storage unit are both connected with the image data input end of the FPGA processor.

Preferably, only one of the first storage unit and the second storage unit outputs data to the FPGA processor at the same time, and the other is read-disabled.

Preferably, the first storage unit and the second storage unit have only one write-in of image data output from the image sensor at the same time, and the other write-inhibit.

Preferably, the first storage unit and the second storage unit are both static memories, and the models of the first storage unit and the second storage unit are 6264(8 KB).

Preferably, the data signal of the FPGA processor is written into the third storage unit, and the third storage unit is a dynamic memory.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses in, adopt static memory cell to accomplish the quick read-write of image data, image sensor writes into image data when first memory cell and second memory cell simultaneously and the FPGA treater is when reading the data in first memory cell and the second memory cell, first memory cell and second memory cell are respectively in image sensor and FPGA treater, and first memory cell and second memory cell read and write in turn, avoid the read-write conflict of the same address of a chip, realize the rapid processing of image data, accomplish the collection of image.

Description of the drawings:

in order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a block diagram of the present invention;

fig. 2 is a schematic structural diagram of the present invention.

In the figure: 1. a real-time image acquisition system; 101. initializing a module; 102. a sampling control module; 103. a storage control module; 104. an A/D conversion circuit; 105. a first storage unit; 106. a second storage unit; 2. an FPGA processor; 201. a filtering module; 202. a phase-locked loop circuit; 3. an image sensor; 4. and a third storage unit.

The specific implementation mode is as follows:

the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-2, the present invention provides an embodiment: the utility model provides an image acquisition equipment based on FPGA, including real-time image acquisition system 1 and FPGA treater 2, real-time image acquisition system 1 and FPGA treater 2 data connection, real-time image acquisition system 1 includes the initialization module 101 that is used for setting for image sensor 3 mode, a sampling control module 102 that is used for providing control signal for image sensor 3 and the storage control module 103 that is used for carrying out the storage to the image data of image sensor 3 output, FPGA treater 2 includes filtering module 201 and is used for sending the phase-locked loop circuit 202 of control signal for sampling control module 102, data in the storage control module 103 are transmitted to FPGA treater 2 inside through filtering module 201, write the image data that real-time image acquisition system 1 gathered into FPGA treater 2, be the quick reading to image data.

An a/D conversion circuit 104 is integrated inside the image sensor 3, an analog signal output by the image sensor 3 is converted into a digital signal through the a/D conversion circuit 104 and stored in the storage control module 103, the model of the image sensor 3 is a complementary metal oxide semiconductor OV9121, and auxiliary circuits such as the a/D conversion circuit 104 are integrated inside a chip by using the process compatibility of the image sensor 3(CMOS), so that circuit simplification, power consumption reduction and higher controllability are realized.

The storage control module 103 comprises a first storage unit 105 and a second storage unit 106, the image data output ends of the first storage unit 105 and the second storage unit 106 are both connected with the image data input end of the FPGA processor 2, only one of the first storage unit 105 and the second storage unit 106 outputs data to the FPGA processor 2 at the same time, and the other is read-prohibited, only one of the first storage unit 105 and the second storage unit 106 writes image data output by the image sensor 3 at the same time, and the other is write-prohibited, the first storage unit 105 and the second storage unit 106 are both static memories, and the models of the first storage unit 105 and the second storage unit 106 are both 62648KB, because the access time of the static memories is short, the bus utilization rate is high, so that the cached image data can be quickly written into the FPGA processor 2, and the image data can be quickly written, the first storage unit 105 and the second storage unit 106 are used for alternately writing and reading, so that image data output by the image sensor 3 can be continuously stored in the off-chip memory, and the FPGA processor 2 can continuously read data from the off-chip memory and can also avoid read-write collision of the same address of one chip.

The data signal of the FPGA processor 2 is written into the third storage unit 4, the third storage unit 4 is a dynamic memory, the processed image data is directly stored in the third storage unit 4, the processed image data is stored by utilizing the large capacity of the dynamic memory, and the workload of the static memory is reduced.

The working principle is as follows: the image sensor 3 works, analog signals are converted into image data through the A/D conversion circuit 104 and the image data are written into the storage control module 103, the data of the storage control module 103 are read by the FPGA processor 2, when the image data are written into the storage control module 103 and the FPGA processor 2 reads the image data in the storage control module 103, the first storage unit 105 and the second storage unit 106 in the storage control module 103 alternately realize reading and writing, meanwhile, the image data read by the FPGA processor 2 are processed through the filtering module 201, after the FPGA processor 2 finishes the processing of one frame of image, control signals are sent to the sampling control module 102 through the phase-locked loop circuit 202, the sampling control module 102 adjusts the image sensor 3 according to the received control signals, and the working mode of the image sensor 3 is preset through the initialization module 101.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. The image acquisition equipment based on the FPGA comprises a real-time image acquisition system (1) and an FPGA processor (2), and is characterized in that the real-time image acquisition system (1) is in data connection with the FPGA processor (2);

the real-time image acquisition system (1) comprises an initialization module (101) for setting the working mode of the image sensor (3), a sampling control module (102) for providing a control signal for the image sensor (3) and a storage control module (103) for storing image data output by the image sensor (3);

the FPGA processor (2) comprises a filtering module (201) and a phase-locked loop circuit (202) used for sending a control signal to the sampling control module (102), and data in the storage control module (103) is transmitted to the interior of the FPGA processor (2) through the filtering module (201).

2. The FPGA-based image acquisition device according to claim 1, wherein an A/D conversion circuit (104) is integrated in the image sensor (3), and an analog signal output by the image sensor (3) is converted into a digital signal by the A/D conversion circuit (104) and stored in the storage control module (103), wherein the model of the image sensor (3) is a complementary metal oxide semiconductor OV 9121.

3. The FPGA-based image acquisition device of claim 1, wherein the storage control module (103) comprises a first storage unit (105) and a second storage unit (106), and image data output ends of the first storage unit (105) and the second storage unit (106) are connected with an image data input end of the FPGA processor (2).

4. An FPGA-based image acquisition device according to claim 3, characterized in that only one of the first (105) and second (106) storage units outputs data to the FPGA processor (2) at a time, and the other is read-disabled.

5. An FPGA-based image capture device according to claim 3, wherein the first (105) and second (106) storage units only write image data output by the image sensor (3) one at a time, and the other write is disabled.

6. The FPGA-based image acquisition device of claim 3, wherein the first storage unit (105) and the second storage unit (106) are both static memories, and the first storage unit (105) and the second storage unit (106) are both 6264(8 KB).

7. An FPGA-based image capturing device according to claim 1, wherein the data signals of the FPGA processor (2) are written into a third storage unit (4), and the third storage unit (4) is a dynamic memory.