CN111601014A - Image processing and transmitting method and system - Google Patents
Image processing and transmitting method and system Download PDFInfo
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- CN111601014A CN111601014A CN201910126354.3A CN201910126354A CN111601014A CN 111601014 A CN111601014 A CN 111601014A CN 201910126354 A CN201910126354 A CN 201910126354A CN 111601014 A CN111601014 A CN 111601014A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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Abstract
The application discloses an image processing and transmitting method, which comprises the following steps: acquiring a transmission signal of the image sensor by using the FPGA chip; performing first processing on the transmission signal through the FPGA chip to obtain a first processing signal; acquiring the first processing signal by using a DSP chip; performing second processing on the first processing signal through the DSP chip to obtain a second processing signal; and transmitting the second processing signal to an upper computer. The FPGA chip and the DSP chip are combined in the application, the FPGA chip and the DSP chip are flexible in programming and strong in expansibility when the FPGA chip and the DSP chip work cooperatively, and the image can be timely and efficiently processed in the face of the requirements of high throughput data and high-speed real-time transmission. Correspondingly, the application also discloses an image processing transmission system with the same beneficial effect.
Description
Technical Field
The invention relates to the technical field of high-speed industrial cameras, in particular to an image processing and transmitting method and system.
Background
With the rapid development of industrial automation, the application scenarios of industrial cameras become very common. In the field of computer vision, in order to shoot clear images, a high-frame-rate and high-resolution technology is adopted, which has high technical requirements on acquisition and storage technologies of a camera system. Therefore, in the industrial camera system, the configuration of the image sensor, the processing and transmission of the image data all need to be performed by a special image processing board.
Image acquisition and transmission systems in the existing market are generally divided into three categories according to the category of controllers: a controller using an Application Specific Integrated Circuit (ASIC) chip for a Specific purpose, a controller using an FPGA (Field-Programmable Gate Array) chip alone, and a controller using a DSP (Digital Signal Processing) chip alone.
The ASIC chip has the defects of very long design period, incapability of being applied in large batch, high manufacturing cost, single function and poor flexibility of a constructed system, and once the ASIC chip is put into use, the ASIC chip can only be realized by redesigning the chip to realize new technology and algorithm, so that the universality of the ASIC chip is poor; in an image acquisition system which independently adopts a DSP (digital signal processor), because the DSP is realized by software programming and the execution mode is serial, the processing efficiency is greatly reduced when the requirement of high-speed real-time transmission of high-throughput data is met; in an image acquisition system which independently adopts the FPGA, the FPGA is used as a hardware programming array, and the image processing algorithm which is good in software is difficult to realize.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides an image processing and transmitting method and system, so as to realize image processing and transmitting efficiently in time. The specific scheme is as follows:
an image processing transmission method, comprising:
acquiring a transmission signal of the image sensor by using the FPGA chip;
performing first processing on the transmission signal through the FPGA chip to obtain a first processing signal;
acquiring the first processing signal by using a DSP chip;
performing second processing on the first processing signal through the DSP chip to obtain a second processing signal;
and transmitting the second processing signal to an upper computer.
Preferably, the process of performing the first processing on the transmission signal through the FPGA chip to obtain a first processing signal specifically includes:
and carrying out word position correction and image reconstruction on the transmission signal through the FPGA chip to obtain a first processing signal.
Preferably, the process of performing the second processing on the first processed signal through the DSP chip to obtain a second processed signal specifically includes:
and carrying out image recognition and picture compression on the first processing signal through the DSP chip to obtain a second processing signal.
Preferably, the process of acquiring the transmission signal of the image sensor by using the FPGA chip specifically includes:
acquiring the transmission signal sent by the image sensor through an LVDS bus by using the FPGA chip;
the process of acquiring the first processing signal by using the DSP chip specifically includes:
and acquiring the first processing signal sent by the FPGA chip through an SRIO bus by using the DSP chip.
Preferably, before the acquiring the transmission signal of the image sensor by using the FPGA chip, the method further includes:
acquiring configuration information of the upper computer by using the DSP chip and sending the configuration information to the FPGA chip;
and configuring the image sensor through the FPGA chip according to the configuration information.
Preferably, the process of acquiring the configuration information of the upper computer by using the DSP chip and sending the configuration information to the FPGA chip specifically includes:
acquiring configuration information of the upper computer by using the DSP chip, and sending the configuration information to the FPGA chip through an SRIO bus;
the process of configuring the image sensor by the FPGA chip according to the configuration information specifically includes:
and configuring the image sensor according to the configuration information through the FPGA chip and the SPI.
Preferably, the image sensor is specifically an area array image sensor.
Correspondingly, the invention also discloses an image processing and transmitting system, which comprises:
acquiring a transmission signal of an image sensor, and performing first processing on the transmission signal to obtain an FPGA chip of a first processing signal;
and acquiring the first processing signal, performing second processing on the first processing signal to obtain a second processing signal, and transmitting the second processing signal to a DSP chip of an upper computer.
Preferably, the image processing transmission system further includes:
the LVDS bus is connected with the image sensor and the FPGA chip;
and the SRIO bus is used for connecting the FPGA chip and the DSP chip.
Preferably, the image processing transmission system further includes:
and connecting the FPGA chip and the SPI of the image sensor.
The invention discloses an image processing and transmitting method, which comprises the following steps: acquiring a transmission signal of the image sensor by using the FPGA chip; performing first processing on the transmission signal through the FPGA chip to obtain a first processing signal; acquiring the first processing signal by using a DSP chip; performing second processing on the first processing signal through the DSP chip to obtain a second processing signal; and transmitting the second processing signal to an upper computer. The FPGA chip and the DSP chip are combined, and are flexible in programming and strong in expansibility when working cooperatively, and the image can be processed timely and efficiently in the face of the requirements of high-throughput data and high-speed real-time transmission.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flowchart illustrating steps of an image processing transmission method according to an embodiment of the present invention;
fig. 2 is a structural distribution diagram of an image processing transmission system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses an image processing and transmitting method, which is shown in figure 1 and comprises the following steps:
s1: acquiring a transmission signal of the image sensor by using an FPGA (Field Programmable gate Array) chip;
specifically, the acquiring process in step S1 is implemented by connecting an LVDS (Low-Voltage Differential Signaling) bus between the FPGA chip and the image sensor, that is: and acquiring the transmission signal sent by the image sensor through an LVDS bus by using the FPGA chip.
It is understood that the image sensor in the present embodiment is selected as an area array sensor according to the structure, and a specific type may be selected as a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
The transmission signal specifically comprises an image signal of the image sensor, a synchronization signal matched with the image signal and a pixel clock signal, and is sent to the FPGA chip through the LVDS bus.
S2: performing first processing on the transmission signal through the FPGA chip to obtain a first processing signal;
it will be appreciated that FPGA chips are provided with a large number of gate logic and flip-flops within them and have the advantage of parallel computing. The method comprises the steps that by utilizing the advantages of large scale, high integration level, high processing speed, high execution efficiency, flexibility, convenience and simplicity in programming and repeated programming, a transmission signal is subjected to first processing through the FPGA chip, wherein the first processing specifically comprises the steps of operating a word position correction algorithm and an image reconstruction algorithm to realize word position correction and image reconstruction, and the method also comprises other image algorithms realized by utilizing the programming advantages of the FPGA chip;
further, in the present embodiment, a high-end FPGA chip of Kintex-7 series of Xilinx is preferable for the model selection of the FPGA chip.
S3: acquiring the first processing Signal by using a DSP (Digital Signal Processor) chip;
specifically, the obtaining process of step S3 is implemented by an SRIO bus connecting the FPGA chip and the DSP chip, that is: and the DSP chip is used for acquiring the first processing signal sent by the FPGA chip through a serial fast input/output (SRIO) bus.
S4: performing second processing on the first processing signal through the DSP chip to obtain a second processing signal;
it can be understood that the DSP chip is implemented by software programming, the second processing specifically includes running an image recognition algorithm and a picture compression algorithm to perform image recognition and picture compression, and the collected image is compressed into a JPG format for subsequent uploading to an upper computer for display.
Specifically, the type of the DSP chip in this embodiment is preferably TMS320C6678 from TI corporation.
S5: and transmitting the second processing signal to an upper computer.
The embodiment of the invention discloses an image processing and transmitting method, which comprises the following steps: acquiring a transmission signal of the image sensor by using the FPGA chip; performing first processing on the transmission signal through the FPGA chip to obtain a first processing signal; acquiring the first processing signal by using a DSP chip; performing second processing on the first processing signal through the DSP chip to obtain a second processing signal; and transmitting the second processing signal to an upper computer. The FPGA chip and the DSP chip are combined, and are flexible in programming and strong in expansibility when working cooperatively, and the image can be processed timely and efficiently in the face of the requirements of high-throughput data and high-speed real-time transmission.
The embodiment of the invention discloses a specific image processing and transmitting method, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme. Specifically, before the step S1 of acquiring the transmission signal of the image sensor by using the FPGA chip, the method further includes:
acquiring configuration information of the upper computer by using the DSP chip and sending the configuration information to the FPGA chip;
and configuring the image sensor through the FPGA chip according to the configuration information.
The method comprises the following steps that the DSP chip is utilized to acquire the configuration information of the upper computer and send the configuration information to the FPGA chip, and specifically comprises the following steps:
acquiring configuration information of the upper computer by using the DSP chip, and sending the configuration information to the FPGA chip through an SRIO bus;
similarly, the process of configuring the image sensor by the FPGA chip according to the configuration information specifically includes:
and configuring the image sensor according to the configuration information through the FPGA chip and the SPI.
It is understood that the present embodiment is a configuration action of the image sensor before the image processing transmission. Specifically, the DSP chip obtains configuration information transmitted by the host computer through the network Interface, and then transmits the configuration information to the FPGA chip through the SRIO bus, and the FPGA chip configures the internal register of the image sensor through the SPI (Serial Peripheral Interface) of the image sensor.
Correspondingly, the embodiment of the present invention further discloses an image processing and transmitting system, as shown in fig. 2, including:
acquiring a transmission signal of an image sensor, and performing first processing on the transmission signal to obtain an FPGA chip 1 of a first processing signal;
and acquiring the first processing signal, performing second processing on the first processing signal to obtain a second processing signal, and transmitting the second processing signal to a DSP chip 2 of an upper computer.
The first processing specifically includes word position correction and image reconstruction, and the second processing specifically includes running an image recognition algorithm and compressing pictures.
Further, the image processing transmission system further includes:
an LVDS bus 3 connecting the image sensor and the FPGA chip;
and the SRIO bus 4 is used for connecting the FPGA chip and the DSP chip.
Further, the image processing transmission system further includes:
and the SPI 5 is used for connecting the FPGA chip and the image sensor.
In addition, the FPGA chip is connected to the image sensor through a GPIO (General Purpose input/output), so as to implement power-on management of the image sensor.
In a preferred embodiment, the model of the FPGA chip can be selected from a high-end FPGA chip of Kintex-7 series of Xilinx corporation, and the model of the DSP chip can be selected from TMS320C6678 of TI corporation.
The image processing transmission system in the embodiment can be provided with the gigabit network port, has strong reliability and strong expansibility, and can better solve the portability problem of the system.
The image processing transmission system in the embodiment is verified by matching actual items with corresponding software systems, and the result shows that the image processing transmission system can complete the technical requirements of image data transmission at a speed of 90 frames per second and high frame frequency load.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The image processing and transmitting method and system provided by the present invention are described in detail above, and a specific example is applied in the text to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. An image processing transmission method, comprising:
acquiring a transmission signal of the image sensor by using the FPGA chip;
performing first processing on the transmission signal through the FPGA chip to obtain a first processing signal;
acquiring the first processing signal by using a DSP chip;
performing second processing on the first processing signal through the DSP chip to obtain a second processing signal;
and transmitting the second processing signal to an upper computer.
2. The image processing transmission method according to claim 1, wherein the process of performing the first processing on the transmission signal by the FPGA chip to obtain a first processed signal specifically includes:
and carrying out word position correction and image reconstruction on the transmission signal through the FPGA chip to obtain a first processing signal.
3. The image processing transmission method according to claim 2, wherein the second processing of the first processed signal by the DSP chip to obtain a second processed signal specifically includes:
and carrying out image recognition and picture compression on the first processing signal through the DSP chip to obtain a second processing signal.
4. The image processing transmission method according to claim 1,
the process of acquiring the transmission signal of the image sensor by using the FPGA chip specifically comprises the following steps:
acquiring the transmission signal sent by the image sensor through an LVDS bus by using the FPGA chip;
the process of acquiring the first processing signal by using the DSP chip specifically includes:
and acquiring the first processing signal sent by the FPGA chip through an SRIO bus by using the DSP chip.
5. The image processing transmission method according to any one of claims 1 to 4, further comprising, before the acquiring the transmission signal of the image sensor by using the FPGA chip:
acquiring configuration information of the upper computer by using the DSP chip and sending the configuration information to the FPGA chip;
and configuring the image sensor through the FPGA chip according to the configuration information.
6. The image processing transmission method according to claim 5,
the process of acquiring the configuration information of the upper computer by using the DSP chip and sending the configuration information to the FPGA chip specifically comprises the following steps:
acquiring configuration information of the upper computer by using the DSP chip, and sending the configuration information to the FPGA chip through an SRIO bus;
the process of configuring the image sensor by the FPGA chip according to the configuration information specifically includes:
and configuring the image sensor according to the configuration information through the FPGA chip and the SPI.
7. The image processing transmission method according to claim 6, wherein the image sensor is an area array image sensor.
8. An image processing transmission system, comprising:
acquiring a transmission signal of an image sensor, and performing first processing on the transmission signal to obtain an FPGA chip of a first processing signal;
and acquiring the first processing signal, performing second processing on the first processing signal to obtain a second processing signal, and transmitting the second processing signal to a DSP chip of an upper computer.
9. The image processing transmission system according to claim 8, further comprising:
the LVDS bus is connected with the image sensor and the FPGA chip;
and the SRIO bus is used for connecting the FPGA chip and the DSP chip.
10. The image processing transmission system according to claim 8 or 9, further comprising:
and connecting the FPGA chip and the SPI of the image sensor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910126354.3A CN111601014A (en) | 2019-02-20 | 2019-02-20 | Image processing and transmitting method and system |
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| CN201910126354.3A CN111601014A (en) | 2019-02-20 | 2019-02-20 | Image processing and transmitting method and system |
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| CN108037138A (en) * | 2017-12-23 | 2018-05-15 | 陕西科技大学 | A kind of web inspection system and detection method for being used to detect the two-sided defect of paper |
| CN108154494A (en) * | 2017-12-25 | 2018-06-12 | 北京航空航天大学 | A kind of image fusion system based on low-light and infrared sensor |
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- 2019-02-20 CN CN201910126354.3A patent/CN111601014A/en active Pending
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| CN101783008A (en) * | 2009-10-13 | 2010-07-21 | 上海海事大学 | Real-time processing platform for ultra high resolution remote sensing images based on functions of FPGA and DSP |
| JP2011223194A (en) * | 2010-04-07 | 2011-11-04 | Hitachi Kokusai Electric Inc | Camera device |
| CN104811597A (en) * | 2015-04-27 | 2015-07-29 | 江苏中科贯微自动化科技有限公司 | Integrated smart camera |
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