CN110460735A - Large format scanner control system based on line array CCD - Google Patents
Large format scanner control system based on line array CCD Download PDFInfo
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- CN110460735A CN110460735A CN201910715912.XA CN201910715912A CN110460735A CN 110460735 A CN110460735 A CN 110460735A CN 201910715912 A CN201910715912 A CN 201910715912A CN 110460735 A CN110460735 A CN 110460735A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/00127—Connection or combination of a still picture apparatus with another apparatus, e.g. for storage, processing or transmission of still picture signals or of information associated with a still picture
- H04N1/00249—Connection or combination of a still picture apparatus with another apparatus, e.g. for storage, processing or transmission of still picture signals or of information associated with a still picture with a photographic apparatus, e.g. a photographic printer or a projector
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/04—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa
- H04N1/10—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa using flat picture-bearing surfaces
- H04N1/1061—Details relating to flat picture-bearing surfaces, e.g. transparent platen
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimile Scanning Arrangements (AREA)
Abstract
The large format scanner control system based on line array CCD that the present invention relates to a kind of, articles holding table controls motor and drives articles holding table mobile, LED lamp tube controls motor and double LED light sources of horizontalization platform space upper end is driven to adjust light source position, lens focusing controls the focusing movement of motor driven optical lens, and MCU output control signal controls various motor work；Tri- colo(u)r streak array CCD image sensor of RGB acquires image data under the Timing driver of CPLD control chip in data collection and transfering system, image data send CPLD to control chip after carrying out analog-to-digital conversion by AD conversion module, the digital signal being converted to is cached in SRAM by CPLD control chip, and CPLD controls chip and digital signal is transmitted to host computer by USB interface.In conjunction with machine control techniques, optical texture technology, digitized image acquisition technique, it is a kind of non-contact scanning instrument control system that ancient book, which is drawn the digitlization of historical relic legacy convenient for saving,.
Description
Technical field
The present invention relates to a kind of scanning technique, in particular to a kind of large format scanner control system based on line array CCD.
Background technique
In recent years, countries in the world matter input artificially or by the event that natural force destroys is emerged one after another, numerous
Historical and cultural heritage dies away among the long river of history.Therefore, the cultural relics protection unit of various countries is all positive by existing
The digital protection that generationization equipment and science and technology carry out 2D or 3D to historical relic works.The scanner technology of Current Domestic is horizontal
Also in the primary stage of research and development, scanner used in the country scans breadth and all exists substantially mostly from external import
A3 breadth or so, scanner image transducer sensitivity is low, and scanning resolution is single, scanning speed is limited, scanning color deviates
Realistic colour, quality are general.
Summary of the invention
The present invention be directed to the problems that large format scanning technique at this stage is limited, and propose a kind of based on the big of line array CCD
Breadth scanner control system draws ancient book in conjunction with machine control techniques, optical texture technology, digitized image acquisition technique
The digitlization of historical relic legacy is a kind of non-contact scanning instrument control system convenient for saving.
The technical solution of the present invention is as follows: a kind of large format scanner control system based on line array CCD, including Mechanical course
System and data collection and transfering system, Machinery Control System include MCU, articles holding table control motor, camera lens height control motor, mirror
Head focusing control motor and LED lamp tube control motor, and it includes lateral high-precision motor and longitudinal high-precision that articles holding table, which controls motor,
Motor, drives articles holding table mobile and adjustment optical lens height, and LED lamp tube controls motor and drives the double of horizontalization platform space upper end
LED light source adjusts light source position, and lens focusing controls the mobile focusing of motor driven optical lens, MCU output control signal control
Various motor work；Tri- colo(u)r streak array CCD image sensor of RGB drives in the timing of CPLD control chip in data collection and transfering system
Dynamic lower acquisition image data, image data send CPLD to control chip, CPLD control after carrying out analog-to-digital conversion by AD conversion module
The digital signal being converted to is cached in SRAM by chip, and digital signal is transmitted to by CPLD control chip by USB interface
Host computer.
The CPLD control chip gives ccd image sensor, AD conversion module and USB to provide driving signal respectively, gives
SRAM provides control signal, data and data corresponding address.
The tri- colo(u)r streak array CCD image sensor of RGB selects line array CCD-KLI-14403, defeated in each CCD analog signal
A voltage follower is devised on access out and improves load capacity, CPLD output timing signal passes through two CCD simulation displacements
Register is to CCD.
The output signal of any one of CCD pixel includes reset signal, reference signal and vision signal, AD conversion mould
There are two clock, a clock acquisition reference signal, another clock acquisition vision signal, AD conversion modules to export two for block tool
The difference of signal level is acquired, this difference is exactly the useful signal of image data.
The beneficial effects of the present invention are: the present invention is based on the large format scanner control systems of line array CCD, export image
Precision is high, color gradient variation is obvious, stereovision is prominent, and it is fast, easy to operate etc. to be provided simultaneously with strong antijamming capability, scanning speed
Feature.The scanning work of historical relic is drawn suitable for large format ancient book.By the painting and calligraphy historical relic legacy of artists' preciousness with digitized
Form remains, and not only contributes to the preservation of painting and calligraphy heritage information, provides weight for reparation, the reproduction work of later period historical relic legacy
The power-assisted effect wanted, moreover it is possible to by the fast propagation of digital information, allow general masses sieve that can experience the magnificent of historical relic legacy.
Detailed description of the invention
Fig. 1 is that the present invention is based on the large format scanner Control system architecture block diagrams of line array CCD；
Fig. 2 is that the present invention is based on Mechanical course structural schematic diagrams in the large format scanner control system of line array CCD；
Fig. 3 is Linear Array CCD Image Sensor circuit diagram of the present invention；
Fig. 4 is that the present invention improves signal driving capability circuit diagram；
Fig. 5 is the circuit diagram of AD modulus conversion chip of the present invention；
Fig. 6 is CPLD chip controls connection figure of the present invention；
Fig. 7 is that the control instruction of host computer of the present invention is sent to CPLD signal transmission figure by USB；
Fig. 8 is transmitted to host computer signal transmission figure through USB for image data of the present invention.
Specific embodiment
The large format scanner Control system architecture block diagram based on line array CCD, system include Mechanical course system as shown in Figure 1
System and data collection and transfering system, Machinery Control System include MCU (micro-control unit), articles holding table control motor, camera lens height
It controls motor, lens focusing control motor and LED lamp tube and controls motor, Machinery Control System is responsible for adjusting the mobile speed of object disposing platform
Degree, camera lens scanning resolution and scanning light source.Data collection and transfering system successively include ccd image sensor, AD conversion module,
CPLD (Complex Programmable Logic Devices), SRAM (static random access memory), USB interface and host computer, data acquisition pass
Defeated system completes the acquisition, conversion, transmission operation of image data.
Host computer sets object disposing platform movement speed and distance, the camera lens scanning resolution and scanning of Machinery Control System
After the parameters such as light source, mobile by articles holding table carrying manuscript to be scanned, Linear Array CCD Image Sensor passes through high-precision optical camera lens pair
Data are filtered noise reduction and analog-to-digital conversion, connect finally by USB by contribution into scanning sample after obtaining raw image data
Mouth sends data to the end PC host computer, and host computer completes data processing, file storage and image display function.
1, Machinery Control System
Fig. 2 is Mechanical course structural schematic diagram, controls the electric machine operation state of different piece, by MCU to complete glove
Platform moves left and right, the adjusting of optical lens height and focal adjustment and double LED light source angles and spacing.Articles holding table control electricity
Machine includes lateral high-precision motor and longitudinal high-precision motor, drives articles holding table mobile and adjustment optical lens height, light source electricity
Machine (LED lamp tube in Fig. 1 controls motor) drives double LED light sources of horizontalization platform space upper end to adjust light source position, motor of focusing
The mobile focusing of (lens focusing in Fig. 1 controls motor) driving optical lens.Horizontalization platform working size is 1.20m*2.0m, is passed through
1.8 ° of full step motors drive the ball screw movement that length is 2.2m, precision is C3 grades.Under maximum functional size, image scanning
Maximum pixel is up to 3.4 hundred million.Optical lens selects technical grade APO Symmar optical lens, away from object disposing platform maximum vertical height
For 1.5m, it can be achieved that the optical resolution of 300-1200DPI is adjusted.The depth of parallelism of ccd image sensor and articles holding table is by built-in
Three-dimensional fine-tuning mechanism is adjusted, and focus process then passes through software Atomatic focusing method and carries out.Radiation source uses adjustable double LED light
Source matches the sweep object of unlike material by adjusting the distance between two LED light sources, incident angle and brightness.
2, data collection and transfering system
The data collection and transfering system of scanner is responsible for voltage needed for providing each functional module as power configuration circuit,
Tri- colo(u)r streak array CCD image sensor of RGB acquires image data under the Timing driver of CPLD.Arrow in Fig. 1 is image data
Flow direction, image data send CPLD, CPLD that will convert after carrying out analog-to-digital conversion by A/D chip with correlated-double-sampling function
Obtained digital signal is cached in SRAM, and digital signal is transmitted to host computer by USB interface by CPLD.
3, power configuration circuit
Power supply needed for each functional module of data collection and transfering system is not of uniform size, will input electricity using power supply voltage stabilizing chip
Pressure is matched to each functional module required voltage, and the operating voltage of Linear Array CCD Image Sensor is+15V, Timing driver voltage
For+6.8V；The analog voltage of AD conversion chip needs+5V；CPLD chip operating voltage is+3.3V；The power supply of SRAM and USB is all
It is+3.3V.The analog circuit and digital circuit of system are powered respectively, and+19V the voltage of input is carried out pressure stabilizing using power supply chip
It is transformed into+15V, then operating voltage required for modules is depressured to as+15V.Power supply chip uses LDO chip, can be effective
Reduction hardware design part noise jamming, peripheral components are few, can be substantially reduced circuit design volume, improve integrated level.
4, Linear Array CCD Image Sensor
Fig. 3 is Linear Array CCD Image Sensor circuit diagram, and line array CCD-KLI-14403 is selected to belong to low consumption electronic device,
Have the characteristics that high-resolution, high sensitivity and low-dark current, but its load capacity is weaker, output signal cannot drive next stage
Signal processing circuit.Making to be independent of each other between front stage circuit in transmission process to reduce signal, it is negative to improve its band
The ability of load, therefore a voltage follower is devised on each CCD analog signal output access.
What system was selected is CPLD as driver' s timing controller, i.e., provides driver' s timing signal by CPLD for CCD.CCD
Drive level be 6.8V, and the output signal level of CPLD only has 3.3V, and driving capability is limited, thus need CPLD with
Increase the circuit for improving signal driving capability between CCD, as shown in Figure 4.In the CCD analogue shift register of the type, two
A shift register is to receive signal charge from continuous pixel in an alternating fashion.This mode is conducive to pixel density
Increase, can also reduce half transfer number, improve transfer efficiency, charge energy in transfer process can also be reduced at the same time
The loss of amount.After the driving of correct time sequential pulse, the analog signal output VIDn of CCD will be respectively fed to junior's electricity
Road, i.e. AD analog to digital conversion circuit are handled.
5, AD conversion module
The output signal period of any one of CCD pixel is all made of three parts: reset signal, reference signal and video
Signal, wherein video level indicates the photosensitive intensity of current corresponding pixel, contains true image information.Corresponding pixel
Illumination is stronger, and video level will be lower, and the voltage difference with reference signal level will be bigger.Include inside signal
The noise that charge generates in channel transfer process and CCD reseting procedure, including photon shot noise, transfer noise, output make an uproar
Sound, these interference signals largely affect picture quality.For CCD output analog signal processing, mainly include
Signal condition and A/D convert two parts, and the processing of each part plays acquisition high quality graphic signal irreplaceable
Effect.The former is dry in order to eliminate as much as various external disturbances and outside during Image Acquisition, transmission and processing
Disturb the complicated and diversified noise of bring and interference, it is ensured that exporting analog signal in CCD normal range of operation can be according to historical relic figure
Image brightness changes linearly.The latter is then the digitlization completed to ccd output signal, and further software is facilitated to handle.
Fig. 5 is the circuit diagram of AD modulus conversion chip, and as seen from the figure, A/D chip has VINR, VING, VINB tri-
A analog signal input port, in the chip portion to analog signal complete correlated-double-sampling (CDS) processing after, be then biased and
Gain adjustment exports digital signal from the port DD0-DD7 finally by multiple selector.It should be noted that chip only has 8
The digital output end of position, data port need to be multiplexed the data for reaching 16 precision twice.Sampling clock be CDSCLK1 and
CDSCLK2, CDSCLK1 acquire the reference level (reference level is collected in VIDn) of signal VIDn in failing edge,
CDSCLK2 acquires signal level (acquisition signal level is also collected in VIDn) in failing edge, by CDS amplifier
The difference (CDS amplifier is inside A/D chip) of two signal levels is exported afterwards, this difference is exactly effective letter of image data
Number.Because the time is very short in a pixel period, the difference of two signals can filter out reset noise, obtain effectively
Picture signal.
6, CPLD controls chip
Estimating required resource size according to scheme to determine control chip model, the CPLD model of selection is
EPM1270T144C5, the chip have 1270 logic units, 144 external pins, wherein can be used as input/output port
Pin number is 116, and encapsulation is TQFP144.Other embedded mmdb processors can also be used, such as FPGA, MCU, ARM and DSP
Deng.Control circuit includes control chip, system clock circuit, reset circuit, configuration circuit etc..FPGA is mainly responsible for the control of module
System, CPLD as shown in Figure 6 control chip controls connection figure, and CPLD control chip gives ccd image sensor, AD conversion module respectively
Driving signal is provided with USB, provides control signal, data and data corresponding address to SRAM.
6, SRAM data is read and write
Since CPLD not can be carried out the storage inside of data, so sram chip is needed to realize access function in a manner of static storage
Can, small power consumption, access speed is fast, using bistable volt circuit as storage unit, does not need constantly to refresh preservation data as DRAM, only
It needs that the write-in and reading of data can be carried out in corresponding address by correct addressing of address.
7, USB data transmission
The CY7C68013-56PVC chip that this system is selected is Cypress company EZ-USB-FX2 series with MCU
USB2.0 interface chip, it is also possible to which the USB3.0 interface chip of EZ-USB-FX3 series replaces, and can reach 320Mbit/s data biography
Defeated speed.The main function of USB data transmission module includes: that the control instruction of host computer is sent to CPLD by USB, as shown in Figure 7；
Image data is transmitted to host computer through USB, as shown in Figure 8.Chip be arranged 16 data port be used for Designing of High Speed FIFO, 1
A I2C compatible bus interface is used to download the firmware program of CPU, and firmware program is stored in external storage eeprom chip
24LC64.CY7C68013 chip mainly has two kinds of Slave FIFO and GPIF (General ProgrammableInterface)
Mode realizes data acquisition and bulk transfer.In view of system uses CPLD as master controller, therefore select the side of being connected thereto USB
Formula is Slave fifo mode.According to chip concept and structure it is found that USB interface and peripheral circuit can be stored using FIFO
Device, enhanced 8051 can be not involved in USB carries out data transmission with external circuit, but can be accessed by FIFO or RAM
These data.The problem of this design method very good solution bandwidth exists in high speed mode is suitble to transmitted data amount big
Project project exploitation.In Slave fifo mode, external logic or MCU can be connect with the FIFO endpoint of FX2, directly
Logic control is carried out to FIFO, so GPIF mode will not work at this time.The control of FIFO can be analogous to conventional
The data buffer zone of the reading data and write-in of FIFO, four endpoints such as EP2, EP4, EP6, EP8 in subordinate FIFO carries out phase
The read-write operation answered.Under this mode, CPLD is master controller, and EZ-USB is transmitted as just data between USB and CPLD
Channel.Basic fifo signal includes that empty full bit flag signal, selection signal, gating signal etc. are not all drawn from chip interior
Out.Peripheral control unit can work under synchronization or asynchronous system, and can be provided to FX2 interface oneself it is independent when
Clock.Only need CPLD that can provide correct clock signal, CPLD can realize the data communication between computer.
Claims (4)
1. a kind of large format scanner control system based on line array CCD, which is characterized in that including Machinery Control System and data
Acquiring and transmission system, Machinery Control System include MCU, articles holding table control motor, camera lens height control motor, lens focusing control
Motor and LED lamp tube control motor, and it includes lateral high-precision motor and longitudinal high-precision motor that articles holding table, which controls motor, and drive is set
Object platform is mobile and adjustment optical lens height, LED lamp tube control motor and double LED light sources of horizontalization platform space upper end driven to adjust light
Source position, lens focusing control the mobile focusing of motor driven optical lens, and MCU output control signal controls various motor work；
Tri- colo(u)r streak array CCD image sensor of RGB acquires image under the Timing driver of CPLD control chip in data collection and transfering system
Data, image data send CPLD to control chip after carrying out analog-to-digital conversion by AD conversion module, and CPLD control chip will be converted
To digital signal be cached in SRAM, CPLD controls chip and by USB interface digital signal is transmitted to host computer.
2. the large format scanner control system based on line array CCD according to claim 1, which is characterized in that the CPLD
Control chip gives ccd image sensor, AD conversion module and USB to provide driving signal respectively, provides control signal, number to SRAM
Accordingly and data corresponding address.
3. the large format scanner control system based on line array CCD according to claim 1, which is characterized in that the RGB tri-
Colo(u)r streak array CCD image sensor selects line array CCD-KLI-14403, devises one on each CCD analog signal output access
A voltage follower improves load capacity, and CPLD output timing signal passes through two CCD analogue shift registers to CCD.
4. the large format scanner control system based on line array CCD according to claim 1, which is characterized in that the CCD appoints
The output signal of what pixel includes reset signal, reference signal and vision signal, and AD conversion module tool is there are two clock, and one
A clock acquisition reference signal, another clock acquisition vision signal, AD conversion module export the difference of two acquisition signal levels
Value, this difference is exactly the useful signal of image data.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112637451A (en) * | 2020-12-09 | 2021-04-09 | 武汉茂格科技有限公司 | Based on AI image recognition sensor probe mends limit control system |
| CN114466110A (en) * | 2022-01-14 | 2022-05-10 | 东莞中科蓝海智能视觉科技有限公司 | Precision flat-field camera |
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