CN104104825B - Bearing calibration based on the Double face scanner acquisition system of FPGA - Google Patents
Bearing calibration based on the Double face scanner acquisition system of FPGA Download PDFInfo
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Abstract
The invention discloses the Double face scanner acquisition system and its scanning and bearing calibration based on FPGA, including scan data processing system, PC main frames, a CIS sensors and the 2nd CIS sensors, and while the CIS transmission modules being connected with a CIS sensors and the 2nd CIS sensors；Scan data processing system includes FPGA main control chips, while the first data conversion module being connected with FPGA main control chips, the second data conversion module, first memory, communication interface, correction module and USB module, and board mounted power module；First CIS sensors are connected with the first data conversion module, and the 2nd CIS sensors are connected with the second data conversion module, and CIS transmission modules are connected with communication interface, and PC main frames are connected with USB module.The present invention is reasonable in design, easy to use, disposably can show two sides image while fast scan imaging, therefore, which is suitable to popularization and application.
Description
Technical field
The present invention relates to a kind of scanner acquisition system, and in particular to be that a kind of Double face scanner based on FPGA is gathered
The bearing calibration of system.
Background technology
The conventional scanner in existing market, mostly using single-chip microcomputers such as ARM as main control chip.Although occupying on cost
Advantage, but due to the restriction of of ARM chips itself, design unreasonable as well as scanner its own system, cause scanning speed
Degree is slower, it is difficult to meet the live and work rhythm that people increasingly accelerate.And existing scanner is generally single-sweep mould
Formula, for the sweep object of double-side pattern, needs artificial operation twice, does not meet intelligent demand.
The content of the invention
It is an object of the invention to provide a kind of bearing calibration of the Double face scanner acquisition system based on FPGA, main to solve
Certainly existing scanning speed of scanner is slow, and the problem that disposably can not be scanned pattern two sides.
To achieve these goals, the technical solution used in the present invention is as follows：
Based on the bearing calibration of the Double face scanner acquisition system of FPGA, comprise the following steps：
(1), after system electrification, PC main frames send correction instruction to FPGA main control chips by USB module；
(2) FPGA main control chips produce the clock and control signal needed for each module after receiving instruction, by two light sources
Controller controls two CIS sensors respectively while lighting, and passes to CIS transmission modules by communication interface, makes machinery dynamic
Make equipment a CIS sensors and the 2nd CIS sensors are controlled respectively to correcting paper according to the scan pattern of PC main frame requirements
Two sides carries out image acquisition；In the step, it is bright in the front field time point of scanogram that light source controller only controls CIS sensors,
Then close CIS sensors afterwards during field and close light source；
After (3) two CIS sensor scan images, two analog-digital converters, two analog-digital converters are sent data to
Under the change over clock signal that FPGA main control chips are provided, by the analogue signal of two CIS sensors output and it is converted into respectively
Digital signal, stores in being then communicated to memorizer；
(4) FPGA main control chips read memorizer in view data and processed, then by USB module transmit to
PC main frames, and after the data that PC main frames have received two sides image, rearrange according to each pixel RGB order, corrected
Image is simultaneously shown；PC main frames calculate correction parameter according to the image for showing simultaneously, and transmit into FPGA main control chips；
In the step, the process of PC Framework computing correction parameters is as follows：
A () PC main frames obtain view data after, before extracting in half frame images the 500th row of first pixel to the 999th
Row amounts to the data of tri- passages of R, G, B of 500 rows, and the RGB in obtaining pixel the 500th row to the 999th row per a line
Pixel value；
B the rgb pixel value of the pixel in the 500th row to the 999th row every a line is done mean operation by () PC main frames, obtain
R1 is equal、G1 is equal、B1 is equal, that is, obtain the correction parameter of tri- kinds of color modes of R, G, B of first pixel in first half two field picture；
C () circulation step (a), (b) successively, until PC main frames have extracted the remaining pixel of front half frame images, and obtains
The correction parameter of tri- kinds of color modes of R, G, B of remaining each pixel in front half frame images；
Pixel d the 500th row to the 999th row of first pixel is per a line in half frame images after the extraction of () PC main frames in
Value；
E the pixel value of the pixel in the 500th row to the 999th row every a line is done mean operation by () PC main frames, obtain
black, that is, obtain the black correction parameters of first pixel in later half two field picture；
(f) circulation step (d), (e) successively, until PC main frames take the remaining pixel of rear half frame images, and after obtaining
The black correction parameters of remaining each pixel in half frame images；
G the black correction parameters of R, G, B of front half frame images and rear half frame images are transferred to FPGA master controls by () PC main frames
Chip, calculates for correcting；
(5) FPGA main control chips receive parameter, and store to not losing in the correction module of function with power failure data, with
Afterwards during each scanogram, after FPGA main control chips read view data from memorizer, then the school in correction module is read
Positive parameter, and correction parameter is calculated with view data, the view data after being corrected, finally pass through USB module again
It is transferred to PC main frames.
Compared with prior art, the invention has the advantages that：
(1) present invention is reasonable in design, with low cost, and scanning speed is fast, efficiency high.
(2) two sides of the present invention using CIS sensor acquisition images, its have small volume, it is easy for installation, without the need for external light
Source, the advantage of low in energy consumption and zero distortion of imaging, compared to CCD and CMOS, cost is also cheap a lot, then using FPGA as master
Control chip, is responsible for the transmission and process of image, and as FPGA has, internal resource is abundant, I/O quantity is more and can customize function
The features such as, mass data can be processed with very high clock frequency, thus can be laid the foundation quickly to scan figure.This
In bright, FPGA main control chips after with reference to data conversion module and communication interface, the figure line by line that CIS sensor acquisition can be arrived
As being combined arrangement, then complete view data is exported to PC main frames, which is realized well by the combination of software and hardware
The function of quick scanogram and disposable duplex scanning, has been greatly optimized the performance of scanning, therefore, of the invention and prior art
Compare, with prominent substantive distinguishing features and significant progress.
(3) present invention have also been devised the scheme of correct scan, and the combination by software and hardware, be obtained by scanning correction paper
The correction parameter used each is needed under color mode and black and white scan pattern, and applies it to real image scanning
In, the view data to gathering is corrected, it is ensured that the precision of its image scan data so that the image for finally scanning out was both
It is consistent with actual scanning object, and with enough definitions.
(4) present invention is also provided with on-line debugging interface, can be connected with its exterior commissioning device so that FPGA master controls
Chip be provided with can on-line debugging characteristic, user can be programmed to FPGA according to actual needs again, and its function is added and repaiied
Change and facilitate very much, by cleverly hardware designs of the invention, so as to also do subsequently to strengthen and improving present system function
Good place mat.
(5) cost performance of the present invention is high, workable, and which is with a wide range of applications, and is suitable to popularization and application.
Description of the drawings
Fig. 1 is the system structure diagram of the present invention.
Specific embodiment
The invention will be further described with reference to the accompanying drawings and examples, and embodiments of the present invention are included but is not limited to
The following example.
Embodiment
As shown in figure 1, the present invention include a CIS sensors, the 2nd CIS sensors, scan data processing system and
PC main frames.The first CIS sensors and the 2nd CIS sensors are used to gather image, wherein a CIS sensor is used to gather
The direct picture of sweep object, another CIS sensor are used for the verso images of acquisition scans object, and two CIS sensors are same
When be connected with scan data processing system.The scan data processing system is connected with PC main frames, and which is issued according to PC main frames
Instruction is processed to image and is transmitted.Specifically, the scan data processing system includes FPGA main control chips, while with
First data conversion module of the FPGA main control chips connection, the second data conversion module, first memory, communication interface, school
Positive module, USB module and on-line debugging interface, and the board mounted power mould for powering to whole scan data processing system
Block；Wherein, first data conversion module is made up of the first analog-digital converter and the first light source controller, the two simultaneously with
First CIS sensors and the connection of FPGA main control chips, and the second data conversion module is then by the second analog-digital converter and the second light
Source controller composition, the two is then connected with the 2nd CIS sensors and FPGA main control chips simultaneously, the PC main frames then with USB
Module connects, and in the present embodiment, scan data processing system is connected with PC main frames by USB2.0 interfaces.
First memory in scan data processing system is used for interim storage data, so that FPGA main control chips are being carried out
Called data during the process and transmission of image, and in order to further expand the capacity of storage, the present embodiment is also provided with
Second memory.And further, first memory is secondary DDR (DRR II) with the type of second memory.
Communication interface in scan data processing system is used for the mechanical action equipment for making FPGA main control chips and scanner
Connection, will pass through the instruction control machinery action equipment control CIS sensor scan images that FPGA main control chips are issued.
Correction module in scan data processing system, should for after system compensation, storing the correction parameter of its generation
Correction module has the characteristic that power failure data is not lost, it can be ensured that correction parameter is not lost, and the moment facilitates system in scanning figure
As when be corrected.
And the on-line debugging interface in scan data processing system is then used for system and connects external debugging device, so as to basis
Being actually needed carries out reprogramming to FPGA main control chips, and its function is added and is changed.
Based on above-mentioned hardware foundation, process is introduced to be realized to of the invention below.The present invention have normal scan and
Correct scan both of which, the two flow process difference are as follows：
Normal scan mode
(1), after system electrification, PC main frames send scan instruction to FPGA main control chips by USB module；
(2) FPGA main control chips produce the clock and control signal needed for each module after receiving instruction, by two light sources
Controller controls two CIS sensors respectively while lighting, and passes to CIS transmission modules by communication interface, is driven CIS
Module controls a CIS sensors and the 2nd CIS sensors to sweep object respectively according to the scan pattern that PC main frames are required
Two sides carries out image acquisition；
After (3) two CIS sensor scan images, two analog-digital converters, two analog-digital converters are sent data to
Under the change over clock signal that FPGA main control chips are provided, the analogue signal of two CIS sensors outputs is converted into into number respectively
Word signal, then simultaneous transmission processed in FPGA main control chips；
(4) after FPGA main control chips processing data, transmitted to PC main frames by USB module, and two have been received in PC main frames
After the data of face image, image is shown.
Correction mode
(1), after system electrification, PC main frames send correction instruction to FPGA main control chips by USB module；
(2) FPGA main control chips produce the clock and control signal needed for each module after receiving instruction, by two light sources
Controller controls two CIS sensors respectively while lighting, and passes to CIS transmission modules by communication interface, is driven CIS
Module controls a CIS sensors and the 2nd CIS sensors to correcting the two of paper respectively according to the scan pattern that PC main frames are required
Face carries out image acquisition；In the step, it is bright in the front field time point of scanogram that light source controller only controls CIS sensors, after
CIS sensors are then closed during field and closes light source；
After (3) two CIS sensor scan images, two analog-digital converters, two analog-digital converters are sent data to
Under the change over clock signal that FPGA main control chips are provided, by the analogue signal of two CIS sensors output and it is converted into respectively
Digital signal, stores in being then communicated to memorizer；
(4) FPGA main control chips read memorizer in view data and processed, then by USB module transmit to
PC main frames, and after the data that PC main frames have received two sides image, rearrange according to each pixel RGB order, corrected
Image is simultaneously shown；PC main frames calculate correction parameter according to the image for showing simultaneously, and transmit into FPGA main control chips；
In the step, the process of PC Framework computing correction parameters is as follows：
A () PC main frames obtain view data after, before extracting in half frame images the 500th row of first pixel to the 999th
Row amounts to the data of tri- passages of R, G, B of 500 rows, and the RGB in obtaining pixel the 500th row to the 999th row per a line
Pixel value；
B the rgb pixel value of the pixel in the 500th row to the 999th row every a line is done mean operation by () PC main frames, obtain
R1 is equal、G1 is equal、B1 is equal, that is, obtain the correction parameter of tri- kinds of color modes of R, G, B of first pixel in first half two field picture；
C () circulation step (a), (b) successively, until PC main frames have extracted the remaining pixel of front half frame images, and obtains
The correction parameter of tri- kinds of color modes of R, G, B of remaining each pixel in front half frame images；
Pixel d the 500th row to the 999th row of first pixel is per a line in half frame images after the extraction of () PC main frames in
Value；
E the pixel value of the pixel in the 500th row to the 999th row every a line is done mean operation by () PC main frames, obtain
black, that is, obtain the black correction parameters of first pixel in later half two field picture；
(f) circulation step (d), (e) successively, until PC main frames take the remaining pixel of rear half frame images, and after obtaining
The black correction parameters of remaining each pixel in half frame images；
G the black correction parameters of R, G, B of front half frame images and rear half frame images are transferred to FPGA master controls by () PC main frames
Chip, calculates for correcting, its correction that can be used under color mode, it is also possible to for the school under black and white scan pattern
Just；
(5) FPGA main control chips receive parameter, and store to not losing in the correction module of function with power failure data, with
Afterwards during each scanogram, after FPGA main control chips read view data from memorizer, then the school in correction module is read
Positive parameter, and correction parameter is calculated with view data, the view data after being corrected, finally pass through USB module again
It is transferred to PC main frames.
For convenience of the calculating understood in the present invention with regard to correction parameter, the present embodiment is explained with a calculated examples
Explanation.
Prepare a pure white correction paper, which is scanned, as before scanning, during half frame images, CIS sensors are lit,
And after scanning during half frame images, CIS sensor light sources are closed, therefore, the plain white image of display is also first half two field picture.
And the resolution of the image of the display is 300DPI, and pixel is 2544 pixels for the width of 2544x 3504, i.e. image,
Namely a line view data number is 2544.
By taking first pixel as an example：
500th row image is divided into into three color channels, can be designated as respectively：
R passages：R1_ 500, R2_ 500, R3_500……R2544_500；
G passages：G1_ 500, G2_ 500, G3_500……G2544_500；
Channel B：B1_ 500, B2_ 500, B3_500……B2544_500；
500th row first row pixel value is then (R1_ 500, G1_ 500, B1_500)。
It is then (R that the 501st row first row pixel value is obtained in the same manner1_ 501, G1_ 501, B1_501)；
502nd row first row pixel value is then (R1_ 502, G1_ 502, B1_502)；
……
999th row first row pixel value is then (R1_ 999, G1_ 999, B1_999)。
Mean operation is made respectively to tri- passages of RGB, by taking R passages as an example, formula is as follows：
R1 is equal=(R1_500+R1_501+R1_502+……+R1_999)/500
G1 is equalAnd B1 is equalComputing formula and R1 is equalIt is identical.
Finally, the R for obtaining1 is equal、G1 is equalAnd B1 is equalAs RGB correction parameters of first pixel of image.Same calculating side
Method can obtain the RGB correction parameters of remaining 2543 pixel.
Half frame images, due to light source closing, are black images because obtained from afterwards, the image any point that its scanning is obtained
Tri- passage gray values of RGB it is equal, it is then same that rear each pixel of half frame images is obtained using similar aforesaid way
Correction parameter, here, we term it black correction parameters.
Consequently, it is possible to resulting R, G, B, black this several correction parameter all can be calculated, and in chromoscan mould
It is used as the correction of view data in formula.
And above-mentioned G, black correction parameter for calculating then is used as the correction of view data in black and white scan pattern,
In black and white scan pattern, G correction parameters here are we term it the white WhiteG parameters of gray scale.
Why above-mentioned correction parameter calculating adopts the 500th row of each pixel to the 999th row image, is to combine
The scanning accuracy of existing scanner, in general, correction paper is fixed as A4 breadth due to correcting paper in scanning, therefore, greatly
About from the 20th row, the rgb pixel value which scans out is relatively stable, of the invention then take its pixel value from the 500th row, is used in combination
In correction parameter is calculated, so calculating greatly improves can the accuracy rate of correction, and for correcting the image of subsequent acquisition
The reliability of data is also very high.If using the 1st row to the 500th row image, because the reason for scanning accuracy, may result in
The image of the 1st row is not the correct correction paper image for scanning, consequently, it is possible to may result in correction parameter mistake in computation.Cause
This, the present invention selects start recording R, G, the data of tri- passages of B from the 500th row image, and for calculating correction parameter.Such as
The reason for this both take into account existing scanner scanning precision, has also been properly arrived at utilization correction parameter of the present invention to collection
The purpose that view data is corrected.
The present invention adopts FPGA as main control chip, and devises again the structure of system so which is provided with scanning speed
Degree is fast, disposably by the function of two Surface scan of image, and can be also equipped with the work(being corrected to the view data for gathering
Can, it is ensured that image accurately shows, improve the precision that image shows.The present invention is all linked with one another in design details, is fitted close, and leads to
Software and hardware combining is crossed, a complete function system is defined well, therefore, the present invention compared with prior art, enter by technology
Step is fairly obvious.
Above-described embodiment is only the present invention preferably one of implementation, should not be used to limit the protection model of the present invention
Enclose, the technology of all done any changes or polishing for having no essential meaning under the body design thought and spirit of the present invention
Scheme, should be within the scope of the present invention.
Claims (1)
1. based on FPGA Double face scanner acquisition system bearing calibration, it is characterised in that comprise the following steps：
(1), after system electrification, PC main frames send correction instruction to FPGA main control chips by USB module；
(2) FPGA main control chips produce the clock and control signal needed for each module after receiving instruction, by two light source controls
Device controls two CIS sensors respectively while lighting, and passes to CIS transmission modules by communication interface, sets mechanical action
The standby scan pattern required according to PC main frames controls a CIS sensors and the 2nd CIS sensors respectively to correcting the two sides of paper
Carry out image acquisition；In the step, it is bright in the front field time point of scanogram that light source controller only controls CIS sensors, later half
CIS sensors are then closed during frame and closes light source；
After (3) two CIS sensor scan images, two analog-digital converters are sent data to, two analog-digital converters exist
Under the change over clock signal that FPGA main control chips are provided, by the analogue signal of two CIS sensors output and number is converted into respectively
Word signal, stores in being then communicated to memorizer；
(4) FPGA main control chips read the view data in memorizer and are processed, and are then transmitted to PC master by USB module
Machine, and after the data that PC main frames have received two sides image, rearrange according to each pixel RGB order, obtain correction chart picture
And shown；PC main frames calculate correction parameter according to the image for showing simultaneously, and transmit into FPGA main control chips；The step
In rapid, the process of PC Framework computing correction parameters is as follows：
A () PC main frames obtain view data after, before extracting, in half frame images, the 500th row of first pixel is total to the 999th row
Count the data of tri- passages of R, G, B of 500 rows, and the rgb pixel in pixel the 500th row to the 999th row being obtained per a line
Value；
B the rgb pixel value of the pixel in the 500th row to the 999th row every a line is done mean operation by () PC main frames, obtain R1 is equal、
G1 is equal、B1 is equal, that is, obtain the correction parameter of tri- kinds of color modes of R, G, B of first pixel in first half two field picture；
C () circulation step (a), (b) successively, until PC main frames have extracted the remaining pixel of front half frame images, and obtains first half
The correction parameter of tri- kinds of color modes of R, G, B of remaining each pixel in two field picture；
Pixel value d the 500th row to the 999th row of first pixel is per a line in half frame images after the extraction of () PC main frames in；
E the pixel value of the pixel in the 500th row to the 999th row every a line is done mean operation by () PC main frames, obtain black ,
The black correction parameters of first pixel in later half two field picture are obtained；
F () circulation step (d), (e) successively, until PC main frames take the remaining pixel of rear half frame images, and obtains rear field
The black correction parameters of remaining each pixel in image；
G the black correction parameters of R, G, B of front half frame images and rear half frame images are transferred to FPGA master control cores by () PC main frames
Piece, calculates for correcting；
(5) FPGA main control chips receive parameter, and store to not losing in the correction module of function with power failure data, often later
During secondary scanogram, after FPGA main control chips read view data from memorizer, then read the correction ginseng in correction module
Number, and correction parameter is calculated with view data, the view data after being corrected, finally transmitted by USB module again
To PC main frames.
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| CN106357949B (en) * | 2016-08-26 | 2019-08-06 | 珠海赛纳打印科技股份有限公司 | A kind of scanning means, image forming apparatus and scan method |
| CN106998408A (en) * | 2017-02-21 | 2017-08-01 | 昆明奥多智能科技有限公司 | It is a kind of closely or contact high-speed image acquisition system |
| CN108933879B (en) * | 2017-05-22 | 2020-02-11 | 深圳市安普盛科技有限公司 | CIS scanning device, system and scanning method |
| CN108259698B (en) * | 2018-03-22 | 2020-05-15 | 深圳怡化电脑股份有限公司 | Image scanning method, system, device and computer readable storage medium |
| CN110022420B (en) * | 2019-03-13 | 2020-09-08 | 华中科技大学 | Image scanning system and method based on CIS and storage medium |
| CN110233948A (en) * | 2019-07-15 | 2019-09-13 | 珠海奔图电子有限公司 | Scanning device, image forming apparatus, scan method and storage medium |
| CN111031240B (en) * | 2019-12-06 | 2021-08-03 | 凌云光技术股份有限公司 | Multi-mode image processing method and device based on FPGA |
| JP2022065848A (en) * | 2020-10-16 | 2022-04-28 | セイコーエプソン株式会社 | Image reading device |
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