CN104113675A - Image real-time correction output method for broad-width scanner - Google Patents

Abstract

The invention discloses an image real-time correction output method for a broad-width scanner. The method includes the following steps: (1) a PC host sends a scanning instruction to an FPGA main control chip; (2) the FPGA main control chip controls N linear CCD image sensors to light on at the same time and controls a CCD transmission module to control the N linear CCD sensors to acquire images synchronously and at the same time, an algorithm module in the FPGA main control chip calculates two correction parameters Alpha and Beta respectively; (3) the linear CCD sensors acquire image data and transmit the image data to analog-to-digital converters and the analog-to-digital converters convert analog signals into digital signals and transmit the digital signals to the algorithm module in the FPGA main control chip to carry out processing; (4) the algorithm module calculates gray level values corrected by all photosensitive units; (5) the FPGA main control chip transmits the gray level values corrected by the photosensitive units to the PC host for processing so as to display images. The image real-time correction output method for the broad-width scanner is reasonable in design, high in processing speed and high in imaging precision.

Description

A kind of image real time correction output intent of broad width scanning instrument

Technical field

The present invention relates to a kind of image output method, what be specifically related to is a kind of image real time correction output intent of broad width scanning instrument.

Background technology

In recent years, due to the needs of high-resolution, super wide format Test Field, adopt the broad width scanning instrument of many CCD (Charge Coupled Device) imaging scheme to be widely used.How in ensureing large capacity image data fast transport, obtain high-quality scan image and be always one of topmost difficult point that broad width scanning instrument need to solve.The problem solving above need to be started with from following two aspects simultaneously: (1) shortens the gray correction time of scan image, because causing scan image gray value, the reasons such as the photosensitive cell response degree of imaging causing in uneven illumination and CCD pixel production technology is inconsistent produce non-uniform change, image information serious distortion, so be necessary the gray scale of scan image to proofread and correct very much.(2) when image rectification is consuming time while being no longer the bottleneck of whole system, just need to improve the speed of intermediate conveyor view data, because the time delay of system is to be determined by the delay time of slow module.

Although above-mentioned two aspects are keys that solution broad width scanning instrument obtains high-quality problem in large capacity image data fast transport, but, the method that can effectively simultaneously optimize this two aspect not yet had at present.

Summary of the invention

For above-mentioned technical deficiency, the invention provides a kind of image real time correction output intent of broad width scanning instrument, have advantages of that calibration accuracy, processing speed are fast, image display precision is high.

To achieve these goals, the technical solution used in the present invention is as follows:

An image real time correction output intent for broad width scanning instrument, is characterized in that, comprises the following steps:

(1), after system powers on, PC main frame sends scan instruction by USB module to FPGA main control chip;

(2) clocking and control signal after FPGA main control chip reception instruction, control N linear ccd image sensor lights simultaneously, and control CCD transmission module and sweep object is carried out to IMAQ according to N linear ccd image sensor of the scan pattern control of PC main frame requirement simultaneously, N is greater than 1 natural number; Meanwhile, the algoritic module in FPGA main control chip is using pure white and two kinds of colors of black as calibration point, and calculates respectively two correction parameter α and β according to following formula:

$\frac{255}{W-B}=1+m---\left(1\right)$

α+β＝m×256 (2)

Wherein, W represents to scan the gray value of pure white picture, and its value is the gray value that 220, B represents ater picture, and its value is that 15, m represents to retain the pure decimal of three after a decimal point; α is the integer part of the data obtained, the fractional part that B is the data obtained;

(3) view data of linear ccd image sensor acquisition scans object, and by this image data transmission to analog to digital converter, under the change over clock signal that analog to digital converter provides at FPGA main control chip, convert the analog signal of linear ccd image sensor output to digital signal, and the algoritic module being transferred in FPGA main control chip is processed;

(4) algoritic module adopts following formula to calculate the gray value A after its correction to first photosensitive unit ₁:

$A_1=x+\frac{(\mathrm{\α}+\mathrm{\β})\×x}{2^8}-(1+\frac{\mathrm{\α}+\mathrm{\β}}{256})\×B$

Wherein, X represents the gray value of first photosensitive unit of linear ccd image sensor actual acquisition;

(5) repeating step (4), until algoritic module all calculates the gray value A after remaining photosensitive unit correction; In repeating step (4) process, the view data that FPGA main control chip obtains correction is deposited in connected DDR memory temporarily;

(6) FPGA main control chip transfers to PC main frame by the gray value A after each each photosensitive unit self-correcting and processes, and PC main frame splices the view data of all linear ccd image sensor collections, obtains complete image, then image is shown.

As preferably, the model of described FPGA main control chip is Cyclone IV.

As preferably, described DDR memory is DDR II memory.

Further, in described step (2), described m represents to retain the pure decimal of four after a decimal point.

Again further, in described step (2), after two correction parameter α and β calculate, FPGA main control chip stores the two in connected flash memory into, afterwards when image correcting data, directly from this flash memory, two parameter alpha and β are read in the random access memory of FPGA main control chip inside, and in transmit image data, two correction parameter α and β are input in algoritic module.

Design principle of the present invention is, due to the gray-tone response difference of each pixel, so each light-sensitive element of CCD needs to carry out the correction of gray scale.First record correction parameter W and B by demarcation, and then use it for the correction that gathers image.The formula (1) being obtained by peg method need to complete to each pixel the floating-point operation of multiplication and division, along with imaging requirements is more and more higher, the pixel of CCD is more and more higher, so the size of picture is increasing, cause algorithm consuming time too much, will inevitably reduce the real-time performance of whole system, realize gray correction for addressing this problem herein with hardware, while is in conjunction with the characteristic of FPGA, gray correction algorithm is optimized to improvement, when having reduced algorithm to arithmetic operator Capability Requirement, also can ensure extraordinary calibration result.

The present invention uses pure white and two kinds of colors of black as calibration point, obtain linear correction equation (1), wherein W represents to scan the gray value of pure white picture, B represents the gray value of ater picture, the theoretical value of W and B is respectively 255 and 0, but it is 220 that W is averaged, it is 15 that B is averaged.Under both of these case, the output of CCD is all in the range of linearity of analog to digital converter, so need to proofread and correct transmitting image, x represents the gray value of the photosensitive unit of actual CCD actual acquisition, and A represents the gray scale after correction.Because the response characteristic of each photosensitive unit there are differences, so each photosensitive unit needs to proofread and correct, test and record correction ginseng coefficient W and the B of each photosensitive unit.

$A=\frac{x-B}{W-B}\×255=\frac{255}{W-B}\×x-\frac{255}{W-B}\×B---\left(1\right)$

For above-mentioned formula, the present invention, after the characteristic in conjunction with FPAG, can improve the real-time performance of system to a great extent, has also ensured extraordinary calibration result simultaneously.Normal CCD device can be guaranteed be the half that grey scale change scope exceedes the whole range of linearity of device, will be expressed as 1+m, m retains the pure decimal of three after a decimal point, and therefore, updating formula can be expressed as:

A＝(1+m)×x-(1+m)×B (2)

And owing to can not directly storing decimal in FPGA, so the correction coefficient calculating in formula (2) can not directly be used.Therefore, the present invention has done following conversion to formula (2), as shown in formula (3), first pure decimal part m is multiplied by 2 ⁸, this is to consider that processing mode the fastest in FPGA is displacement, therefore takes advantage of 2 ⁸be the equal of to move to left 8, fractional part is extracted and does follow-up computing, and retain (1+m) × x × 2 ⁸the integer part of result.

$A=\frac{(1+m)\×x\×2^8}{2^8}-(1+m)\×B---\left(3\right)$

Because m is pure decimal, so the result of m × 256 there will be fractional part, with alpha+beta=m × 256 expression, obtain the new expression formula (4) of A, wherein α represents the integer part of data, β represents the fractional part of data.

$A=x+\frac{(\mathrm{\α}+\mathrm{\β})\×x}{2^8}-(1+\frac{\mathrm{\α}+\mathrm{\β}}{256})\×B---\left(4\right)$

Thus, according to the gray value A after the correction calculating, may be used on carrying out in FPGA main control chip the correction processing of view data, coordinate DDR technology to make correction rate and image buffer storage performance reach coupling simultaneously, be finally transferred in PC main frame and carry out showing image after Image Mosaics.

Compared with prior art, the present invention has following beneficial effect:

(1) the present invention designs ingeniously, and principle is simple, and scanning imagery effect is good.

(2) the present invention is by the characteristic in conjunction with FPGA, design brand-new correcting scheme, reduce the dependence of the performance of algorithm to fpga chip, significantly improve traditional hardware corrected scheme, and apply it to ccd image output facet, the present invention completes multiple existing needs clock cycle the method improvement of correction for only needing 1 clock just can export data, and design by m value and choosing, reduce to a great extent correction error, its error is reduced in 0.5 DN (digital number), and the results showed, before after proofreading and correct, the light and shade contrast of image and picture detail are all obviously better than proofreading and correct.The present invention by effective combination of software and hardware, has solved the problem that prior art exists well, picture the restriction of prior art, and realized great innovation, therefore, the present invention compared with prior art, has outstanding substantive distinguishing features and significant progressive.

(3) the present invention adopts DDR memory as buffer memory, FPGA main control chip can be stored data in DDR memory in the process of image data processing temporarily, by the cooperation of FPGA main control chip and DDR memory, can make correction rate and the image buffer storage performance of system reach best matching degree, and then the overall performance of raising system, the processing speed of accelerating view data, real time correction speed of the present invention can reach Microsecond grade.

(4) real-time of the present invention is good, efficiency is high, reliability is strong, can meet well Practical Project demand, and therefore, it is with a wide range of applications, and is suitable for large-scale promotion application.

Brief description of the drawings

Fig. 1 realizes the hardware configuration schematic diagram of using required for the present invention.

Fig. 2 is schematic flow sheet of the present invention.

Fig. 3 is that the present invention-embodiment scans material object and the image schematic diagram of timing output not.

Fig. 4 is that the present invention-embodiment scans material object and proofreaies and correct the image schematic diagram of rear output.

Embodiment

Below in conjunction with drawings and Examples, the invention will be further described, and embodiments of the present invention include but not limited to the following example.

Embodiment

As shown in Figure 1, the present invention is mainly used in broad width scanning instrument aspect, its hardware aspect, mainly by the interior FPGA main control chip that is provided with algoritic module (being hardware multiplier) and random access memory (being RAM), multiple analog to digital converters that output is all connected with this FPGA main control chip input, the CCD transmission module being connected with this FPGA main control chip output, all with the two-way flash memory being connected of this FPGA main control chip, DDR memory and USB module, with the two-way PC main frame being connected of this USB module, and the linear ccd image sensor that output is connected with analog to digital converter input and is connected with CCD transmission module forms.

And based on above-mentioned hardware configuration, as shown in Figure 2, realization flow of the present invention is as follows:

(1), after system powers on, PC main frame sends scan instruction by USB module to FPGA main control chip;

(2) clocking and control signal after FPGA main control chip reception instruction, control N linear ccd image sensor lights simultaneously, and control CCD transmission module and sweep object is carried out to IMAQ according to N linear ccd image sensor of the scan pattern control of PC main frame requirement simultaneously, N is greater than 1 natural number; Meanwhile, the algoritic module in FPGA main control chip is using pure white and two kinds of colors of black as calibration point, and calculates respectively two correction parameter α and β according to following formula:

$\frac{255}{W-B}=1+m---\left(1\right)$

α+β＝m×256 (2)

Wherein, W represents to scan the gray value of pure white picture, and its value is the gray value that 220, B represents ater picture, and its value is that 15, m represents to retain the pure decimal of three after a decimal point; α is the integer part of the data obtained, the fractional part that B is the data obtained;

(3) view data of linear ccd image sensor acquisition scans object, and by this image data transmission to analog to digital converter, under the change over clock signal that analog to digital converter provides at FPGA main control chip, convert the analog signal of linear ccd image sensor output to digital signal, and the algoritic module being transferred in FPGA main control chip is processed;

(4) algoritic module adopts following formula to calculate the gray value A after its correction to first photosensitive unit ₁:

$A_1=x+\frac{(\mathrm{\α}+\mathrm{\β})\×x}{2^8}-(1+\frac{\mathrm{\α}+\mathrm{\β}}{256})\×B$

Wherein, X represents the gray value of first photosensitive unit of linear ccd image sensor actual acquisition;

(5) repeating step (4), until algoritic module is all calculated the gray value A after remaining photosensitive unit correction; In repeating step (4) process, the view data that FPGA main control chip obtains correction is deposited in connected DDR memory temporarily;

(6) FPGA main control chip transfers to PC main frame by the gray value A after each each photosensitive unit self-correcting and processes, and PC main frame splices the view data of all linear ccd image sensor collections, obtains complete image, then image is shown.

In the present invention, the model of FPGA main control chip is preferably Cyclone IV, the FPGA main control chip inside of this kind of model has the RAM of 3.9Mbit, enough realize the buffering of data, and 266 hardware multipliers also can meet the correcting algorithm of the present invention's design well, and it can just can complete correction by a clock.

The setting of described DDR memory is in order to coordinate FPGA main control chip, and the cooperation of the two can make the correction rate of system and image buffer storage performance reach coupling, thereby improves the overall performance of system.If use the image buffer storage scheme of traditional SDRAM can increase the time delay of image transmitting level, although algorithm correction module has reached very fast speed, it is best that but the performance of whole broad width scanning instrument does not reach, the longest module of time delay that is to say original system is appointed so and is not optimized, so the present invention adopts the buffer memory of DDR memory as transmitting stage, and as preferred, described DDR memory is selected two generation DDR memories (being DDR II), and the each clock of DDR2 can be with 4 times to the external bus speed read/write data of SDRAM.And why to improve the performance of memory device, because correcting algorithm just can complete correction through a clock cycle after optimizing, but the time delay of system is to be determined by the delay time of slow module, so the performance of whole system all will get a promotion after the buffer memory speed that improves image.

In addition,, in step (2), m represents to retain the pure decimal of three after a decimal point, it is quite little that it obtains gamma error DN (A represents with Δ), and in order further to reduce gamma error, as preferably, m represents to retain the pure decimal of four after a decimal point.So the reason of design is, after design, draws formula:

$\mathrm{\ΔA}=\frac{\mathrm{\β}\×x}{256}-\frac{\mathrm{\β}\×B}{2^8}=\frac{\mathrm{\β}\×(x-B)}{2^8}$

And from this formula, because x-B < 255, so again because β is decimal, so Δ A is less than 1, again because α calculates according to m, so decimal of many reservations can be reduced to error the half of error originally in the time calculating m, in the time of calculation correction coefficient, m can make the error of result of calculation in 0.5 DN after retaining four decimals.

In addition, after two correction parameter α and β calculate, FPGA main control chip stores the two in connected flash memory into, afterwards when image correcting data, directly from this flash memory, two parameter alpha and β are read in the random access memory of FPGA main control chip inside, and in transmit image data, two correction parameter α and β are input in algoritic module, then in whole trimming process, do not need to go again to read coefficient, then the view data obtaining in trimming process can be put into DDR2 memory cache, carry out owing to proofreading and correct in whole process and transmitting simultaneously, so speed is very fast, reach the requirement of real-time.In order to allow data can reach complete streamline output, namely will guarantee that algorithm execution time is less than the transmission time of image, the computing in FPGA has all adopted multi-stage pipeline, ensures that each clock cycle completes once-through operation simultaneously.

For the outstanding good effect of the present invention, the present embodiment explains with an example.

As shown in Figure 3,4, Fig. 3 is the picture of proofreading and correct, and Fig. 4 proofreaies and correct picture afterwards.As can be seen from Figure 3, there is skew with respect to actual value in the gray value due to each pixel before carrying out gray correction, and the gray scale non-uniform degree of each ccd image sensor is different, so the picture in its entirety after Overlap-scanning can clearly see that the distribution between different CCD exists colour band, 0～255 grade of original distribution simultaneously has probably been compressed into 15～220 grades of distributions, the keynote of view picture figure is partially dark, some details between pixel, because the not obvious impact of contrast is observed, has a strong impact on the decipher of image.After overcorrect, gray scale is reverted to normal range (NR) again, and the image after splicing has been removed colour band, and picture quality obviously improves, and has reflected more truly the attribute of image, and details is more clear.The image of contrast adjacent C CD can find that image color is consistent, has substantially eliminated the aberration between sheet.

The present invention when general gray correction method is provided according to the concrete property of FPGA, updating formula is optimized, view data can be put into DDR memory cache simultaneously, make the picture transmission of algorithm correction and big data quantity all obtain optimization, whole system performance is all greatly improved.The present invention can realize the object that 1 clock cycle completes correcting algorithm, and it can not exert an influence to the real-time of system in concrete engineering application, and correcting algorithm has been carried out to specific implementation in CCD imaging control FPGA.Therefore, compared to existing technology, technological progress is fairly obvious in the present invention.

Above-described embodiment is only preferably one of implementation of the present invention; should be in order to not limit the scope of the invention; the technical scheme of all any change or the polishing of having no essential meaning done under body design thought of the present invention and spirit, all should be in protection scope of the present invention.

Claims (5)

1. an image real time correction output intent for broad width scanning instrument, is characterized in that, comprises the following steps:

(1), after system powers on, PC main frame sends scan instruction by USB module to FPGA main control chip;

(2) clocking and control signal after FPGA main control chip reception instruction, control N linear ccd image sensor lights simultaneously, and control CCD transmission module and sweep object is carried out to IMAQ according to N linear ccd image sensor of the scan pattern control of PC main frame requirement simultaneously, N is greater than 1 natural number; Meanwhile, the algoritic module in FPGA main control chip is using pure white and two kinds of colors of black as calibration point, and calculates respectively two correction parameter α and β according to following formula:

$\frac{255}{W-B}=1+m---\left(1\right)$

α+β＝m×256 (2)

Wherein, W represents to scan the gray value of pure white picture, and its value is the gray value that 220, B represents ater picture, and its value is that 15, m represents to retain the pure decimal of three after a decimal point; α is the integer part of the data obtained, the fractional part that B is the data obtained;

(3) view data of linear ccd image sensor acquisition scans object, and by this image data transmission to analog to digital converter, under the change over clock signal that analog to digital converter provides at FPGA main control chip, convert the analog signal of linear ccd image sensor output to digital signal, and the algoritic module being transferred in FPGA main control chip is processed;

(4) algoritic module adopts following formula to calculate the gray value A after its correction to first photosensitive unit ₁:

$A_1=x+\frac{(\mathrm{\&alpha;}+\mathrm{\&beta;})\&times;x}{2^8}-(1+\frac{\mathrm{\&alpha;}+\mathrm{\&beta;}}{256})\&times;B$

Wherein, X represents the gray value of first photosensitive unit of linear ccd image sensor actual acquisition;

(5) repeating step (4), until algoritic module all calculates the gray value A after remaining photosensitive unit correction; In repeating step (4) process, the view data that FPGA main control chip obtains correction is deposited in connected DDR memory temporarily;

(6) FPGA main control chip transfers to PC main frame by the gray value A after each each photosensitive unit self-correcting and processes, and PC main frame splices the view data of all linear ccd image sensor collections, obtains complete image, then image is shown.

2. the image real time correction output intent of a kind of broad width scanning instrument according to claim 1, is characterized in that, the model of described FPGA main control chip is Cyclone IV.

3. the image real time correction output intent of a kind of broad width scanning instrument according to claim 2, is characterized in that, described DDR memory is DDR II memory.

4. according to the image real time correction output intent of a kind of broad width scanning instrument described in any one of claim 1～3, it is characterized in that, in described step (2), described m represents to retain the pure decimal of four after a decimal point.

5. the image real time correction output intent of a kind of broad width scanning instrument according to claim 4, it is characterized in that, in described step (2), after two correction parameter α and β calculate, FPGA main control chip stores the two in connected flash memory into, afterwards when image correcting data, directly from this flash memory, two parameter alpha and β are read in the random access memory of FPGA main control chip inside, and in transmit image data, two correction parameter α and β are input in algoritic module.