CN104243868A - High-resolution CMOS (complementary metal oxide semiconductor) image sensor - Google Patents
High-resolution CMOS (complementary metal oxide semiconductor) image sensor Download PDFInfo
- Publication number
- CN104243868A CN104243868A CN201410513413.XA CN201410513413A CN104243868A CN 104243868 A CN104243868 A CN 104243868A CN 201410513413 A CN201410513413 A CN 201410513413A CN 104243868 A CN104243868 A CN 104243868A
- Authority
- CN
- China
- Prior art keywords
- signal
- pixel
- module
- image sensor
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The invention discloses a high-resolution CMOS (complementary metal oxide semiconductor) image sensor comprising a plurality of image sensor units. The image sensor units work independently and concurrently. Each image sensor unit comprises a pixel unit and a data processing and outputting unit. Each pixel unit comprises a pixel array composed of a plurality of pixels. Each data processing and outputting unit comprises a first control module, a plurality of double-sampling modules, a second control module, a column-level comparator module, a plurality of shifting register modules and a high-speed data interface module. The first control module controls selection and output of the pixels. The double-sampling modules correspond to the line numbers of the pixel arrays. The second control module controls the double-sampling modules to read and output pixel signals. The column-level comparator modules are used for performing analog-to-digital conversion on signals output by the double-sampling modules according to slope signals generated by a digital-to-analog conversion module. The shifting register modules are used for serially outputting converted digital signals. The high-speed data interface module pushes signals output by the shifting register modules to the outside. Follow-up data processing pressure of the CMOS image sensor can be reduced while extra-large pixels are realized.
Description
Technical field
The present invention relates to field of image sensors, particularly the high-resolution multichannel cmos image sensor of one.
Background technology
Imageing sensor is the important component part of composition digital camera.According to the difference of element, the large class of CCD and CMOS two can be divided into.Cmos sensor obtain a prerequisite of extensive use be its higher sensitivity had, compared with short exposure time and the Pixel Dimensions that day by day reduces.
As a rule, the frame data output rate of cmos image sensor is inversely proportional to pixel size, that is, for the cmos image sensor (as more than 50,000,000 pixels) of super large resolution, usual frame per second is also very low, be generally less than 1 second one frame.
But for some special applications, the cmos image sensor of super large resolution but needs to possess sufficiently high frame per second, such as, takes photo by plane in the application of CIS shooting at some, because needs catch high-precision ground resolution, usually need to possess very high cmos image sensor resolution.And because aircraft in application of taking photo by plane is usually in high-speed motion, therefore, needs the frame per second of cmos image sensor also higher, at least reach frame each second 5 ~ 10, like this could in high-speed motion situation, efficient record ground aerial photography effect.
Because CMOS technology possesses highly integrated, can on a chips integrated pixel portion and digital processing circuit part, be therefore highly suitable for the frame per second effectively improving imageing sensor.So the super-pixel cmos image sensor of superelevation frame per second is the emphasis of current super-pixel sensor technical field research.
The cmos image sensor of existing superelevation frame per second normally adopts single-channel data to export framework, if realize the data flow ability of more than 6,400 ten thousand very-high solution frames lower each second 10, mean and need each second to transmit 64M*10=640M pixel, each second, the throughput of 6.4 hundred million pixels was obviously very huge, will bring great pressure to back-end digital signal processor.
Summary of the invention
Main purpose of the present invention is the defect overcoming prior art, provides a kind of cmos image sensor of ultrahigh resolution, not only can realize the data flow ability of high frame per second, and significantly can reduce the pressure of picture element signal process.
For reaching above-mentioned purpose, the invention provides a kind of cmos image sensor, comprise multiple independent and image sensor cell of concurrent working, each described image sensor cell comprises a pixel cell and a data processing and output unit, and the pixel cell of each described image sensor cell is disposed adjacent between two and each described data processing and output unit are arranged at the periphery of each described pixel cell.Wherein, pixel cell described in each comprises a pel array be made up of multiple pixel.Data processing described in each and output unit comprise: the first control module, for choosing the pixel of described pel array, control the signal parallel of the pixel of same row in described pel array and to export and the signal controlled with the pixel of a line exports with predefined procedure; Multiple pairs of sampling modules, each row configuration of corresponding described pel array, for reading the signal of the pixel of each row of described pel array respectively and exporting; D/A converter module, produces the slope signal that characterizes digital signal and analog signal transformational relation; Multiple row level comparator module, is connected with each described pair of sampling module, arranges level comparator module, according to this slope signal, the analog signal that the two sampling modules be connected export is converted to digital signal described in each; Second control module, for control each described pair of sampling module walk abreast the pixel reading same row in described pel array signal and control two sampling module described in each to read each pixel of its corresponding row signal according to described predefined procedure; And the signal parallel controlling each pixel of the same row that each described pair of sampling module is read exports each described row level comparator module to; Multiple shift register module, is connected with each described row level comparator module, for the digital signal Serial output by described multiple row level comparator conversion; And high speed interface module, be connected with the output of described multiple shift register module, the digital signal of its Serial output is exported successively by it.
Preferably, pixel described in each comprises light sensitive diode, transfer tube, suspension node, reset transistor, source follower and row gate tube, and described transfer tube is connected with described light sensitive diode; The source electrode of the drain electrode of described transfer tube, the grid of described source follower, described reset transistor is connected to described suspension node; The input of the described pair of sampling module that the drain electrode of described row gate tube is connected with the source electrode of described source follower, source electrode is corresponding with this pixel is connected.For pixel described in each, described first control module controls described suspension node and carries out electric charge and empty and reset to export the first signal, control described transfer tube to carry out electric charge at described suspension node and empty and open to export secondary signal after resetting, the difference of described first signal and secondary signal is the signal of this pixel.
Preferably, described pair of sampling module comprises the first path and alternate path, the first read switch that described first path comprises series connection is with the first output switch and be connected the first ground capacity between the two, and the second read switch that described alternate path comprises series connection is with the second output switch and be connected the second ground capacity between the two.
Preferably, for sampling module two described in each, the opening and closing that described second control module controls the first read switch of this pair of sampling module, the first output switch, the second read switch and the second output switch with the first signal storage of the pixel read in described first ground capacity, the secondary signal of this pixel is stored in described second ground capacity, and described first signal and secondary signal is exported to the described row level comparator module that this pair of sampling module be connected simultaneously.
Preferably, this first signal that it receives by described row level comparator module and secondary signal are subtracted each other, and process to obtain corresponding digital signal to the difference obtained after subtracting each other.
Preferably, described second control module controls the reading that described multiple pairs of sampling modules carry out each described first signal of same row in described pel array simultaneously, and carries out the reading of each described secondary signal of these row in the completed more simultaneously; In this pel array that each described pair of sampling module of described second control module control is read, each described two paths of signals of same row exports the described row level comparator module that each correspondence is connected to simultaneously.
Preferably, the signal that described pair of coupled sampling module exports is converted to the digital signal of n position by described row level comparator module, and n is positive integer.
Preferably, the data memory format of described shift register module is n+3 position, store the digital signal of described n position respectively, the clock sync signal of a pixel, the clock sync signal of the clock sync signal of one-row pixels and an image sensor cell one frame pixel.
Preferably, described high speed interface module comprises n+3 parallel data-interface, and the n+3 bit data that described multiple shift register module exports each time is transferred to outside by described n+3 the data-interface walked abreast simultaneously.
Preferably, in image sensor cell described in each, the time of the digital signal Serial output of the pixel of same row is less than or equal to each described pair of sampling module and reads and export the time sum that time of the signal of the pixel of next column and the signal of each described row level comparator module to those pixels process by each described shift register module.
The invention has the advantages that and cmos image sensor is divided into multiple image sensor cell, the pixel cell of each image sensor cell forms the pel array of continuous seamless, and data processing and output unit form multiple independently data transmission channel, with respectively by the signal independent process of pel array corresponding part and output, compared to prior art, the data throughout of each data transmission channel of the present invention is able to remarkable reduction, therefore data processing and output unit is not only significantly reduced to the pressure of signal transacting, and significantly can reduce the design complexities of cmos image sensor.In addition imaging, data processing and output unit is distributed in the outside of pel array, thus occur black surround around each CMOS image sensor unit after also can be avoided in the outside of pel array.
Accompanying drawing explanation
Figure 1 shows that the schematic diagram of the cmos image sensor of one embodiment of the invention;
Figure 2 shows that the schematic diagram of an image sensor cell of one embodiment of the invention;
Figure 3 shows that the schematic diagram of two sampling modules of an image sensor cell of one embodiment of the invention;
Figure 4 shows that the transmission time sequence figure of the picture element signal of an image sensor cell of one embodiment of the invention;
Figure 5 shows that the schematic diagram of the high speed interface module of one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Cmos image sensor 1 of the present invention comprises multiple image sensor cell 10.Each image sensor cell 10 works alone, and multiple image sensor cell is concurrent working.Fig. 1 is the schematic diagram of the cmos image sensor of one embodiment of the invention, and as shown in Figure 1, image sensor cell 10 is 4, and adjacent distributions is two row two row between two.In the present embodiment, cmos image sensor 1 can realize the data flow ability of more than 64M pixel frame each second 10, because it divide into 4 image sensor cells worked alone 10, the sum of all pixels that each image sensor cell 10 comprises is 64M/4=16M pixel, therefore, under the prerequisite meeting the above data flow ability of 10 frame per second, the data throughout of each image sensor cell 10 each second is 16M*10=160M pixel, not only significantly reduce the pressure of rear digital signal process, and significantly reduce the design complexities of each image sensor cell.
Figure 2 shows that the schematic diagram of an image sensor cell 10, this image sensor cell 10 is positioned at the upper left corner of the cmos image sensor shown in Fig. 1.Incorporated by reference to seeing figures.1.and.2, each image sensor cell 10 includes a pixel cell and a data processing and output unit, and the pixel cell of each image sensor cell is disposed adjacent between two and each data processing and output unit are arranged at the periphery of each pixel cell.Wherein, each pixel cell comprises the pel array be made up of multiple pixel.Each data processing and output unit comprise the first control module 11, multiple pairs of sampling modules 12, D/A converter module 13, multiple row level comparator module 14, second control module 15, multiple shift register module 16 and high speed interface (LVDS) modules 17.Wherein, corresponding two sampling module 12, the row level comparison module 14 of the every one-row pixels of pel array and a shift register module 16.First control module 11 has decoding function, control choosing and the output of picture element signal of pixel in pel array, second control module 15 controls reading and the output of two sampling module, the corresponding digital signal of row level comparator module 14 for the analog signal that two sampling module 12 exports being converted to a slope signal of analog signal transformational relation according to the sign digital signal generated in D/A converter module 13, each shift register module 16 and each row level comparator module 14 connect one to one its corresponding each digital signal Serial output successively received, high speed interface module 17 is connected with the output of shift register module 16, the digital signal of shift register module 16 Serial output is exported to chip exterior by this high speed interface module 17.For convenience of the arrangement of modules in data processing and transmission unit, shift register module 16 and high speed interface module 17 are positioned at outermost, constitute the output channel of the pixel data after process.Although Fig. 2 only show an image sensor cell 10, but according to Fig. 1,4 identical image sensor cells 10 are symmetric with the center of cmos image sensor, 4 shift register modules constitute 4 data output channel respectively, data transfer direction as shown by the arrows in Figure 1, can form the four-way cmos image sensor of the present embodiment thus.
Next composition graphs 2 to Fig. 5 is illustrated the operation principle of the CMOS image sensor unit of one embodiment of the invention.Due to the completely the same and concurrent working of the working method of image sensor cell forming cmos image sensor, therefore hereafter will only be described in detail for an image sensor cell.
As previously mentioned, data processing and output unit comprise the first control module 11, multiple pairs of sampling modules 12, D/A converter module 13, multiple row level comparator module 14, second control module 15, multiple shift register module 16 and high speed interface modules 17.
Wherein, first control module 11 (decoding module) is for choosing the pixel in pel array and the signal parallel controlling the wherein pixel of same row exports and controls with the signal of the pixel of a line as to export according to particular order, such as first choose first that exports this row, then the 3rd, 5th pixel etc., and the picture element signal be not limited in same a line must export successively.Particularly, each pixel comprises light sensitive diode PD, transfer tube M4, row gate tube M1, reset transistor M3, source follower M2, suspension node P.Wherein, transfer tube M4 is connected with light sensitive diode PD, for reading the signal of light sensitive diode PD and exporting suspension node P to.The signal read from suspension node P is outputted to row gate tube M1 by the source electrode of source follower M2.Reset transistor M3 is used for emptying the electric charge of suspension node P and resetting.Row gate tube M1 is used for choosing pixel, and is exported by corresponding picture element signal.In order to realize choosing a certain pixel, the grid of row gate tube M1 is connected with a selected signal ROW, when this selected signal ROW sets high, chooses the pixel at this row gate tube M1 place.In order to realize operating each light sensitive diode separately, the grid of each transfer tube M4 is connected with a gating signal TX, and when gating signal TX sets high, this transfer tube M4 opens, and exports the signal of corresponding light sensitive diode PD to suspension node P.In order to the electric charge realizing suspension node P empties and resets, the grid of reset transistor M3 is connected with a reset signal RX, when this reset signal RX sets high, reset transistor M3 opens, make the current potential of suspension node P be driven high power supply Vdd, thus the electric charge of suspension node P is emptied, realize resetting.Wherein, gating signal TX, selected signal ROW, reset signal RX all can be produced by the first control module.Thus, by the control of the first control module 11 couples of gating signal TX, selected signal ROW and reset signal RX, the signal parallel that just can control 4000 pixels being positioned at same row in pel array export and the signal controlling to be positioned at 4000 pixels of same row for export according to particular order.
The each row configuration of multiple pairs of sampling module 12 respective pixel arrays, for reading respectively and exporting the signal of the pixel of each row.In the present embodiment, a pel array has 4000 row pixels, and therefore also correspondence is configured with 4000 two sampling modules 12.The reading of each pair of sampling module 12 and output action control by the second control module 15, second control module 15 controls each pair of sampling module 12 and to walk abreast the signal of the pixel of same row in read pixel array specifically, and the signal parallel also controlling each pixel of the same row that each pair of sampling module 12 is read exports connected each row level comparator module 14 to.Due under the control of the first control module 11, the signal with each pixel of a line is export according to particular order, and therefore each two sampling module 12 signal to each pixel of its corresponding row is also read according to particular order.
Please continue to refer to Fig. 3, in order to carry out the reading of picture element signal, each two sampling module 12 comprises two paths, and the first path has read switch S1 and the output switch S3 of series connection, is connected with ground capacity C1 between read switch S1 and output switch S3.Alternate path has read switch S2 and the output switch S4 of series connection, is connected with ground capacity C2 between read switch S2 and output switch S4.Second control module 15 carries out reading and the output of the signal of pixel by making ground capacity C1 and C2 to the open and close controlling of each read switch and output switch, wherein the first signal of exporting for pixel when storing the resetting charge of suspension node of ground capacity C1, the secondary signal that ground capacity C2 exports for the pixel stored when the rear transfer tube of suspension nod charge reset is opened, and namely the difference of the first signal and secondary signal represents the signal of this pixel.
The signal that two sampling module 12 exports transfers to row level comparator module 14 to carry out analog-to-digital conversion.Concrete, each row level comparator module 14 is connected with a two sampling module 12, and in the present embodiment, the row level comparator module 14 of an image sensor cell is also 4000.The signal that row level comparator module 14 once receives comprises the two paths of signals be made up of the first signal and secondary signal characterizing picture element signal, and both signal subtractions are obtained the signal of this pixel and carry out corresponding analog-to-digital conversion action by it.Specifically, row level comparator module 14 is carried out analog-to-digital according to the slope signal produced in D/A converter module 13.The slope signal that D/A converter module 13 produces and the corresponding conversion relation between analog signal and digital signal.Such as analog signal 0 ~ 2V corresponding digital signals 0 ~ 1024, slope signal is 0 ~ 2V/0 ~ 1024, suppose that the picture element signal that row level comparator module 14 receives is 1V, the 1V picture element signal that the analogue value corresponding for each digital signal in slope signal and its receive compares by row level comparator module 14 successively, and finally obtaining digital signal corresponding to 1V is 512.In pel array, the action of each row level comparator module 14 is synchronous, and the picture element signal received it is concurrently converted to corresponding digital signal.
Picture element signal through the process of row level comparator module 14 is passed to coupled multiple shift register modules 16 with Serial output successively.Multiple shift register module 16 is also each row configuration of respective pixel array.Wherein, the data memory format of each shift register module is n+3 position, wherein n represents the digital signal that row level comparator module 14 changes is n bit binary data, in addition three bit data represent the clock sync signal of a pixel respectively, the clock sync signal of one-row pixels, and the clock sync signal of this image sensor cell one frame pixel.In the present embodiment, digital signal is 12, then the data memory format of shift register module is 15.
High speed interface module 17 is connected with the output of each shift register module 16, for the signal of each shift register module 16 Serial output is pushed to chip exterior successively.Specifically, high speed interface module 17 comprises n+3 parallel LVDS data-interface, the n+3 bit data that each shift register module 16 exports each time is transferred to outside simultaneously.As shown in Figure 5, in the present embodiment, high speed interface module 17 comprises 15 parallel LVDS data-interfaces, wherein these 12 data-interfaces of D0 ~ D11 export the digital signal of 12, data-interface PIX_CLK correspondence exports the clock sync signal of a pixel, data-interface LINE_CLK correspondence exports the clock sync signal of one-row pixels, and data-interface PIC_CLK correspondence exports the clock sync signal of this image sensor cell one frame pixel.
Next, composition graphs 2 ~ 5 is described in detail sequencing control process that cmos image sensor of the present invention carries out Signal transmissions for an image sensor cell.
As previously mentioned, a pel array comprises 4000 × 4000 pixels, and correspondence has 4000 two sampling module, 4000 row level comparator module and 4000 shift register modules.When image sensor cell exposure is complete, from a certain row of pel array, carry out the transmission of the signal of pixel according to particular order, until the picture element signal end of transmission all arranged.
Example is transmitted as with what carry out picture element signal by column from first row.First, the transmission of first row picture element signal is carried out.
First control module 11 is by setting high 4000 pixels choosing pel array first row by corresponding selected signal ROW.Within the t1 time period, the signal RX1 of the reset transistor of these 4000 pixels chosen sets high by the first control module 11, empties and reset to suspension nod charge, and now the voltage of suspension node P is about Vdd voltage, as 3.3V.The voltage of row gate tube source electrode (pixel output) is that suspension node P voltage deducts the gate source voltage of source follower M2 and the drain-source voltage of row gate tube M1, as the first signal; Simultaneously, the read switch S1 that second control module 15 opens the first path of whole 4000 two sampling modules 12 reads the first signal of 4000 pixels respectively, keep the output switch S3 of the first path and alternate path to turn off simultaneously, thus read result stored in the ground capacity C1 corresponding to each first path by these 4000, then close each read switch S1.Then, within the t2 time period, the signal RX1 of the reset transistor of first row 4000 pixels sets low by the first control module 11, and reset transistor is ended; The signal TX1 of transfer tube is set to high level, now the signal of pixel is transferred to suspension node P, the voltage of suspension node P exports via source follower and row gate tube, the voltage of this output is that suspension node P voltage deducts the gate source voltage of source follower M2 and the drain-source voltage of row gate tube M1, as secondary signal; Second control module 15 opens the read switch S2 of the alternate path of 4000 two sampling modules 12 simultaneously, keep the output switch S4 shutoff of alternate path, the first path shutoff, to read 4000 secondary signals, and by reading result stored in the ground capacity C2 corresponding to each alternate path, the gating signal TX1 of each for first row pixel sets low by the first control module 11 afterwards.Therefore, within the t1+t2 time period, two sampling modules 12 of corresponding 1st row ~ the 4000th row first and two control module effect under read the first signal and be stored in ground capacity C1, reading secondary signal be stored in ground capacity C2, these 4000 two sampling module 12 actions are identical, and occur simultaneously.
After the t1+t2 time terminates, the picture element signal of all row of the 1st row in this pel array all completes storage, and now, row level comparator module 14 is started working.Concrete, output switch S3 and S4 that second control module 15 controls whole 4000 the two sampling modules 12 of row of pel array first row opens, thus is delivered to 4000 row level comparator module 14 processes storing the first signal and secondary signal two-way in ground capacity C1 and C2.First signal and secondary signal subtract each other and carry out according to the slope signal produced in D/A converter module 13 digital signal that analog-to-digital conversion obtains correspondence by each row level comparator module 14, and digital signal are exported to the corresponding shift register module 16 be connected.Be appreciated that the form of expression that this first signal and secondary signal are subtracted each other the difference obtained and can be considered to the signal of pixel, when incident light is stronger, it is more that this pixel carries out the electric charge that opto-electronic conversion obtains, then the difference of the first signal and secondary signal is also less.Therefore, after the T1=t1+t2+t3 time terminates, 4000 picture element signal that independently pel array the 1st arranges in image sensor cell 10 have all completed to read and changes and export 4000 shift register modules 16 of correspondence to.
Then, shift register module 16 within the t4 time period by 4000 digital train of signal line outputs to high speed data interface module 17, then export chip exterior to successively by high speed interface module.
Next carry out successively the 2nd row, the 3rd row ..., the 4000th row picture element signal transmission.In the present embodiment, 1st ~ 4000 row picture element signals transmit successively, but the first control module 11 control under, also other particular order can complete the transmission of each row picture element signal.Preferably, after, once the reading of row pixel and front once row pixel are carried out for simultaneously from shift register output after treatment.For the output of first row pixel after analog to digital converter process, while shift register module 16 is started working, the first control module 11 also starts the secondary series pixel choosing each array of sub-pixels, to carry out the signal-obtaining of each secondary series pixel.Specifically, T2 time, the digital signal of shift register module 16 each pixel of Serial output whole array of sub-pixels first row within the t4 time period; Simultaneously under the effect of the first and second control modules, within the t1+t2 time period, the secondary series pixel of 4 array of sub-pixels is selected, and the first signal storage of each secondary series pixel is stored in corresponding ground capacity C2 in corresponding ground capacity C1, secondary signal by two sampling modules 12 of corresponding 1st row ~ the 4000th row of each array of sub-pixels, and two sampling module actions corresponding to 4 array of sub-pixels are identical, and occur simultaneously.Within the ensuing t3 time period, the analog signal of 4000 secondary series pixels is converted to corresponding digital signal according to the slope signal that D/A converter module 13 generates by 4000 row level comparator module 14.It should be noted that, the t3 time period of T2 terminate, row level comparator module by the digital signal of secondary series pixel export before, the whole Serial output successively of digital signal that 4000 shift register modules 16 must will wherein store, is pushed to chip exterior by high speed interface module 17.That is to say, shift register module 16 the time t4 of the digital signal Serial output of previous column pixel is less than after a row pixel reading and change-over time t1+t2+t3.
Therefore, through T1+T2+ ... after+T4000+t4 the time, this independently the digital signal of the pixel of image sensor cell provide interface by 15 each parallel high speeds and be sent to chip exterior with 15 tunnels.
The working method of other image sensor cells and aforesaid way completely the same and carry out simultaneously, the cmos image sensor of whole 8000 × 8000 has 60 high speed interfaces.Therefore, through T1+T2+ ... after+T4000+t4 the time, four image sensor cells pixel data after treatment all respectively by 4 independently data output channel be successfully pushed to chip exterior.
As in the present embodiment, the resolution of cmos image sensor is 8000 × 800,0=6,400 ten thousand, suppose that frame per second is 10 frames per second, then the data throughput of each image sensor cell is a 64/4*10=160M per second pixel, then each image sensor cell is to process (reading conversion) the time T1=1/10/4000=25us of every row pixel.Owing to signal will be carried out analog-to-digital conversion in the t3 time period, and be carry out reading to the analog signal of pixel to export within the t1+t2 time, therefore in general the t3 time period should be greater than the t1+t2 time period as far as possible, as t1+t2=5us can be set, and t3=20us.Now, each row level comparator module 14 needs the data of process 1 pixel within the t3=20us time, shift register module will remove 4000 data in t1+t2+t3=25us, namely every 6.25ns shifts out data, therefore shift register module to shift out data frequency minimum for 160MHz.
In sum, the cmos image sensor with ultrahigh resolution of the present invention has shared the pressure of picture element signal process by arranging multiple independently image sensor cell, reduce the design pressure of data processing section, and improve the efficiency to picture element signal process.
Although the present invention discloses as above with preferred embodiment; right described many embodiments are citing for convenience of explanation only; and be not used to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. a cmos image sensor, it is characterized in that, comprise multiple independent and image sensor cell of concurrent working, each described image sensor cell comprises a pixel cell and a data processing and output unit, and the pixel cell of each described image sensor cell is disposed adjacent between two and each described data processing and output unit are arranged at the periphery of each described pixel cell; Wherein,
Pixel cell described in each comprises a pel array be made up of multiple pixel;
Data processing described in each and output unit comprise:
First control module, for choosing the pixel of described pel array, controls the signal parallel of the pixel of same row in described pel array and to export and the signal controlled with the pixel of a line exports with predefined procedure;
Multiple pairs of sampling modules, each row configuration of corresponding described pel array, for reading the signal of the pixel of each row of described pel array respectively and exporting;
D/A converter module, produces the slope signal that characterizes digital signal and analog signal transformational relation;
Multiple row level comparator module, is connected with each described pair of sampling module, arranges level comparator module, according to this slope signal, the analog signal that the two sampling modules be connected export is converted to digital signal described in each;
Second control module, for control each described pair of sampling module walk abreast the pixel reading same row in described pel array signal and control two sampling module described in each to read each pixel of its corresponding row signal according to described predefined procedure; And the signal parallel controlling each pixel of the same row that each described pair of sampling module is read exports each described row level comparator module to;
Multiple shift register module, is connected with each described row level comparator module, for the digital signal Serial output by described multiple row level comparator conversion; And
High speed interface module, is connected with the output of described multiple shift register module, the digital signal of its Serial output is exported successively.
2. cmos image sensor according to claim 1, is characterized in that, pixel described in each comprises light sensitive diode, transfer tube, suspension node, reset transistor, source follower and row gate tube, and described transfer tube is connected with described light sensitive diode; The source electrode of the drain electrode of described transfer tube, the grid of described source follower, described reset transistor is connected to described suspension node; The input of the described pair of sampling module that the drain electrode of described row gate tube is connected with the source electrode of described source follower, source electrode is corresponding with this pixel is connected;
For pixel described in each, described first control module controls described suspension node and carries out electric charge and empty and reset to export the first signal, control described transfer tube to carry out electric charge at described suspension node and empty and open to export secondary signal after resetting, the difference of described first signal and secondary signal is the signal of this pixel.
3. cmos image sensor according to claim 2, it is characterized in that, described pair of sampling module comprises the first path and alternate path, the first read switch that described first path comprises series connection is with the first output switch and be connected the first ground capacity between the two, and the second read switch that described alternate path comprises series connection is with the second output switch and be connected the second ground capacity between the two.
4. cmos image sensor according to claim 3, it is characterized in that, for sampling module two described in each, the opening and closing that described second control module controls the first read switch of this pair of sampling module, the first output switch, the second read switch and the second output switch with the first signal storage of the pixel read in described first ground capacity, the secondary signal of this pixel is stored in described second ground capacity, and described first signal and secondary signal is exported to the described row level comparator module that this pair of sampling module be connected simultaneously.
5. cmos image sensor according to claim 4, is characterized in that, this first signal that it receives by described row level comparator module and secondary signal are subtracted each other, and processes to obtain corresponding digital signal to the difference obtained after subtracting each other.
6. cmos image sensor according to claim 2, it is characterized in that, described second control module controls the reading that described multiple pairs of sampling modules carry out each described first signal of same row in described pel array simultaneously, and carries out the reading of each described secondary signal of these row in the completed more simultaneously; In this pel array that each described pair of sampling module of described second control module control is read, each described two paths of signals of same row exports the described row level comparator module that each correspondence is connected to simultaneously.
7. the cmos image sensor according to any one of claim 1 to 6, is characterized in that, the signal that described pair of coupled sampling module exports is converted to the digital signal of n position by described row level comparator module, and n is positive integer.
8. cmos image sensor according to claim 7, it is characterized in that, the data memory format of described shift register module is n+3 position, store the digital signal of described n position respectively, the clock sync signal of a pixel, the clock sync signal of the clock sync signal of one-row pixels and an image sensor cell one frame pixel.
9. cmos image sensor according to claim 8, it is characterized in that, described high speed interface module comprises n+3 parallel data-interface, and the n+3 bit data that described multiple shift register module exports each time is transferred to outside by described n+3 the data-interface walked abreast simultaneously.
10. cmos image sensor according to claim 1, it is characterized in that, in image sensor cell described in each, the time of the digital signal Serial output of the pixel of same row is less than or equal to each described pair of sampling module and reads and export the time sum that time of the signal of the pixel of next column and the signal of each described row level comparator module to those pixels process by each described shift register module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410513413.XA CN104243868B (en) | 2014-09-29 | 2014-09-29 | High resolution cmos image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410513413.XA CN104243868B (en) | 2014-09-29 | 2014-09-29 | High resolution cmos image sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104243868A true CN104243868A (en) | 2014-12-24 |
| CN104243868B CN104243868B (en) | 2017-11-10 |
Family
ID=52231114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410513413.XA Active CN104243868B (en) | 2014-09-29 | 2014-09-29 | High resolution cmos image sensor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104243868B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104486564A (en) * | 2014-12-26 | 2015-04-01 | 上海集成电路研发中心有限公司 | Super-large-resolution CMOS image sensor and clock synchronizing method thereof |
| CN108845157A (en) * | 2018-05-16 | 2018-11-20 | 上海集成电路研发中心有限公司 | A kind of photoelectric velocity measurement chip |
| CN109643454A (en) * | 2016-08-10 | 2019-04-16 | Ux 株式会社 | The solid figure integration system and method for integrated CMOS induction |
| CN116155395A (en) * | 2023-04-19 | 2023-05-23 | 深圳华创芯光科技有限公司 | Optical wireless communication space division multiplexing receiving device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923840A (en) * | 2010-06-12 | 2010-12-22 | 武汉大学 | High-capacity and ultra high-speed image digital signal generator based on programmable logic device |
| CN101990070A (en) * | 2009-08-03 | 2011-03-23 | 索尼公司 | Solid-state image sensing device, analog-digital conversion method of solid-state image sensing device, and electronic apparatus |
| CN102811059A (en) * | 2011-05-31 | 2012-12-05 | 海力士半导体有限公司 | Automatic offset adjustment for digital calibration of column parallel single-slope adcs for image sensors |
| CN102938410A (en) * | 2012-12-03 | 2013-02-20 | 上海集成电路研发中心有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor) image sensor manufacturing method |
| CN103281494A (en) * | 2013-05-03 | 2013-09-04 | 上海集成电路研发中心有限公司 | Complementary metal-oxide semiconductor (CMOS) image sensor and transmission method for image data of CMOS image sensor |
| EP2760198A1 (en) * | 2013-01-25 | 2014-07-30 | Innovaciones Microelectrónicas S.L. (Anafocus) | Advanced region of interest function for image sensors |
-
2014
- 2014-09-29 CN CN201410513413.XA patent/CN104243868B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101990070A (en) * | 2009-08-03 | 2011-03-23 | 索尼公司 | Solid-state image sensing device, analog-digital conversion method of solid-state image sensing device, and electronic apparatus |
| CN101923840A (en) * | 2010-06-12 | 2010-12-22 | 武汉大学 | High-capacity and ultra high-speed image digital signal generator based on programmable logic device |
| CN102811059A (en) * | 2011-05-31 | 2012-12-05 | 海力士半导体有限公司 | Automatic offset adjustment for digital calibration of column parallel single-slope adcs for image sensors |
| CN102938410A (en) * | 2012-12-03 | 2013-02-20 | 上海集成电路研发中心有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor) image sensor manufacturing method |
| EP2760198A1 (en) * | 2013-01-25 | 2014-07-30 | Innovaciones Microelectrónicas S.L. (Anafocus) | Advanced region of interest function for image sensors |
| CN103281494A (en) * | 2013-05-03 | 2013-09-04 | 上海集成电路研发中心有限公司 | Complementary metal-oxide semiconductor (CMOS) image sensor and transmission method for image data of CMOS image sensor |
Non-Patent Citations (1)
| Title |
|---|
| 李晓晨: "CMOS图像传感器系统中的列并行高速ADC的研究设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104486564A (en) * | 2014-12-26 | 2015-04-01 | 上海集成电路研发中心有限公司 | Super-large-resolution CMOS image sensor and clock synchronizing method thereof |
| CN104486564B (en) * | 2014-12-26 | 2018-02-27 | 上海集成电路研发中心有限公司 | A kind of super large resolution ratio cmos image sensor and its clock synchronizing method |
| CN109643454A (en) * | 2016-08-10 | 2019-04-16 | Ux 株式会社 | The solid figure integration system and method for integrated CMOS induction |
| CN109643454B (en) * | 2016-08-10 | 2023-09-05 | 智芯(广东)半导体智能科技有限公司 | Integrated CMOS induced stereoscopic image integration system and method |
| CN108845157A (en) * | 2018-05-16 | 2018-11-20 | 上海集成电路研发中心有限公司 | A kind of photoelectric velocity measurement chip |
| CN116155395A (en) * | 2023-04-19 | 2023-05-23 | 深圳华创芯光科技有限公司 | Optical wireless communication space division multiplexing receiving device |
| CN116155395B (en) * | 2023-04-19 | 2023-07-07 | 深圳华创芯光科技有限公司 | Optical wireless communication space division multiplexing receiving device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104243868B (en) | 2017-11-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11076119B2 (en) | Solid state imaging device, method of controlling solid state imaging device, and program for controlling solid state imaging device | |
| CN101409772B (en) | Data processing device, solid-state imaging device, imaging device, and electronic apparatus | |
| CN104822034A (en) | Solid State Imaging Apparatus And Imaging System | |
| WO2015113407A1 (en) | Image sensor and data tranmission method thereof | |
| US10542231B2 (en) | Method of driving image pickup device, image pickup device, image pickup system | |
| US20120147229A1 (en) | Two-by-two pixel structure in an imaging system-on-chip | |
| CN104301639A (en) | CMOS image sensor with ultra high frame rate | |
| CN108184081A (en) | A kind of high-speed data reading circuit in cmos image sensor | |
| CN104243868A (en) | High-resolution CMOS (complementary metal oxide semiconductor) image sensor | |
| CN103139500B (en) | Reading circuit and operation time sequence based on sigma-delta analog to digital converter (ADC) and used for imaging sensor | |
| CN103533267A (en) | Column-level ADC (analog to digital converter) based pixel division and combination image sensor and data transmission method | |
| CN102595060A (en) | Analog accumulator capable of implementing time delay integration (TDI) function inside complementary metal-oxide semiconductor (CMOS) image sensor | |
| US20160316165A1 (en) | Image sensor and data tranmission method thereof | |
| CN102387319B (en) | Photoelectric conversion apparatus and image pickup system | |
| CN103888688A (en) | Time sequence generating device for driving charge-coupled device | |
| CN108521549A (en) | A kind of super large face array CMOS image sensor structure | |
| US10015418B2 (en) | TDI line image sensor including source follower amplifiers | |
| CN105516625B (en) | Cmos image sensor pixel merges reading circuit structure and signal processing reading method | |
| CN107040733B (en) | CMOS image sensor | |
| CN102164251B (en) | Signal processing circuit and signal processing method for image sensor | |
| CN103975579A (en) | Solid-state imaging element, method for driving same, and camera system | |
| US8907835B2 (en) | A/D conversion circuit and solid-state image pickup device | |
| CN102387318B (en) | Solid-state image pickup apparatus and image pickup system | |
| CN104580952A (en) | Global image element CMOS (complementary metal oxide semiconductor) image sensor system architecture and signal transmission method thereof | |
| CN111669526B (en) | CMOS image sensor for improving frame frequency high-speed all-digital data reading |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Li Chen Inventor after: Jiang Bin Inventor before: Li Chen |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |