CN104486564A - Super-large-resolution CMOS image sensor and clock synchronizing method thereof - Google Patents
Super-large-resolution CMOS image sensor and clock synchronizing method thereof Download PDFInfo
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Abstract
The invention discloses a super-large-resolution CMOS image sensor and a clock synchronizing method of the super-large-resolution CMOS image sensor. Mutually-mirroring multi-channel CMOS image sensor units are adopted, each CMOS image sensor unit is provided with a phase-locked loop of the corresponding CMOS image sensor unit and an independent back-end data transmission interface, functions of all independent PLLs are changed through different digital configuration modes of different channels, that is, input and output interfaces of all the independent PLLs are configured to achieve clock synchronizing so as to achieve the purpose that independent internal clock signals in multi-channel CMOS image sensors control digital signal processing chips on the rear portions of the independent internal clock signals to conduct synchronous work, and meanwhile the design complexity is lowered.
Description
Technical field
The invention belongs to field of image sensors, relate to a kind of super large resolution four-way complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, be called for short CMOS) image sensor system framework, particularly relate to a kind of super large resolution cmos image sensor (being called for short CIS) clock synchronizing method.
Background technology
Imageing sensor is the important component part of composition digital camera, according to the difference of element, can be divided into charge coupled cell (Charge-coupled Device is called for short CCD) imageing sensor and the large class of cmos image sensor two.Cmos sensor obtain a prerequisite of extensive use be its higher sensitivity had, compared with short exposure time and the Pixel Dimensions that day by day reduces.
As a rule, the frame data output rate of cmos image sensor is inversely proportional to pixel size, that is, for the cmos image sensor (as more than 50,000,000 pixels) of super large resolution, usual frame per second is also very low, be generally less than 1 second one frame.
In some applications, the cmos image sensor of super large resolution but needs to possess sufficiently high frame per second, such as, takes photo by plane in the application of CIS shooting at some, because needs catch high-precision ground resolution, usually need to possess very high cmos image sensor resolution.
But, because in application of taking photo by plane, aircraft, usually in high-speed motion, therefore, needs the frame per second of cmos image sensor also higher, at least reaches frame each second 5 ~ 10, like this could in high-speed motion situation, efficient record ground aerial photography effect.
Usually, for the imageing sensor of super-pixel, if adopt CMOS technology, just can possess highly integrated feature, namely can on a chips integrated pixel and digital processing circuit.Therefore the frame per second effectively improving imageing sensor is highly suitable for.Therefore, the super-pixel cmos image sensor of high frame per second is the emphasis of current super-pixel sensor field research.
It will be apparent to those skilled in the art that the CIS chip for super large resolution, can improve transfer of data frame per second by multichannel CIS framework, multichannel CIS can effectively reduce the transfer of data pressure of each independent CIS.Such as, refer to Fig. 1, Fig. 1 is the cmos image sensor that current industry compares the four-way of main flow, as shown in the figure, in order to realize the data flow ability of more than 6,400 ten thousand very-high solution frames lower each second 10, if the system architecture adopting traditional single channel to export, meaning and needing each second to transmit 64M*10=640M pixel, each second, 6.4 hundred million pixel throughputs were very huge, will bring great pressure to the digital signal processor at rear.Therefore, super-pixel cmos image sensor system architecture realizes based on multichannel.
Each channel cmos imageing sensor needs independently clock source, and namely independently phase-locked loop or phase-locked loop (Phase Locked Loop is called for short PLL) carry out work.As shown in Figure 2, for each independent cmos image sensor, the input/output interface of this clock source PLL comprises:
(1) standard time clock input, this standard time clock is provided by the crystal oscillator (Crystal Oscillator) outside sheet;
(2) this standard time clock controls to produce internal clock signal, inner for each corresponding independent cmos image sensor.As shown in Figure 3.Because each passage is that complete mirror image is consistent, therefore, the cmos image sensor of whole super large resolution has four independently PLL.
But, because whole cmos image sensor has been divided into multiple passage, for four passages, so the data transmission interface of CIS rear end also has four autonomous channels, Digital Signal Processing (the digital signal processing at super large resolution CIS rear, being called for short DSP) chip will gather and process the data of these four autonomous channels, then, is spliced into a width integral photograph.Taking photo by plane in application, need the photomosaic of four independent acquisition to become a width integral photograph.
And for the cmos image sensor of this super large resolution, owing to have employed four independently PLL, mean the data of four passages export be do not associate mutually, nonsynchronous mutually.Because each CIS in four-way works alone, therefore, Digital Signal Processing (the digital signal processing at super large resolution CIS rear, being called for short DSP) chip can receive independently four channel datas, if this independently has time delay or nonsynchronous situation between four channel datas, four photos so after dsp chip process will be dislocation (such as: four photos be spliced are not taken simultaneously).
Therefore, how to solve the out of step conditions occurred in above-mentioned super-pixel imageing sensor CIS, become one of important topic of current super-pixel imageing sensor.
Summary of the invention
Main purpose of the present invention is to provide a kind of super large resolution cmos image sensor and clock synchronizing method thereof, it changes the function of each independent PLL by the different digital configuration mode of different passage, namely configure the input/output interface of each independent PLL to realize clock synchronous, to realize respective independent internal clocks signal in multichannel cmos image sensor, go the digital signal processing chip synchronous working controlling respective rear.
For reaching above-mentioned purpose, the invention provides a kind of super large resolution cmos image sensor, described cmos image sensor is N channel cmos image sensor, it is stitched together by N number of independent CMOS image sensor unit and on a single die integrated, described N number of independently CMOS image sensor unit is mutual mirror image, each has respective phase-locked loop and independently Back end data coffret, and N number of independently phase-locked loop is identical; Wherein, N be more than or equal to 2 positive integer; Described in each, the input/output interface of phase-locked loop comprises: standard time clock input port, one for residing for the inner internal clock signal output port of CMOS image sensor unit, and multiple output frequency interface; One in described N number of CMOS image sensor unit is configured to main CMOS image sensor unit: described main phase-locked loop standard time clock input port receives the standard time clock that the crystal oscillator outside described chip provides, the internal clock signal output port of described main phase-locked loop provides its internal clock signal, and described main phase-lock-ring output frequency interface exports described standard time clock; Residue N-1 in described N number of CMOS image sensor unit is configured to from CMOS image sensor unit: the described standard time clock input port sky from phase-locked loop connects, the described internal clock signal output port from phase-locked loop provides respective internal clock signal, described from phase-lock-ring output frequency interface one of them for receiving described standard time clock; And remainingly described be used for the output of described standard time clock from phase-lock-ring output frequency interface or sky connects; Wherein, the described described standard time clock from phase-lock-ring output frequency interface comes from the standard time clock or other standard time clock exported from phase-lock-ring output frequency interface that described main phase-lock-ring output frequency interface exports, with the digital signal processing chip synchronous working at the independent internal clocks signal controlling realizing described N number of CMOS image sensor unit rear separately.
Preferably, described N is even number.
Preferably, described N is 4.
Preferably, described four CMOS image sensor unit are mutual mirror images; Wherein, one in described four CMOS image sensor unit is configured to main CMOS image sensor unit: described main phase-locked loop standard time clock input port receives the standard time clock that the crystal oscillator outside described chip provides, the internal clock signal output port of described main phase-locked loop provides its internal clock signal, and described main phase-lock-ring output frequency interface exports described standard time clock; Residue three in described four CMOS image sensor unit is configured to from CMOS image sensor unit: the described standard time clock input port sky from phase-locked loop connects, described internal clock signal second output port from phase-locked loop provides respective internal clock signal, described main CMOS image sensor unit at least has two input and output frequency interface, input and output frequency interface outputting standard clock to described in transverse side from phase-locked loop; Another input and output frequency interface outputting standard clock described is given vertical sideways described from phase-locked loop; And input from phase-lock-ring output frequency interface from above-mentioned two output frequency interface standard time clocks of any one from phase-locked loop described in remaining one.
Preferably, the standard clock signal that described crystal oscillator provides is 16MHz, and the internal clock signal that each phase-locked loop produces is 256MHz.
For reaching above-mentioned purpose, the present invention also provides a kind of clock synchronizing method adopting above-mentioned super large resolution cmos image sensor, and it comprises clock synchronous step S1 and data syn-chronization transmission step S2;
Described clock synchronous step S1 comprises:
Step S11: the standard time clock from the outer crystal oscillator of described chip is supplied to described main phase-locked loop standard time clock input port, and described main phase-lock-ring output frequency interface exports described standard time clock;
From the described standard time clock of phase-lock-ring output frequency interface described in step S12: at least 1;
Step S13: the standard time clock that residue is described to be exported from phase-lock-ring output frequency interface main described in phase-lock-ring output frequency interface or described in other from the standard time clock that phase-lock-ring output frequency interface exports;
Described data syn-chronization transmission step S2 comprises:
Step S21: described main phase-locked loop and described from phase-locked loop internal clock signal output port under the control of described standard time clock, produce respective synchronous internal clock signal;
Step S22: the internal clock signal of described N number of CMOS image sensor unit independently controls the digital signal processing chip synchronous working at respective rear.
As can be seen from technique scheme, super large resolution cmos image sensor of the present invention and clock synchronizing method thereof, solve because each CIS in multichannel works alone very well, the dsp chip at super large resolution CIS rear can receive independently multiple channel data, thus causes independently having time delay or nonsynchronous situation between multiple channel data.It is emphasized that, although each CIS design in multichannel is consistent (namely produced chip is also consistent), but the present invention still can change the function of each independent PLL by the different digital configuration mode of different passage, namely configure the input/output interface of each independent PLL to realize above-mentioned clock synchronous, meanwhile, design complexities is reduced.
Accompanying drawing explanation
Fig. 1 is the cmos image sensor configuration diagram that current industry compares the four-way of main flow
Fig. 2 is the schematic diagram of the clock generating mode of the cmos image sensor framework being applied to four-way in prior art
Fig. 3 is the schematic diagram of PLL input/output interface in the cmos image sensor framework being applied to four-way in prior art
Fig. 4 is the schematic diagram that the present invention is applied to the clock generating mode embodiment of the cmos image sensor framework of four-way
Fig. 5 is the schematic diagram that the present invention is applied to PLL input/output interface embodiment in the cmos image sensor framework of four-way
Embodiment
Some exemplary embodiments embodying feature & benefits of the present invention describe in detail in the explanation of back segment.Be understood that the present invention can have various changes in different examples, it neither departs from the scope of the present invention, and explanation wherein and being shown in essence when the use explained, and be not used to limit the present invention.
It should be noted that, in order to reduce design complexities, in super large resolution cmos image sensor of the present invention, multiple independent CMOS image sensor unit is stitched together and on a single die integrated, normally be made up of even number CMOS image sensor unit, that is, multiple independently CMOS image sensor unit is mutual mirror image, and each has respective phase-locked loop and independently Back end data coffret, and multiple independently phase-locked loop is identical.
The input/output interface of each phase-locked loop comprises: standard time clock input port, one for residing for the inner internal clock signal output port of CMOS image sensor unit, and multiple output frequency interface.Super large resolution cmos image sensor clock synchronizing method of the present invention, it changes the function of each independent PLL by the different digital configuration mode of different passage, namely configure the input/output interface of each independent PLL to realize clock synchronous, to realize respective independent internal clocks signal in multichannel cmos image sensor, go the digital signal processing chip synchronous working controlling respective rear.
Above-mentioned and other technical characteristic and beneficial effect, by conjunction with the embodiments and accompanying drawing 4-Fig. 5 the present invention is configured after four-way cmos image sensor and and clock synchronizing method be described in detail.
Those skilled in the art are fully aware of, and the cmos image sensor of the four-way that this patent adopts, each passage is an independent image transducer respectively, when throughput data stream, if each imageing sensor (64M/4=16M pixel) works alone.Therefore, each second, the data throughout of every passage was 16M*10=160M pixel, not only significantly reduced the pressure of rear digital signal processor, and, also significantly reduce the design pressure of each channel cmos imageing sensor.
Refer to Fig. 4, Fig. 4 is Fig. 4 is the schematic diagram that the present invention is applied to the clock generating mode embodiment of the cmos image sensor framework of four-way.In the cmos image sensor of super large resolution as shown in the figure, arrange four cmos image sensor passages up and down, the CMOS image sensor unit of each passage still adopts respective PLL.Due to four independently CMOS image sensor unit be that mutual mirror image is consistent, therefore, four independently PLL be also on all four.In an embodiment of the present invention, although employing is consistent produced chip, the function of each independent PLL can be changed by the different digital configuration mode of different passage.
The cmos image sensor framework of the four-way in Fig. 4 is identical with framework shown in Fig. 3: the input/output interface of each phase-locked loop comprises: standard time clock input port, one for residing for the inner internal clock signal output port of CMOS image sensor unit, and multiple output frequency interface.
Framework shown in the cmos image sensor framework of the four-way in Fig. 4 and Fig. 3 unlike: one in four CMOS image sensor unit is configured to main CMOS image sensor unit: the standard time clock that the crystal oscillator outside main phase-locked loop standard time clock input port receiving chip provides, the internal clock signal output port of main phase-locked loop provides its internal clock signal, main phase-lock-ring output frequency interface outputting standard clock; Residue in four CMOS image sensor unit three is configured to from CMOS image sensor unit: connect from the standard time clock input port sky of phase-locked loop, there is provided respective internal clock signal from the internal clock signal output port of phase-locked loop, from phase-lock-ring output frequency interface one of them for receiving described standard time clock; And remainingly described be used for the output of standard time clock from phase-lock-ring output frequency interface or sky connects; Wherein, the standard time clock or other standard time clock exported from phase-lock-ring output frequency interface that main phase-lock-ring output frequency interface exports is come from, with the digital signal processing chip synchronous working at the independent internal clocks signal controlling realizing four CMOS image sensor unit rear separately from the standard time clock of phase-lock-ring output frequency interface.
That is, different passage is an independently CIS function, means and comprises independently digital control approach, as being configured by the IP configuration bit of digital IIC module to each passage.So, after each passage has had unified reference frequency, just can be configured respectively by the IP of the digital control module of each passage to each passage, and it is synchronous owing to carry out clock frequency, all digital control (comprising sequential, clock etc.) is all synchronous, the CIS of all like this passages can carry out image taking simultaneously, thus achieves the synchronous of large face battle array CIS.
Particularly, refer to Fig. 4 again, in the present embodiment, upper left PLL is configured to main CMOS image sensor unit, its standard time clock input port accepts the crystal oscillator Crystal Oscillator standard clock signal from external system, this is also unique input standard clock signal of this super-pixel CIS, the PLL of its excess-three passage is configured to from CMOS image sensor unit: connect from the standard time clock input port sky of phase-locked loop, does not accept the crystal oscillator Crystal Oscillator signal from external system.
Refer to Fig. 5, Fig. 5 is the schematic diagram that the present invention is applied to PLL input/output interface embodiment in the cmos image sensor framework of four-way.As shown in Figure 5, the PLL functional configuration of the design of four principal and subordinate PLL is different, and for upper left main PLL, the input/output interface of this main PLL is configured to:
(1) standard time clock input port, it provides standard time clock by the crystal oscillator Crystal Oscillator outside sheet;
(2) internal clock signal output port: produce internal clock signal inner for main CMOS image sensor unit;
(3) two input and output frequency interface, connecting from PLL for transverse side, another input and output frequency interface connects from PLL for vertical sideways.
For top-right from PLL, should be configured to from the input/output interface of PLL:
(1) internal clock signal output port: produce internal clock signal inner for being somebody's turn to do from CMOS image sensor unit;
(2) left side incoming frequency interface inputs as standard time clock; Eliminate the connection of external crystal oscillator Crystal Oscillator signal, eliminate below output frequency interface and connect.
For this from PLL, because the incoming frequency adopted is that the main PLL in upper left side produces, therefore, should be synchronous with upper left main PLL from the clock of PLL, namely crystal oscillator Crystal Oscillator signal outer with unique sheet is synchronous.
For lower left from PLL, should be configured to from the input/output interface of PLL:
(1) internal clock signal output port: produce internal clock signal inner for being somebody's turn to do from CMOS image sensor unit;
(2) upside incoming frequency interface inputs as standard time clock, eliminates the connection of external crystal oscillator Crystal Oscillator signal, eliminates top output frequency interface and connects.
For this from PLL, because the incoming frequency adopted is that the main PLL in upper left side produces, therefore, should be synchronous with the main PLL in upper left side from the clock of PLL, namely crystal oscillator Crystal Oscillator signal outer with unique sheet is synchronous.
For bottom-right from PLL, should be configured to from the input/output interface of PLL:
(1) internal clock signal output port: produce internal clock signal inner for being somebody's turn to do from CMOS image sensor unit;
(2) upside incoming frequency interface inputs as standard time clock, eliminates the connection of external crystal oscillator Crystal Oscillator signal, eliminates left output frequency interface and connects.
For this from PLL, because the incoming frequency adopted is that upper right side produces from PLL, therefore, should be synchronous from PLL with upper right side from the clock of PLL, also be namely synchronous with upper left from PLL, namely crystal oscillator Crystal Oscillator signal outer with unique sheet is synchronous.
Certainly, in of the present invention other is implemented, also should accept from the standard clock signal of lower left from PLL by left side incoming frequency interface from PLL.
Such as, the standard clock signal of crystal oscillator Crystal Oscillator is 16MHz, the internal clock signal that each PLL produces for respective independent CMOS image sensor unit is inner is 256MHz, it is 16MHz that the main PLL in upper left side to export for upper right side from the frequency of PLL, it is 16MHz that the main PLL in upper left side to export for lower left from the frequency of PLL, and upper right side is 16MHz for lower right from the frequency of PLL from PLL output.
It is emphasized that, adopt the super large resolution cmos image sensor of above-mentioned design consistent (namely produced chip is also consistent), the present invention can change the function of each independent PLL by the different digital configuration mode of different passage, namely configure the input/output interface of each independent PLL to realize above-mentioned clock synchronous.
In one embodiment of the invention, adopt the clock synchronizing method of above-mentioned super large resolution cmos image sensor, comprise clock synchronous step S1 and data syn-chronization transmission step S2;
Clock synchronous step S1 comprises:
Step S11: the standard time clock from the outer crystal oscillator of chip is supplied to main phase-locked loop standard time clock input port, and main phase-lock-ring output frequency interface exports described standard time clock;
Step S12: at least 1 standard time clock from phase-lock-ring output frequency interface;
Step S13: remain the standard time clock or other standard time clock exported from phase-lock-ring output frequency interface that export from the main phase-lock-ring output frequency interface of phase-lock-ring output frequency interface;
Data syn-chronization transmission step S2 comprises:
Step S21: main phase-locked loop and from phase-locked loop internal clock signal output port under the control of standard time clock, produce respective synchronous internal clock signal;
Step S22: the internal clock signal of multiple CMOS image sensor unit independently controls the digital signal processing chip synchronous working at respective rear.
Above-describedly be only embodiments of the invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (7)
1. a super large resolution cmos image sensor, described cmos image sensor is N channel cmos image sensor, it is stitched together by N number of independent CMOS image sensor unit and on a single die integrated, described N number of independently CMOS image sensor unit is mutual mirror image, each has respective phase-locked loop and independently Back end data coffret, and N number of independently phase-locked loop is identical; Wherein, N be more than or equal to 2 positive integer;
Described in each, the input/output interface of phase-locked loop comprises: standard time clock input port, one for residing for the inner internal clock signal output port of CMOS image sensor unit, and multiple output frequency interface;
It is characterized in that:
One in described N number of CMOS image sensor unit is configured to main CMOS image sensor unit: described main phase-locked loop standard time clock input port receives the standard time clock that the crystal oscillator outside described chip provides, the internal clock signal output port of described main phase-locked loop provides its internal clock signal, and described main phase-lock-ring output frequency interface exports described standard time clock;
Residue N-1 in described N number of CMOS image sensor unit is configured to from CMOS image sensor unit: the described standard time clock input port sky from phase-locked loop connects, the described internal clock signal output port from phase-locked loop provides respective internal clock signal, described from phase-lock-ring output frequency interface one of them for receiving described standard time clock; And remainingly described be used for the output of described standard time clock from phase-lock-ring output frequency interface or sky connects;
Wherein, the described described standard time clock from phase-lock-ring output frequency interface comes from the standard time clock or other standard time clock exported from phase-lock-ring output frequency interface that described main phase-lock-ring output frequency interface exports, with the digital signal processing chip synchronous working at the independent internal clocks signal controlling realizing described N number of CMOS image sensor unit rear separately.
2. super large resolution cmos image sensor according to claim 1, is characterized in that, described N is even number.
3. according to claim 2 super large resolution cmos image sensor, it is characterized in that, described N is 4.
4. according to claim 3 super large resolution cmos image sensor, it is characterized in that, described four CMOS image sensor unit are mutual mirror images; Wherein, one in described four CMOS image sensor unit is configured to main CMOS image sensor unit: described main phase-locked loop standard time clock input port receives the standard time clock that the crystal oscillator outside described chip provides, the internal clock signal output port of described main phase-locked loop provides its internal clock signal, and described main phase-lock-ring output frequency interface exports described standard time clock;
Residue three in described four CMOS image sensor unit is configured to from CMOS image sensor unit: the described standard time clock input port sky from phase-locked loop connects, described internal clock signal second output port from phase-locked loop provides respective internal clock signal, described main CMOS image sensor unit at least has two input and output frequency interface, input and output frequency interface outputting standard clock to described in transverse side from phase-locked loop; Another input and output frequency interface outputting standard clock described is given vertical sideways described from phase-locked loop; And input from phase-lock-ring output frequency interface from above-mentioned two output frequency interface standard time clocks of any one from phase-locked loop described in remaining one.
5. according to claim 1 super large resolution cmos image sensor, it is characterized in that, the standard clock signal that described crystal oscillator provides is 16MHz, and the internal clock signal that each phase-locked loop produces is 256MHz.
6. adopt a clock synchronizing method for claim 1-5 super large resolution cmos image sensor described in any one, it is characterized in that: comprise clock synchronous step S1 and data syn-chronization transmission step S2;
Described clock synchronous step S1 comprises:
Step S11: the standard time clock from the outer crystal oscillator of described chip is supplied to described main phase-locked loop standard time clock input port, and described main phase-lock-ring output frequency interface exports described standard time clock;
From the described standard time clock of phase-lock-ring output frequency interface described in step S12: at least 1;
Step S13: the standard time clock that residue is described to be exported from phase-lock-ring output frequency interface main described in phase-lock-ring output frequency interface or described in other from the standard time clock that phase-lock-ring output frequency interface exports;
Described data syn-chronization transmission step S2 comprises:
Step S21: described main phase-locked loop and described from phase-locked loop internal clock signal output port under the control of described standard time clock, produce respective synchronous internal clock signal;
Step S22: the internal clock signal of described multiple CMOS image sensor unit independently controls the digital signal processing chip synchronous working at respective rear.
7. according to claim 1 super large resolution cmos image sensor, it is characterized in that, the standard clock signal that described crystal oscillator provides is 16MHz, and the internal clock signal that each phase-locked loop produces is 256MHz.
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