CN111147690A - Frame synchronization device and method for multi-image sensor camera - Google Patents
Frame synchronization device and method for multi-image sensor camera Download PDFInfo
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- CN111147690A CN111147690A CN201911349100.4A CN201911349100A CN111147690A CN 111147690 A CN111147690 A CN 111147690A CN 201911349100 A CN201911349100 A CN 201911349100A CN 111147690 A CN111147690 A CN 111147690A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
- H04N5/067—Arrangements or circuits at the transmitter end
- H04N5/073—Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
- H04N5/0733—Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations for distributing synchronisation pulses to different TV cameras
Abstract
The embodiment of the invention discloses a frame synchronization device and a frame synchronization method for a multi-image sensor camera, and relates to the field of image processing. The device comprises: the image sensor comprises a first image sensor and an Nth image sensor, the main control chip, the clock duplicator and the image sensor are electrically connected with each other, and a clock sending end of the first image sensor is connected to a clock receiving end of the clock duplicator. The embodiment of the invention can solve the problem of low quality of spliced images caused by frame asynchronism among multiple image sensors of the existing multi-image sensor camera.
Description
Technical Field
The embodiment of the invention relates to the field of image processing, in particular to a frame synchronization device and a frame synchronization method for a multi-image sensor camera.
Background
In recent years, with the continuous development of video capture technology and semiconductor technology, the technical demands for resolution and field of view in the field of image capture are increasing. However, due to the limitation of the conventional optical lens of the camera, the high resolution and the large field of view cannot be simultaneously considered, and under the background, the solution of the multi-image sensor camera begins to appear in the market. In addition, the light field imaging technology which has been emerging in recent years also adopts a multi-image sensor to collect multi-dimensional optical information in space.
The scheme of the multi-image sensor camera is generally realized by adopting a mode that a single main control chip is connected with a plurality of image sensors, and the main control chip is responsible for the functions of data acquisition, image splicing, image correction and the like of the plurality of image sensors. However, the commonly used monitoring main control chip has no image sensor function, the used image sensors are independent ICs, and the synchronization between the sensors cannot be realized in the aspects of image signal acquisition, processing and transmission. And the phenomenon of image asynchronization is aggravated by compressing and coding multi-path asynchronization signals generated by the multiple photosensitive chips after the multi-path asynchronization signals are spliced by the main control chip. For example, in video capture in a scene with a moving object with a long focal length, the adverse effect caused by the non-synchronism of the images is very obvious. If a binocular camera can reach a 90-degree horizontal field angle through splicing, when a driving automobile crosses a gap between two camera acquisition areas, namely when the driving automobile moves from one camera to the shooting area of the other camera, the phenomenon that an obvious picture is torn or even a shot object is damaged can occur, and when a user observes the driving automobile, the driving automobile can be instantly moved from one area to the other area. This phenomenon is exacerbated when the number of cameras is increased, such as with the same focal length and horizontal field angle, to four-eye, i.e., four independent image sensors.
The phenomenon of frame asynchronism between the image sensors caused by independent work of the acquisition end cannot be solved by adjusting the image sensors or internal hardware or programs of the existing main control chip.
Disclosure of Invention
The embodiment of the invention aims to provide a frame synchronization device and a frame synchronization method for a multi-image sensor camera, which are used for solving the problem of low quality of spliced images caused by frame asynchronism among multiple image sensors of the existing multi-image sensor camera.
In order to achieve the above object, the embodiments of the present invention mainly provide the following technical solutions:
in a first aspect, embodiments of the present invention provide a frame synchronization apparatus for a multi-image sensor camera,
the device comprises: the image sensor comprises a first image sensor and an Nth image sensor, the main control chip, the clock duplicator and the image sensor are electrically connected with each other, and a clock sending end of the first image sensor is connected to a clock receiving end of the clock duplicator.
Furthermore, the main control chip is connected to the clock duplicator and the image sensors through the control circuit, a clock sending end of the clock duplicator is connected to the main control chip and a clock receiving end of each Nth image sensor, and a data sending end of each image sensor is connected to a data receiving end of the main control chip.
Further, the first image sensor and the Nth image sensor of the image sensor are the same type of sensor, and the configured working modes of the image sensor comprise a master mode for actively generating an image clock and a slave mode for accepting an externally input image clock.
Further, the clock replicator is based on a field programmable gate array FPGA.
In a second aspect, embodiments of the present invention provide a frame synchronization method for a multi-image sensor camera,
the method is applied to a frame synchronization device of a multi-image sensor camera, and comprises the following steps: initializing a main control chip, and starting an image sensor and a clock duplicator; the clock duplicator receives an image clock of the first image sensor after internal initialization; synchronizing the output of the clock replicator with the input image clock until the clock replicator has a synchronized and stable output; the main control chip controls each path of image sensor to generate image data according to respective image clock; the main control chip collects images input by each image sensor and marks time stamps of the images; and the main control chip splices the images into a frame of image according to the time stamp interval of each image.
Further, before the image sensor is started, the main control chip configures the working mode of the first image sensor as a master mode, and configures the working mode of the nth image sensor as a slave mode.
Further, the synchronizing the output of the clock copier and the input image clock specifically includes: the clock duplicator duplicates the acquired image clock and outputs the duplicated image clock to an FPGA internal bus; the clock duplicator samples the duplicated output image clock and the input image clock respectively and calculates the phase difference; when the phase difference is greater than 1% of the period of the input image clock, the input and output clocks are considered to be asynchronous, and when the phase difference is less than 1% of the period of the input image clock, the input and output clocks are considered to be synchronous.
Further, the method comprises: when the input clock and the output clock are asynchronous, the clock duplicator solves the phase difference obtained by calculation through a conjugate gradient model built in the FPGA to obtain output delay control parameters, and then carries out delay fine adjustment on the output clock signal of the clock duplicator according to the delay control parameters.
Further, the method comprises: and when the time stamp interval of the two images is less than 1 millisecond, the time stamps of the two images are considered to be close, and the main control chip splices the two images into a frame of image.
The technical scheme provided by the embodiment of the invention at least has the following advantages:
the embodiment of the invention uses the first image sensor as the only image clock reference and forms a plurality of stable and synchronous clock outputs through the clock duplicator for each image sensor and the main control chip to use, thereby ensuring the synchronism of the system image clock.
Drawings
Fig. 1 is a schematic structural diagram of a frame synchronization apparatus of a multi-image sensor camera according to an embodiment of the present invention.
Fig. 2 is a flowchart illustrating steps of a frame synchronization method for a multi-image sensor camera according to an embodiment of the present invention.
Fig. 3 is a partial flowchart of a frame synchronization apparatus for a multi-image sensor camera according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, interfaces, techniques, etc. in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
The embodiment of the invention provides a frame synchronization device of a multi-image sensor camera, referring to fig. 1, the device mainly comprises: a main control chip 01, a clock duplicator 02 and an image sensor. The master chip 01 is a chip having a plurality of image receiving interfaces and having internal splicing capability, such as Hi3519a, Hi3559a, H22, CV22, CV22AQ and the like; the clock duplicator 02 is a common FPGA, such as a Zync-7000, a Kintex series and the like; the image sensor is an image sensor with a digital image output interface and has a master-slave mode, such as IMX290, IMX334, IMX477 and the like. There are at least two image sensors, the image sensors include a first image sensor 03 and an nth image sensor, and the main control chip 01, the clock copier 02 and the image sensors are electrically connected to each other, where: the clock transmitting terminal 04 of the first image sensor 03 is connected to the clock receiving terminal 05 of the clock duplicator 02, so that the operation of the first image sensor 03 is set to the master mode to achieve clock synchronization of all the image sensors.
Specifically, the main control chip 01 is connected to the clock copier 02 and the image sensor through the control circuit, and is used for controlling the start and stop of the clock copier 02 and the image sensor, and the main control chip 01, the clock copier 02 and the image sensor have a common power supply in the application, so that the consistency of power supplies of all parts of the embodiment is ensured, and all functional units are ensured to supply power simultaneously.
The main control chip 01 has the capability of collecting at least two paths of image sensor data and splicing the collected image data, the main control chip 01 is provided with a clock receiving end 05 and a plurality of data receiving ends 07, the clock duplicator 02 is provided with a clock receiving end 05 and a plurality of clock transmitting ends 04, a first image sensor 03 and an Nth image sensor of the image sensors are sensors of the same model, the image sensors are provided with the clock transmitting ends 04, the clock receiving ends 05 and the data transmitting ends 06, and different ports can be connected according to requirements. Wherein the value of N is 2, 3, 4 … … N.
The clock transmitting terminal 04 of the clock duplicator 02 is connected to the main control chip 01 and the clock receiving terminal 05 of each nth image sensor, and the data transmitting terminal 06 of each image sensor is connected to the data receiving terminal 07 of the main control chip 01. The clock-transmitting terminal 04 of the first image sensor 03 is connected to the clock-receiving terminal 05 of the clock duplicator 02 so that the clock duplicator 02 duplicates the image clock of the first image sensor 03. And the operation modes in which the image sensor is configured include a master mode of actively generating an image clock and a slave mode of accepting an externally input image clock.
The clock duplicator 02 is based on a Field Programmable gate Array FPGA, a Field-Programmable gate Array, and the FPGA adopts a Logic unit Array LCA and a Logic Cell Array, so that the clock duplicator internally comprises a Configurable Logic Block CLB, an Input Output Block Input and Output module IOB and an internal connection Interconnect. The FPGA utilizes a small lookup table 16 multiplied by 1RAM to realize the combinational logic, each lookup table is connected to the input end of a D flip-flop, the flip-flop drives other logic circuits or drives I/O, so that basic logic unit modules which can realize the combinational logic function and the sequential logic function are formed, and the modules are mutually connected or connected to the I/O module by utilizing metal connecting wires. The logic of the FPGA is implemented by loading programming data into the internal static memory cells, the values stored in the memory cells determine the logic function of the logic cells and the way of the connections between the modules or between the modules and the I/O and finally the functions that can be implemented by the FPGA, which allows an unlimited number of programming.
In the embodiment, the clock duplicator 02 based on the FPGA realizes strict synchronization of a plurality of input and output image clocks through steps of internal sampling, duplication, phase synchronization, locking, output and the like of the input image clock, so as to realize frame synchronization of images.
Corresponding to the above embodiments, the present embodiment provides a frame synchronization method for a multiple image sensor camera, and referring to fig. 2, the method mainly includes: starting a power supply, initializing a main control chip 01, and starting an image sensor and a clock duplicator 02 by the main control chip 01; before the image sensor is started, the main control chip 01 configures the working mode of the first image sensor 03 as a master mode, and configures the working mode of the nth image sensor as a slave mode.
Further, after the clock duplicator 02 performs internal initialization, the clock duplicator 02 receives the image clock of the first image sensor 03, synchronizes the output with the input image clock until the clock duplicator 02 has a synchronized and stable output, and locks the clock phase at this time; the main control chip 01 controls each path of image sensor to collect image data according to the image clock output by the clock duplicator 02 and sends the image data to the main control chip 01; the main control chip 01 collects images input by each image sensor and marks time stamps of the images; the main control chip 01 splices the images into a frame of image according to the time stamp interval of each image.
Referring to fig. 3, synchronizing the output of the clock copier 02 with the input image clock specifically includes:
the clock duplicator 02 duplicates the acquired image clock and outputs the duplicated image clock to an FPGA internal bus; the clock copier 02 samples the image clock outputted from the copier and the inputted image clock, respectively, and calculates a phase difference
Wherein, tATime at initial phase of input signal, tBTime to initial phase of output signal, tCΔ T is the time difference between the input and output signals, T is the signal period, for the time when the input signal reaches the initial phase again.
When the phase difference is greater than 1% of the period of the input image clock, the input and output clocks are considered to be asynchronous, and when the phase difference is less than 1% of the period of the input image clock, the input and output clocks are considered to be synchronous.
When the input clock and the output clock are asynchronous, the clock duplicator 02 solves the calculated phase difference through a conjugate gradient model built in the FPGA to obtain an output delay control parameter, and the calculation steps of the delay control parameter x (k) comprise:
calculate residual r (k):
r(k)＝Ax(k-1)-b
calculating a direction vector d (k) from the residual:
calculating step length a (k) according to the direction vector:
updating the solution according to the step length:
x(k)＝x(k-1)+a(k)d(k)
in the above formula, k is the number of iterations, a is a symmetric positive definite matrix, b is a constant, r (k) is the residual error of k iterations, d (k) is the direction vector of k iterations, a (k) is the step size of k iterations, and x (k) is the solution of k iterations, i.e., the delay control parameter.
And then, performing delay fine adjustment on the output clock signal of the clock duplicator 02 according to the delay control parameter, wherein the delay method is to obtain a delay parameter set by FGPA according to the following formula, wherein B is a unit conversion constant:
dealy＝Bx
in addition, preferably, when the time stamp interval of the two images is less than 1 millisecond, the time stamps of the two images are considered to be close to each other, and the main control chip 01 splices the two images into one frame of image.
In the embodiment of the invention, the first image sensor 03 is used as a unique image clock reference, and a plurality of stable and synchronous clock outputs are formed by the clock duplicator 02 to be used by each image sensor and the main control chip 01, so that the synchronism of the system image clock is ensured.
Those skilled in the art will appreciate that the functionality described in the present invention may be implemented in a combination of hardware and software in one or more of the examples described above. When software is applied, the corresponding functionality may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present invention should be included in the scope of the present invention.
Claims (9)
1. A frame synchronization apparatus of a multi-image sensor camera, the apparatus comprising: the image sensor comprises a first image sensor and an Nth image sensor, the main control chip, the clock duplicator and the image sensor are electrically connected with each other, and a clock sending end of the first image sensor is connected to a clock receiving end of the clock duplicator.
2. The frame synchronizing device of a multi-image sensor camera as claimed in claim 1, wherein the main control chip is connected to the clock duplicator and the image sensors through the control circuit, a clock transmitting terminal of the clock duplicator is connected to the main control chip and a clock receiving terminal of each nth image sensor, and a data transmitting terminal of each image sensor is connected to a data receiving terminal of the main control chip.
3. The frame synchronization apparatus of a multi-image sensor camera as claimed in claim 1, wherein the first image sensor and the nth image sensor of the image sensor are the same type of sensor, and the operation modes in which the image sensor is configured include a master mode for actively generating an image clock and a slave mode for receiving an externally input image clock.
4. The frame synchronizing device of a multi-image sensor camera according to claim 1, wherein the clock replicator is based on a Field Programmable Gate Array (FPGA).
5. A frame synchronization method of a multi-image sensor camera, the method is applied to a frame synchronization device of the multi-image sensor camera, and the method comprises the following steps:
initializing a main control chip, and starting an image sensor and a clock duplicator;
the clock duplicator receives an image clock of the first image sensor after internal initialization;
synchronizing the output of the clock replicator with the input image clock until the clock replicator has a synchronized and stable output;
the main control chip controls each path of image sensor to generate image data according to respective image clock;
the main control chip collects images input by each image sensor and marks time stamps of the images;
and the main control chip splices the images into a frame of image according to the time stamp interval of each image.
6. The method as claimed in claim 5, wherein the master chip configures an operation mode of a first image sensor as a master mode and an operation mode of an nth image sensor as a slave mode before the image sensors are activated.
7. The method of claim 5, wherein the synchronizing the output of the clock replicator and the input image clock comprises:
the clock duplicator duplicates the acquired image clock and outputs the duplicated image clock to an FPGA internal bus;
the clock duplicator samples the duplicated output image clock and the input image clock respectively and calculates the phase difference;
when the phase difference is greater than 1% of the period of the input image clock, the input and output clocks are considered to be asynchronous, and when the phase difference is less than 1% of the period of the input image clock, the input and output clocks are considered to be synchronous.
8. The method of frame synchronization for a multiple image sensor camera of claim 7, the method comprising: when the input clock and the output clock are asynchronous, the clock duplicator solves the phase difference obtained by calculation through a conjugate gradient model built in the FPGA to obtain output delay control parameters, and then carries out delay fine adjustment on the output clock signal of the clock duplicator according to the delay control parameters.
9. The method of frame synchronization for a multiple image sensor camera of claim 8, the method comprising: and when the time stamp interval of the two images is less than 1 millisecond, the time stamps of the two images are considered to be close, and the main control chip splices the two images into a frame of image.
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