CN112689991B - Initialization synchronization device, initialization synchronization method, and camera - Google Patents
Initialization synchronization device, initialization synchronization method, and camera Download PDFInfo
- Publication number
- CN112689991B CN112689991B CN201880097091.1A CN201880097091A CN112689991B CN 112689991 B CN112689991 B CN 112689991B CN 201880097091 A CN201880097091 A CN 201880097091A CN 112689991 B CN112689991 B CN 112689991B
- Authority
- CN
- China
- Prior art keywords
- processing circuit
- signal
- controller
- sensor
- initialization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Studio Devices (AREA)
Abstract
The embodiment of the application provides an initialization synchronization device, an initialization synchronization method and a camera, and relates to the technical field of video processing. The initialization synchronization apparatus includes: the device comprises a CPU, one or more controllers and a signal processing circuit, wherein each controller of the one or more controllers is coupled to the CPU and the signal processing circuit, and the signal processing circuit is connected with one or more sensors outside the initialization synchronization device. The CPU may control the signal processing circuit to be in a first state for instructing the first controller to connect with each of the one or more sensors through the signal processing circuit. The first controller may simultaneously transmit the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit, such that each of the sensors can simultaneously receive the initialization signal and complete the initialization configuration at the same time.
Description
Technical Field
The present disclosure relates to the field of video processing technologies, and in particular, to an initialization synchronization apparatus, an initialization synchronization method, and a video camera.
Background
The video stitching technology is a technology for stitching video images acquired by a plurality of cameras to form a panoramic image, and is generally applied to panoramic cameras.
A conventional panoramic camera includes: a plurality of cameras and SOC (System On Chip), each camera all includes image sensor, and each image sensor all is connected with SOC. Before each camera normally acquires an image, the SOC sends an initialization configuration instruction to an image sensor of each camera to complete initialization configuration of the image sensor. After the initialization configuration of each image sensor is completed, each image sensor transmits the acquired image to the SOC, and the SOC can splice the images acquired by different image sensors to form a panoramic image.
However, at present, the initialization configuration of the plurality of image sensors by the SOC is not synchronous, so that images acquired by the image sensors are not synchronous, the SOC splices the asynchronous images, and the obtained panoramic image has a poor display effect.
Disclosure of Invention
The application provides an initialization synchronization device, an initialization synchronization method and a camera, which can synchronously initialize a plurality of sensors so as to synchronously output images of all image sensors.
In a first aspect, an initialization synchronization apparatus is provided, including: a Central Processing Unit (CPU), one or more controllers, and a signal processing circuit, wherein each of the one or more controllers is coupled to the CPU and the signal processing circuit, the signal processing circuit connected to one or more sensors external to the initialization synchronization device; the CPU is used for controlling the signal processing circuit to be in a first state, the first state is used for indicating a first controller to be connected with each sensor in the one or more sensors through the signal processing circuit, and the first controller is one controller in the one or more controllers; the first controller is configured to send the initialization signal generated by the CPU to each of the one or more sensors simultaneously through the signal processing circuit when the signal processing circuit is in the first state.
In the application, when the CPU controls the signal processing circuit to be in the first state, the first controller sends the initialization signal generated by the CPU to each sensor of the one or more sensors through the signal processing circuit, so that each sensor can receive the initialization signal at the same time, and the initialization configuration is completed at the same time, thereby avoiding the phenomenon that images acquired by the sensors are asynchronous. If the initialization synchronization device is integrated on the SOC, when the SOC splices images acquired by the sensors to obtain a panoramic image, the initialization signal can be simultaneously sent to the image sensors through the signal processing circuit, so that the images acquired by the sensors are synchronously output, and the display effect of the spliced panoramic image is good.
Optionally, the CPU is further configured to control the signal processing circuit to be in a second state, where the second state is used to instruct each of the one or more controllers to be connected to a sensor through the signal processing circuit; each controller is configured to send the initialization signal or a parameter modification signal generated by the CPU to a sensor corresponding to each controller when the signal processing circuit is in the second state, where the parameter modification signal is used to adjust an initialization parameter recorded in the sensor, and the initialization parameter is a parameter carried in the initialization signal received by the sensor in the process of initializing each sensor.
In the present application, due to manufacturing errors between the respective sensors, when the same initialization parameters are configured for the respective sensors, there may be a difference in display quality (e.g., definition or color depth, etc.) of images acquired by the respective sensors. In order to enable each sensor to acquire an image with high display quality, after the initialization configuration of each sensor is completed by the initialization synchronization device, the CPU may control the signal processing circuit to be in the second state, and each controller may transmit the parameter modification signal generated by the CPU to the sensor corresponding to each controller. The parameter modification signal is used for adjusting the initialization parameters recorded in the register of the sensor, and each sensor can acquire images with high display quality. Because the initialization parameters in each sensor can be adjusted by the corresponding controller, the efficiency of adjusting the initialization parameters in each sensor by the initialization synchronization device after the initialization configuration is completed is high.
Optionally, the signal processing circuit includes: an output processing circuit and an input processing circuit; the first controller sending the CPU-generated signal to each of the one or more sensors through the output processing circuit while the signal processing circuit is in the first state; the first controller receives, via the input processing circuit, a response signal generated by each of the one or more sensors when the signal processing circuit is in the first state.
In the present application, the CPU in the initialization synchronization apparatus may transmit a signal to each of the one or more sensors through the output processing circuit, and the CPU may also receive a signal generated by each sensor through the input processing circuit and perform signal processing by the CPU.
Optionally, the output processing circuit includes: one or more digital selectors, an output of each of the one or more digital selectors connected to a corresponding sensor; when the signal processing circuit is in the first state, the input end of each digital selector in the one or more digital selectors is connected with the first controller; when the signal processing circuit is in the second state, the input end of each digital selector in the one or more digital selectors is connected with the corresponding controller.
Optionally, each digital selector includes a first input port, a second input port, a status selection port, and an output port, the first input port of each digital selector is connected to the first controller, the second input port of each digital selector is connected to the corresponding controller, the status selection port of each digital selector is connected to the CPU, and the output port of each digital selector is connected to the corresponding sensor; for each digital selector, when a state selection port of the digital selector receives an indication signal which is sent by the CPU and used for indicating that the signal processing circuit is in the first state, the first input port is in an on state, and the second input port is in an off state; for each digital selector, when the state selection port of the digital selector receives an indication signal sent by the CPU to indicate that the signal processing circuit is in the second state, the first input port is in an off state, and the second input port is in an on state.
Optionally, the input processing circuit includes: an AND gate logic circuit; when the signal processing circuit is in the first state, the AND gate logic circuit sends the received response signal generated by each sensor of the one or more sensors to the first controller after processing; each controller of the one or more controllers receives a response signal generated by a corresponding sensor when the signal processing circuit is in the second state.
Optionally, the input processing circuit further includes: a signal selector; each sensor in the one or more sensors is connected with an input end of the AND gate logic circuit, an output end of the AND gate logic circuit is connected with a first input end of the signal selector, an output end of the signal selector is connected with the first controller, and a first sensor corresponding to the first controller is also connected with a second input end of the signal selector; when the signal processing circuit is in the first state, the AND gate logic circuit sends the processed signal to the first controller through the signal selector; when the signal processing circuit is in the second state, the signal selector sends the response signal generated by the first sensor to the first controller.
Optionally, the initializing synchronization device further includes: a connection bus through which each of the one or more controllers is coupled to the CPU and the signal processing circuit, the connection bus being one or more of an integrated circuit I2C connection bus and a synchronous serial port SSP connection bus.
Assuming that the connection bus in this application is an I2C connection bus, then: the output processing circuit includes: a first output processing circuit for outputting a data signal, and a second output processing circuit for outputting a clock signal; the first input port of each digital selector in the first output processing circuit is connected with the data port of the first controller, the second input port of each digital selector in the first output processing circuit is connected with the data port of the corresponding controller, the first input port of each digital selector in the second output processing circuit is connected with the clock port of the first controller, and the second input port of each digital selector in the second output processing circuit is connected with the clock port of the corresponding controller.
The input processing circuit includes: a first input processing circuit for inputting a data signal, and a second input processing circuit for inputting a clock signal.
Optionally, the initialization synchronization apparatus further includes: the system register is respectively connected with the CPU and the signal processing circuit; the CPU is used for controlling the register value of the system register to be a first numerical value so as to enable the signal processing circuit to be in the first state; the CPU is also used for controlling the register value of the system register to be a second numerical value so as to enable the signal processing circuit to be in the second state, wherein the first numerical value is different from the second numerical value.
Optionally, the initialization synchronization apparatus further includes one or more input/output IO interfaces, and the signal processing circuit is connected to the one or more sensors one by one through the one or more IO interfaces; when the signal processing circuit is in the first state, the one or more IO interfaces are connected to the first controller; when the signal processing circuit is in the second state, each controller is connected with the corresponding sensor through an IO interface.
Optionally, the CPU is further configured to: before the initialization process is performed on each sensor, a reset instruction is sent to each sensor to clear the initialization parameters in each sensor.
Optionally, the CPU is further configured to: after initialization processing is carried out on each sensor, image information acquired by each sensor is received; judging whether the image information acquired by any two sensors is synchronous or not according to the synchronous signal in the image information; and performing compensation adjustment on the sensors with unsynchronized acquired image information. Therefore, the images acquired by the sensors 200 are synchronous, and the display effect of the panoramic image formed by subsequent splicing is improved.
In a second aspect, an initialization synchronization method is provided, which is applied to an initialization synchronization apparatus, and the initialization synchronization apparatus includes: a CPU, one or more controllers, and a signal processing circuit, wherein each of the one or more controllers is coupled to the CPU and the signal processing circuit, the signal processing circuit connected with one or more sensors external to the initialization synchronization device, the method comprising: the CPU controls the signal processing circuit to be in a first state, the first state is used for indicating that a first controller is connected with each sensor of the one or more sensors through the signal processing circuit, and the first controller is one controller of the one or more controllers; the first controller sends the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit.
Optionally, the method further includes: the CPU controls the signal processing circuit to be in a second state, and the second state is used for indicating that each controller of the one or more controllers is connected with a sensor through the signal processing circuit; each controller sends the initialization signal or the parameter modification signal generated by the CPU to the sensor corresponding to the controller, the parameter modification signal is used to adjust the initialization parameter recorded in the sensor, and the initialization parameter is a parameter carried in the initialization signal received by the sensor in the process of initializing each sensor.
Optionally, the signal processing circuit includes: an output processing circuit and an input processing circuit; after the CPU controls the signal processing circuit to be in the first state, the method further includes: the first controller sending the CPU-generated signal to each of the one or more sensors through the output processing circuitry; the first controller receives, via the input processing circuit, a response signal generated by each of the one or more sensors.
Optionally, the output processing circuit includes: one or more digital selectors, an output of each of the one or more digital selectors connected to a corresponding sensor; the first controller sends the CPU-generated signal to each of the one or more sensors through the output processing circuitry, including: each digital selector in the one or more digital selectors controls a respective input to be connected with the first controller, so that the first controller sends signals generated by the CPU to one or more sensors through the one or more digital selectors; after the CPU controls the signal processing circuit to be in the second state, the method further includes: each of the one or more digital selectors controls a respective input to be connected to a corresponding controller.
Optionally, the input processing circuit includes: an AND gate logic circuit; the first controller receives, via the input processing circuitry, a response signal generated by each of the one or more sensors, including: the first controller receives a signal obtained by processing a received response signal generated by each sensor of the one or more sensors through the AND gate logic circuit; after the CPU controls the signal processing circuit to be in the second state, the method further includes: each controller of the one or more controllers receives a response signal generated by a corresponding sensor.
Optionally, the input processing circuit further includes: the signal selector is connected with the input end of the AND gate logic circuit, the output end of the AND gate logic circuit is connected with the first input end of the signal selector, the output end of the signal selector is connected with the first controller, and the first sensor corresponding to the first controller is also connected with the second input end of the signal selector; the first controller receives a signal processed by the and logic circuit according to the received response signal generated by each sensor of the one or more sensors, and includes: the first controller receives a signal which is sent by the AND gate logic circuit through the signal selector after the processed signal is processed; after the CPU controls the signal processing circuit to be in the second state, the method further includes: the signal selector sends the response signal generated by the first sensor to the first controller.
Optionally, the initialization synchronization apparatus further includes: the system register, this system register is connected with this CPU and this signal processing circuit respectively, and this CPU control this signal processing circuit is in first state, includes: the CPU controls the register value of the system register to be a first numerical value so as to enable the signal processing circuit to be in a first state; the CPU controls the signal processing circuit to be in a second state, including: the CPU controls the register value of the system register to be a second value so as to enable the signal processing circuit to be in a second state, wherein the first value and the second value are different.
Optionally, the initialization synchronization apparatus further includes one or more input/output IO interfaces, and the signal processing circuit is connected to the one or more sensors one by one through the one or more IO interfaces; after the CPU controls the signal processing circuit to be in the first state, the method further includes: the signal processing circuit controls the one or more IO interfaces to be connected to the first controller; after the CPU controls the signal processing circuit to be in the second state, the method further includes: the signal processing circuit controls each controller to be connected with the corresponding sensor through an IO interface.
Optionally, the method further includes: before performing the initialization process for each sensor, the CPU sends a reset instruction to each sensor to clear the initialization parameters in each sensor.
Optionally, the method further includes: after performing initialization processing on each sensor, the CPU receives image information acquired by each sensor; the CPU judges whether the image information acquired by any two sensors is synchronous or not according to the synchronous signal in the image information; the CPU performs compensation adjustment on the sensors whose acquired image information is not synchronized.
It should be noted that, in the principle of the initialization synchronization method in the second aspect, reference may be made to a corresponding part in the initialization synchronization apparatus in the first aspect, and details of this application are not repeated herein.
In a third aspect, there is provided a camera comprising: a plurality of cameras and a system on chip SOC, the SOC comprising: the initialization synchronizer of any of the first aspect, wherein each camera comprises a sensor, each sensor being connected to the initialization synchronizer.
Drawings
Fig. 1 is a block diagram of a panoramic camera provided in the related art;
fig. 2 is a block diagram of another panoramic camera provided in the related art;
fig. 3 is a block diagram of an initialization synchronization apparatus according to an embodiment of the present application;
fig. 4 is a block diagram of another initialization synchronization apparatus provided in an embodiment of the present application;
fig. 5 is a schematic structural diagram of an output processing circuit according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of the transmission of signals in the output processing circuit shown in FIG. 5;
fig. 7 is a schematic structural diagram of an input processing circuit according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of transmission of signals in the output processing circuit shown in fig. 7.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. The drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the concepts of the application by those skilled in the art with reference to specific embodiments.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a block diagram of a panoramic camera provided in the related art, the panoramic camera including: SOC 01, and a plurality of cameras (not shown in fig. 1), each of which may include an image sensor 02. An I2C (Integrated Circuit) bus 011 and a plurality of INCK (Input Clock) circuits 012 are disposed inside the SOC 01, each image sensor 02 is connected to the I2C bus 011, and the plurality of INCK circuits 012 are connected to the plurality of image sensors 02 in a one-to-one correspondence.
When the panoramic camera acquires a panoramic image, the SOC 01 needs to send an initialization configuration instruction to all the image sensors 02 through the I2C bus 011 and the plurality of INCK circuits 012, each image sensor 02 performs initialization configuration after receiving the initialization configuration instruction, and after the initialization configuration of the image sensors 02 is completed, an image can be acquired and sent to the SOC 01, so that the SOC 01 splices images acquired by different image sensors 02 to obtain the panoramic image.
However, when all the image sensors 02 are connected through one I2C bus 011, the SOC 01 needs to control the image sensors 02 one by one for initial configuration, that is, after a certain image sensor is initially configured, the SOC 01 can control the next image sensor for initial configuration. In general, after the image sensors 02 are initialized and configured, the image sensors 02 immediately send the acquired images to the SOC 01, and the SOC 01 cannot control the plurality of image sensors 01 to complete the initialization and configuration at the same time, so that the images acquired by the image sensors 02 are not synchronized, the SOC 01 splices the images that are not synchronized, and the obtained panoramic image has poor display effect.
Referring to fig. 2, fig. 2 is a block diagram of another panoramic camera provided in the related art, in which a plurality of I2C buses 011 and a plurality of INCK circuits 012 are disposed in an SOC 01, the plurality of I2C buses 011 and the plurality of image sensors 02 are connected in a one-to-one correspondence, and the plurality of INCK circuits 012 and the plurality of image sensors 02 are connected in a one-to-one correspondence. At this time, the SOC 01 does not need to control the plurality of image sensors 02 one by one for initialization configuration, although the plurality of image sensors 02 may perform initialization configuration at the same time, due to the reason of sequential execution of software, the SOC 01 needs to send an initialization image command to each image sensor 02 one by one through the plurality of I2C buses 011, the time of initialization completion of each image sensor 02 is still delayed in sequence, the SOC 01 still cannot control the plurality of image sensors 01 to complete initialization configuration at the same time, images acquired by the image sensors 02 are not synchronized, the SOC 01 splices the images that are not synchronized, and the display effect of the obtained panoramic image is poor.
Referring to fig. 3, fig. 3 is a block diagram of an initialization synchronization apparatus provided in an embodiment of the present application, where the initialization synchronization apparatus 100 may include:
a Central Processing Unit (CPU) 10, one or more controllers 20, and a signal Processing circuit 30, wherein each controller 20 of the one or more controllers 20 is coupled to the CPU10 and the signal Processing circuit 30, and the signal Processing circuit 30 is connected to one or more sensors 200 outside the initialization synchronization apparatus. For example, the sensor 200 in the embodiment of the present application may be an image sensor.
The CPU10 is configured to control the signal processing circuit 30 to be in a first state, the first state being used to instruct the first controller 20a to be connected to each of the one or more sensors 200 through the signal processing circuit 30, the first controller 20a being one of the one or more controllers 20.
The first controller 20a is configured to simultaneously transmit the initialization signal generated by the CPU10 to each of the one or more sensors 200 through the signal processing circuit 30 when the signal processing circuit 30 is in the first state.
Illustratively, the signal processing circuit 30 has a plurality of input/output interfaces, wherein the plurality of input/output interfaces are connected to the sensors one by one, when the signal processing circuit 30 is in the first state, the plurality of input/output interfaces of the signal processing circuit 30 are all connected to the first controller 20a, when the CPU10 generates an initialization signal, the initialization signal is simultaneously sent to each sensor 200 through the plurality of input/output interfaces by the first controller 20a, each sensor 200 can write initialization parameters (e.g., resolution, refresh rate, exposure time, gain, etc. of an image) carried in the initialization signal into registers in the sensor 200 after receiving the initialization signal sent by the first controller 20a, and after the initialization parameter writing is completed, the sensor 200 can complete initialization configuration. Since the first controller 20a sends the initialization signal to each of the one or more sensors 200 through the signal processing circuit 30, each sensor 200 can receive the initialization signal at the same time and complete the initialization configuration at the same time, thereby avoiding the phenomenon that the images acquired by the sensors 200 are not synchronized. If the initialization synchronization device 100 is integrated on the SOC, when the SOC splices the images acquired by the sensors 200 to obtain a panoramic image, the initialization signal may be simultaneously sent to the image sensors 200 through the signal processing circuit 30, so that the images acquired by the sensors 200 are synchronously output, and the display effect of the spliced panoramic image is better.
Further, the CPU10 is further configured to control the signal processing circuit 30 to be in a second state, where the second state is used to instruct each of the one or more controllers 20 to be connected to one of the sensors 200 through the signal processing circuit 30. Each controller 20 is configured to send the initialization signal generated by the CPU10 to the sensor 200 corresponding to each controller 20 when the signal processing circuit 30 is in the second state.
Illustratively, when the signal processing circuit 30 is in the second state, each sensor 200 is connected to the CPU10 through a respective controller 20, and the CPU10 can control each sensor 200 independently.
In the embodiment of the present application, after the initialization synchronization apparatus 100 completes the initialization configuration of each sensor 200, each sensor 200 may acquire an image, but due to manufacturing errors among the sensors 200, when the same initialization parameters are configured for each sensor 200, there may be differences in display quality (for example, definition, color depth, and the like) of the images acquired by each sensor 200. In order to enable each sensor 200 to acquire an image with high display quality, after the initialization configuration of each sensor 200 is completed by the initialization synchronization device 100, the CPU10 controls the signal processing circuit 30 to be in the second state, and each controller 20 may transmit the parameter modification signal generated by the CPU10 to the sensor 200 corresponding to each controller 20. The parameter modification signal is used to adjust the initialization parameter recorded in the register of the sensor 200, so as to ensure that each sensor 200 can acquire an image with high display quality. Since the initialization parameter in each sensor 200 can be adjusted by the corresponding controller 20, the efficiency of adjusting the initialization parameter in each sensor 200 by the initialization synchronization device 100 after the initialization configuration is completed is high.
In an alternative implementation manner, as shown in fig. 4, fig. 4 is a block diagram of another initialization synchronization apparatus provided in an embodiment of the present application. The initialization synchronization apparatus 100 may further include: and a system register 40, wherein the system register 40 is connected to the CPU10 and the signal processing circuit 30, respectively. The CPU10 is configured to control the register value of the system register 40 to be a first value, so that the signal processing circuit 30 is in a first state; the CPU10 is further configured to control the register value of the system register 40 to be a second value, so that the signal processing circuit 30 is in a second state. Wherein the first value is different from the second value. For example, the first value may be 1, and the second value may be 0. It should be noted that, in fig. 4, the CPU10 controls the register value of the system register 40 to control the signal processing circuit 30 to be in the first state or the second state, in another alternative implementation, the CPU10 may directly control the signal processing circuit 30 to be in the first state or the second state, which is not specifically limited in this embodiment of the present application.
Optionally, the initializing synchronization apparatus 100 may further include: one or more Input/Output (IO) interfaces, through which the signal processing circuit 30 is connected to the one or more sensors 200 one by one. It should be noted that fig. 4 is a schematic diagram illustrating an IO general interface 50, and the IO general interface 50 includes one or more IO interfaces connected to one or more sensors 200. In the present embodiment, when the signal processing circuit 30 is in the first state, the one or more IO interfaces are each connected to the first controller 20a such that the first controller 20a is connected with each of the one or more sensors 200; when the signal processing circuit 30 is in the second state, each controller 20 is connected to the corresponding sensor 200 through one IO interface, so that each controller 20 of the one or more controllers 20 is connected to the corresponding sensor 200.
In the embodiment of the present application, the initialization synchronization apparatus 100 further includes: a bus 60 is connected. Each controller 20 of the one or more controllers 20 is coupled to the CPU10 and the signal processing circuit 30 via the connection bus 60, and the signal processing circuit 30 and the IO bus interface 50 may also be connected via the connection bus 60. Optionally, the connection bus 60 may be one or more of an Inter-Integrated Circuit (I2C) connection bus and a Synchronous Serial Port (SSP) connection bus. It should be noted that the I2C connection bus may include a data trace for transmitting a data signal and a clock trace for transmitting a clock signal; the SSP connection bus may include three types of signal traces: an input/output data trace (also called a bidirectional data trace) for transmitting a data signal, a clock trace for transmitting a clock signal, and a chip select trace for transmitting a chip select signal; the SSP connection bus may also include four types of signal traces: the chip select line comprises an input data line for transmitting data signals, an output data line for transmitting data signals, a clock line for transmitting clock signals, and a chip select line for transmitting chip select signals. It should be understood that the embodiment of the present application divides the initialization synchronization apparatus from the functional point of view, and there may be another dividing manner in practical implementation, for example, a plurality of modules may be combined or may be integrated into another system. The coupling of the various modules to each other may be through interfaces that are typically electrical communication interfaces, but mechanical or other forms of interfaces are not excluded. Thus, modules described as separate components may or may not be physically separate, may be located in one place, or may be distributed in different locations on the same or different devices. In various embodiments of the present application, coupled refers to being interconnected in a particular way, including being directly connected or being indirectly connected through other devices.
Optionally, as shown in fig. 4, the signal processing circuit 30 in the initialization synchronization apparatus 100 includes: an output processing circuit 31 and an input processing circuit 32.
When the signal processing circuit 30 is in the first state, the first controller 20a sends a signal generated by the CPU10 to each of the one or more sensors 200 through the output processing circuit 31, for example, the signal generated by the CPU10 may be an initialization signal; the first controller 20a receives, via the input processing circuit 32, a response signal that each sensor 200 of the one or more sensors 200 will generate individually, e.g., the response signal of each sensor 200 is an initialization response signal that the sensor 200 generates upon receiving the initialization signal.
When the signal processing circuit 30 is in the second state, each controller 20 of the one or more controllers 20 sends a signal generated by the CPU10 to the corresponding sensor 200 through the output processing circuit 31, for example, the signal generated by the CPU10 may be a parameter modification signal; each controller 20 of the one or more controllers 20 receives a response signal of the corresponding sensor 200 via the input processing circuit 32, e.g., the response signal of each sensor 20 is a parameter modification response signal generated by the sensor 200 after receiving the parameter modification signal.
In the embodiment of the present application, after receiving the response signal sent by the sensor 200, each controller 20 sends the response signal to the CPU10, and the CPU10 performs signal processing.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an output processing circuit 31 according to an embodiment of the present disclosure. The output processing circuit includes: one or more digital selectors 311. In the present embodiment, at least one of the one or more digital selectors 311 may correspond to a sensor and a controller. The output of the one or more digital selectors 311 is connected to a corresponding sensor.
Illustratively, as shown in fig. 6, fig. 6 is a schematic diagram of transmission of signals in the output processing circuit 31 shown in fig. 5. When the signal processing circuit is in the first state, the signal transmission direction in the output processing circuit 31 is the direction of the solid line in fig. 6, and the input port of each digital selector 311 in the one or more digital selectors 311 is connected to the first controller, so that the first controller can simultaneously transmit the signal generated by the CPU to each sensor in the one or more sensors; when the signal processing circuit is in the second state, the signal transmission direction in the output processing circuit 31 is the direction of the dotted line in fig. 6, and the input terminal of each digital selector 311 in the one or more digital selectors 311 is connected to the corresponding controller, so that each controller in the one or more controllers can send the signal generated by the CPU to the corresponding sensor.
Optionally, each digital selector 311 includes: a first input port T1, a second input port T2, a status selection port S and an output port Z. The first input port T1 of each digital selector 311 is connected to the first controller; the second input port T2 of each digital selector 311 is connected to a corresponding controller; the status selection port S of each digital selector 311 is connected to the CPU, and in an optional case, the status selection port S of each digital selector 311 is connected to the CPU through a system control register, that is, the status selection port S is connected to the system control register, and the system control register is connected to the CPU; the output port Z of each digital selector 311 is connected to a corresponding sensor.
For each digital selector 311, when the state selection port S of the digital selector 311 receives an indication signal sent by the CPU to indicate that the signal processing circuit is in the first state, the first input port T1 of the digital selector 311 is in an on state, and the second input port T2 of the digital selector is in an off state, so that each of the one or more sensors is connected to the first controller through the output processing circuit 31.
For each digital selector 311, when the state selection port S of the digital selector 311 receives an indication signal sent by the CPU to indicate that the signal processing circuit is in the second state, the first input port T1 of the digital selector 311 is in an off state, and the second input port T2 of the digital selector is in an on state, so that each of the one or more sensors is connected to the corresponding controller through the output processing circuit 31.
Assuming that the connection bus in the initialization synchronization apparatus in the embodiment of the present application is an I2C connection bus, the output processing circuit 31 may include: a first output processing circuit 31a for outputting a data signal, and a second output processing circuit 31b for outputting a clock signal. The data trace in the I2C connection bus is connected to the first output processing circuit 31a, and the clock trace in the I2C connection bus is connected to the second output processing circuit 31b. The first output processing circuit 31a and the second output processing circuit 31b may each include: one or more signal selectors 311. A first input port T1 of each digital selector 311 in the first output processing circuit 31a is connected to a data port of a first controller, and a second input port T2 of each digital selector 311 in the first output processing circuit 31a is connected to a data port of a corresponding controller; the first input port T1 of each digital selector 311 in the second output processing circuit 31b is connected to the clock port of the first controller, and the second input port T2 of each digital selector 311 in the second output processing circuit 31b is connected to the clock port of the corresponding controller.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an input processing circuit 32 according to an embodiment of the present disclosure. The input processing circuit 32 may include: and gate logic 321. Illustratively, as shown in fig. 8, fig. 8 is a schematic diagram of transmission of signals in the output processing circuit 31 shown in fig. 7. When the signal processing circuit is in the first state, the signal transmission direction in the input processing circuit 32 is the direction of the solid line in fig. 8, and each sensor of the one or more sensors sends the response signal generated by each sensor to the first controller after being processed by the and logic circuit 321; when the signal processing circuit is in the second state, the direction of signal transmission into the processing circuit 32 is in the direction of the dashed line in fig. 8, and each of the one or more controllers receives a response signal generated by the corresponding sensor.
Optionally, the input processing circuit 32 may further include: a digital selector 322. In the embodiment of the present application, each of the one or more sensors is connected to an input of the and logic circuit 321; the output terminal of the and logic circuit 321 is connected to the first input terminal of the signal selector 322; the output terminal of the signal selector 322 is connected to the first controller; the first sensor corresponding to the first controller is also connected to a second input terminal of the signal selector 322. As shown in fig. 8, when the signal processing circuit is in the first state, the and gate logic circuit 322 sends the processed signal to the first controller through the signal selector 322; when the signal processing circuit is in the second state, the signal selector 322 transmits the response signal generated by the first sensor to the first controller.
Assuming that the connection bus in the initialization synchronization apparatus in the embodiment of the present application is an I2C connection bus, the input processing circuit 32 may include: a first input processing circuit 32a for inputting a data signal, and a second input processing circuit 32b for inputting a clock signal. The data trace in the I2C connection bus is connected to the first input processing circuit 32a, and the clock trace in the I2C connection bus is connected to the second input processing circuit 32b. The first input processing circuit 32a and the second input processing circuit 32b each include: and gate logic 321 and a signal selector 322, and the connection manner between the and gate logic 321 and the signal selector 322 is the same in both the first input processing circuit 32a and the second input processing circuit 32b. The following embodiment schematically illustrates a specific connection between the and gate logic 321 and the signal selector 322:
illustratively, the and gate logic 321 has an output port Z and one or more input ports (T0, T1, T2,. And.tn) corresponding to one or more sensors one by one, and the digital selector 322 has a first input port T1, a second input port T2, a status selection port S, and an output port Z. Each of the one or more sensors is connected to a corresponding input port in the and logic circuit 321; the output port Z of the and logic circuit 321 is connected to the first input port T1 of the digital selector; a first sensor of the one or more sensors is connected to the second input port T2 of the digital selector 322; the output port Z of the digital selector 322 is connected to the first controller; each sensor of the one or more sensors except the first sensor is directly connected with the corresponding controller; the status selection port S of the digital selector 322 is connected to the CPU, and for example, the status selection port S of the digital selector 322 is connected to a system control register, which needs to be connected to the CPU.
When the state selection port of the digital selector 322 receives an indication signal sent by the CPU to indicate that the signal processing circuit is in the first state, the first input port T1 of the digital selector 322 is in an on state, and the second input port T2 of the digital selector 322 is in an off state. At this time, the response signal generated by each of the one or more sensors is processed by the and logic circuit 321 and then transmitted to the first sensor. It should be noted that, when the signal processing circuit is in the first state, the CPU may control the connection between the CPU and each of the one or more controllers except the first controller to be interrupted, and at this time, although the response signal generated by each of the one or more sensors except the first sensor may be transmitted to the corresponding controller, the controllers may not transmit the received response signal to the CPU, and therefore, the CPU may only receive the signal transmitted by the first controller after being processed by the and gate logic circuit, and the CPU may only process the signal transmitted by the first controller.
When the state selection port of the digital selector 322 receives an indication signal sent by the CPU to indicate that the signal processing circuit is in the second state, the second input port T2 of the digital selector 322 is in an on state, and the first input port T1 of the digital selector 322 is in an off state. At this time, the response signal generated by the first sensor may be transmitted to the first controller through the digital selector 322, and the response signal generated by each of the one or more sensors other than the first sensor is directly transmitted to the corresponding controller. It should be noted that, when the signal processing circuit is in the second state, the CPU needs to control that it can be normally connected to each controller in the one or more controllers, and at this time, a response signal generated by each sensor in the one or more sensors is sent to the CPU through the corresponding controller, so that the CPU can process the signal sent by each controller.
In an alternative implementation, the output port of the digital selector 322 in the first input processing circuit 32a is connected to the data port of the first controller; the digital selector 322 output port in the second input processing circuit 32b is connected to the clock port of the first controller. Each sensor of the one or more sensors except the first sensor is respectively connected with the data port and the clock port of the corresponding controller.
In the embodiment of the present application, as shown in fig. 3 or fig. 4, the CPU10 is further configured to: before the initialization process is performed for each sensor 200, a reset instruction is sent to each sensor 200 to clear the initialization parameters stored in the registers in each sensor 200. It should be noted that, when the CPU10 sends a reset instruction to each sensor 200, the CPU10 may control the signal processing circuit 30 to be in the first state, or may control the signal processing circuit 30 to be in the second state, which is not limited in this embodiment of the present invention.
In an alternative implementation, because there are some manufacturing errors inside each sensor 200, after the initialization processing is performed on each sensor 200 by the initialization synchronization apparatus 100, each sensor 200 may transmit the acquired image to the initialization synchronization apparatus 100 for different time periods, and normally, if the time difference between the transmission of the acquired image to the initialization synchronization apparatus 100 by two sensors 200 is within 0.15 microseconds, the image information acquired by the two sensors may be considered to be synchronized. In the embodiment of the present application, in order to further improve the display effect of the subsequently synthesized stitched image, the CPU10 is further configured to: receiving image information acquired by each sensor 200 after performing the initialization process 30 on each sensor 200; judging whether the image information acquired by any two sensors 200 is synchronous or not according to the synchronous signal in the image information; compensation adjustments are made to the sensor 200 that are not synchronized with the acquired image information. Therefore, the images acquired by the sensors 200 are synchronous, and the display effect of the panoramic image formed by subsequent splicing is improved.
To sum up, the initialization synchronization device provided in the embodiment of the present application includes: a CPU, one or more controllers, and signal processing circuitry. When the CPU controls the signal processing circuit to be in the first state, the first controller simultaneously sends the initialization signal generated by the CPU to each sensor of the one or more sensors through the signal processing circuit, so that each sensor can simultaneously receive the initialization signal and complete initialization configuration at the same time, and the phenomenon that images acquired by the sensors are asynchronous is avoided. If the initialization synchronization device is integrated on the SOC, when the SOC splices the images acquired by the sensors to obtain a panoramic image, the initialization signal may be simultaneously sent to the image sensors through the signal processing circuit, so that the images acquired by the sensors are synchronously output, and the display effect of the spliced panoramic image is better. Furthermore, the CPU may further control the signal processing circuit to be in the second state, and each controller may send a parameter modification signal generated by the CPU to a sensor corresponding to each controller, where the parameter modification signal is used to adjust an initialization parameter recorded in a register of the sensor, so as to ensure that each sensor can acquire an image with higher display quality. Because the initialization parameters in each sensor can be adjusted by the corresponding controller, the efficiency of adjusting the initialization parameters in each sensor by the initialization synchronization device after the initialization configuration is completed is high.
An embodiment of the present application further provides an initialization synchronization method, which is applied to the initialization synchronization apparatus shown in fig. 3 or 4, and the method may include:
step A1, the CPU controls the signal processing circuit to be in a first state, the first state is used for indicating that a first controller is connected with each sensor in one or more sensors through the signal processing circuit, and the first controller is one controller in the one or more controllers.
And step B1, the first controller sends the initialization signal generated by the CPU to each sensor of the one or more sensors through the signal processing circuit.
Optionally, the initialization synchronization method may further include:
step A2, the CPU controls the signal processing circuit to be in a second state, and the second state is used for indicating each controller in the one or more controllers to be connected with one sensor through the signal processing circuit;
and step B2, each controller sends the initialization signal or the parameter modification signal generated by the CPU to the sensor corresponding to each controller.
Optionally, after the CPU controls the signal processing circuit to be in the first state, the initialization synchronization method may further include:
and step A3, the first controller sends signals generated by the CPU to each sensor in the one or more sensors through the output processing circuit.
And step B3, the first controller receives response signals generated by each sensor of the one or more sensors through the input processing circuit.
Optionally, step A3 may include: each of the one or more digital selectors has its respective input connected to the first controller such that the first controller sends signals generated by the CPU through the one or more digital selectors to the one or more sensors.
After the CPU controls the signal processing circuit to be in the second state, the initialization synchronization method may further include: each of the one or more digital selectors controls a respective input to be connected to a corresponding controller.
Optionally, step B3 may include: the first controller receives a signal processed by the AND gate logic circuit according to the response signal generated by each sensor of the one or more sensors.
After the CPU controls the signal processing circuit to be in the second state, the initialization synchronization method may further include: each controller of the one or more controllers receives a response signal generated by a corresponding sensor.
Optionally, step B3 specifically includes: and the first controller receives a signal which is sent by the AND gate logic circuit through the signal selector after the processed signal.
After the CPU controls the signal processing circuit to be in the second state, the initialization synchronization method may further include: the signal selector transmits the response signal generated by the first sensor to the first controller.
Optionally, after the CPU controls the signal processing circuit to be in the first state, the initialization synchronization method may further include: the signal processing circuit controls one or more IO interfaces to be connected to the first controller;
after the CPU controls the signal processing circuit to be in the second state, the initialization synchronization method may further include: and the signal processing circuit controls each controller to be connected with the corresponding sensor through an IO interface.
Optionally, the controlling, by the CPU, the signal processing circuit to be in the first state in step A1 may include: the CPU controls the register value of the system register to be a first numerical value so as to enable the signal processing circuit to be in a first state.
Optionally, the controlling, by the CPU, the signal processing circuit to be in the second state in step A2 may include: the CPU controls the register value of the system register to be a second numerical value so as to enable the signal processing circuit to be in a second state, wherein the first numerical value and the second numerical value are different.
Optionally, the initialization synchronization method may further include: before performing the initialization process for each sensor, the CPU sends a reset instruction to each sensor to clear the initialization parameters in each sensor.
Optionally, the initialization synchronization method may further include:
and step A4, after initialization processing is carried out on each sensor, the CPU receives image information acquired by each sensor.
And step B4, the CPU judges whether the image information acquired by any two sensors is synchronous according to the synchronous signal in the image information.
And C4, the CPU performs compensation adjustment on the sensor with unsynchronized acquired image information.
It should be noted that, for the principle of the initialization synchronization method, reference may be made to the corresponding parts in the foregoing embodiments of the initialization synchronization apparatus, and details are not described herein again.
The embodiment of the present application further provides a camera, which may be a panoramic camera, and the camera may include: a plurality of cameras and an SOC, the SOC comprising: the initialization synchronizer shown in fig. 3 or 4, each camera includes a sensor, which may be an image sensor, each sensor being connected to the initialization synchronizer.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (21)
1. An initialization synchronization apparatus, comprising: a Central Processing Unit (CPU), one or more controllers, and a signal processing circuit, wherein each of the one or more controllers is coupled to the CPU and the signal processing circuit, the signal processing circuit connected to one or more sensors external to the initialization synchronization device;
the CPU is used for controlling the signal processing circuit to be in a first state, the first state is used for indicating that a first controller is connected with each sensor in the one or more sensors through the signal processing circuit, and the first controller is one controller in the one or more controllers;
the first controller is used for simultaneously sending the initialization signal generated by the CPU to each sensor of the one or more sensors through the signal processing circuit when the signal processing circuit is in the first state;
the CPU is further used for controlling the signal processing circuit to be in a second state, and the second state is used for indicating each controller in the one or more controllers to be connected with one sensor through the signal processing circuit;
each controller is configured to send the initialization signal or a parameter modification signal generated by the CPU to a sensor corresponding to each controller when the signal processing circuit is in the second state, where the parameter modification signal is used to adjust an initialization parameter recorded in the sensor, and the initialization parameter is a parameter carried in the initialization signal received by the sensor in an initialization process performed on each sensor.
2. The initialization synchronization apparatus of claim 1, wherein the signal processing circuit comprises: an output processing circuit and an input processing circuit;
the first controller sends the CPU-generated signal to each of the one or more sensors through the output processing circuit while the signal processing circuit is in the first state;
the first controller receives, via the input processing circuit, a response signal generated by each of the one or more sensors when the signal processing circuit is in the first state.
3. The initialization synchronization apparatus of claim 2,
the output processing circuit includes: one or more digital selectors, an output of each of the one or more digital selectors connected to a corresponding sensor;
when the signal processing circuit is in the first state, the input end of each digital selector in the one or more digital selectors is connected with the first controller;
when the signal processing circuit is in the second state, the input end of each digital selector in the one or more digital selectors is connected with the corresponding controller.
4. The initialization synchronization apparatus of claim 3,
each digital selector comprises a first input port, a second input port, a state selection port and an output port, the first input port of each digital selector is connected with the first controller, the second input port of each digital selector is connected with the corresponding controller, the state selection port of each digital selector is connected with the CPU, and the output port of each digital selector is connected with the corresponding sensor;
for each digital selector, when a state selection port of the digital selector receives an indication signal which is sent by the CPU and used for indicating that the signal processing circuit is in the first state, the first input port is in an on state, and the second input port is in an off state;
for each digital selector, when a state selection port of the digital selector receives an indication signal sent by the CPU to indicate that the signal processing circuit is in the second state, the first input port is in an off state, and the second input port is in an on state.
5. The initialization synchronization apparatus of claim 4,
the output processing circuit includes: a first output processing circuit for outputting a data signal, and a second output processing circuit for outputting a clock signal;
the first input port of each digital selector in the first output processing circuit is connected with the data port of the first controller, the second input port of each digital selector in the first output processing circuit is connected with the data port of the corresponding controller,
the first input port of each digital selector in the second output processing circuit is connected with the clock port of the first controller, and the second input port of each digital selector in the second output processing circuit is connected with the clock port of the corresponding controller.
6. The initialization synchronization apparatus according to claim 2,
the input processing circuit includes: an AND gate logic circuit;
when the signal processing circuit is in the first state, the and gate logic circuit sends the received response signal generated by each sensor of the one or more sensors to the first controller after processing;
each controller of the one or more controllers receives a response signal generated by a corresponding sensor when the signal processing circuit is in the second state.
7. The initialization synchronization apparatus of claim 6,
the input processing circuit further comprises: a signal selector;
each sensor in the one or more sensors is connected with an input end of the AND gate logic circuit, an output end of the AND gate logic circuit is connected with a first input end of the signal selector, an output end of the signal selector is connected with the first controller, and a first sensor corresponding to the first controller is also connected with a second input end of the signal selector;
when the signal processing circuit is in the first state, the AND gate logic circuit sends the processed signal to the first controller through the signal selector;
the signal selector sends a response signal generated by the first sensor to the first controller when the signal processing circuit is in the second state.
8. The initialization synchronization apparatus of claim 6,
the input processing circuit includes: a first input processing circuit for inputting a data signal, and a second input processing circuit for inputting a clock signal.
9. The initializing synchronizer as claimed in any one of claims 1 to 8, wherein said initializing synchronizer further comprises: the system register is respectively connected with the CPU and the signal processing circuit;
the CPU is used for controlling the register value of the system register to be a first numerical value so as to enable the signal processing circuit to be in the first state;
the CPU is further configured to control a register value of the system register to be a second value, so that the signal processing circuit is in the second state, where the first value and the second value are different.
10. The initialization synchronizer according to any one of claims 1 to 8, wherein the initialization synchronizer further comprises one or more input/output (IO) interfaces, and the signal processing circuit is connected with the one or more sensors one by one through the one or more IO interfaces;
wherein when the signal processing circuit is in the first state, the one or more IO interfaces are each connected to the first controller;
and when the signal processing circuit is in the second state, each controller is connected with the corresponding sensor through an IO interface.
11. The initialization synchronization device of any one of claims 1 to 8,
the CPU is further configured to: before the initialization processing is carried out on each sensor, a reset instruction is sent to each sensor so as to clear the initialization parameters in each sensor.
12. The initialization synchronization apparatus of any one of claims 1 to 8, wherein the CPU is further configured to:
after each sensor is subjected to initialization processing, receiving image information acquired by each sensor;
judging whether the image information acquired by any two sensors is synchronous or not according to the synchronous signals in the image information;
and performing compensation adjustment on the sensors with unsynchronized acquired image information.
13. An initialization synchronization method, applied to an initialization synchronization apparatus, the initialization synchronization apparatus comprising: a CPU, one or more controllers, and a signal processing circuit, wherein each of the one or more controllers is coupled to the CPU and the signal processing circuit, the signal processing circuit connected with one or more sensors external to the initialization synchronization device, the method comprising:
the CPU controls the signal processing circuit to be in a first state, the first state is used for indicating that a first controller is connected with each sensor of the one or more sensors through the signal processing circuit, and the first controller is one controller of the one or more controllers;
the first controller sends an initialization signal generated by the CPU to each sensor of the one or more sensors through the signal processing circuit;
the CPU controls the signal processing circuit to be in a second state, and the second state is used for indicating each controller in the one or more controllers to be connected with one sensor through the signal processing circuit;
each controller sends the initialization signal or the parameter modification signal generated by the CPU to a sensor corresponding to each controller, where the parameter modification signal is used to adjust an initialization parameter recorded in the sensor, and the initialization parameter is a parameter carried in the initialization signal received by the sensor in the process of initializing each sensor.
14. The method of claim 13, wherein the signal processing circuit comprises: an output processing circuit and an input processing circuit;
after the CPU controls the signal processing circuit to be in the first state, the method further includes:
the first controller sending the CPU generated signal to each of the one or more sensors through the output processing circuit;
the first controller receives, via the input processing circuitry, a response signal generated by each of the one or more sensors.
15. The method of claim 14, wherein the output processing circuit comprises: one or more digital selectors, an output of each of the one or more digital selectors connected to a corresponding sensor;
the first controller sends the CPU-generated signal to each of the one or more sensors through the output processing circuit, including:
controlling an input of each of the one or more digital selectors to be connected to the first controller so that the first controller sends signals generated by the CPU to one or more sensors through the one or more digital selectors;
after the CPU controls the signal processing circuit to be in the second state, the method further includes:
and controlling the respective input end of each digital selector in the one or more digital selectors to be connected with the corresponding controller.
16. The method of claim 14, wherein the input processing circuit comprises: an AND gate logic circuit;
the first controller receives, via the input processing circuitry, a response signal generated by each of the one or more sensors, including:
the first controller receives a signal obtained by processing a received response signal generated by each sensor of the one or more sensors through the AND gate logic circuit;
after the CPU controls the signal processing circuit to be in the second state, the method further includes:
each controller of the one or more controllers receives a response signal generated by a corresponding sensor.
17. The method of any of claims 13 to 16, wherein initializing a synchronization device further comprises: a system register connected to the CPU and the signal processing circuit, respectively,
the CPU controls the signal processing circuit to be in a first state, and comprises the following steps:
the CPU controls the register value of the system register to be a first numerical value so as to enable the signal processing circuit to be in a first state;
the CPU controls the signal processing circuit to be in a second state, and the method comprises the following steps:
and the CPU controls the register value of the system register to be a second numerical value so as to enable the signal processing circuit to be in a second state, wherein the first numerical value and the second numerical value are different.
18. The method according to any one of claims 13 to 16, wherein the initialization synchronization device further comprises one or more input/output IO interfaces, and the signal processing circuit is connected to the one or more sensors one by one through the one or more IO interfaces;
after the CPU controls the signal processing circuit to be in the first state, the method further includes:
connecting, by the signal processing circuit, the one or more IO interfaces to the first controller;
after the CPU controls the signal processing circuit to be in the second state, the method further includes:
and each controller is connected with the corresponding sensor through an IO interface through the signal processing circuit.
19. The method of any of claims 13 to 16, further comprising:
before performing initialization processing on each sensor, the CPU sends a reset instruction to each sensor to clear initialization parameters in each sensor.
20. The method of any of claims 13 to 16, further comprising:
after each sensor is subjected to initialization processing, the CPU receives image information acquired by each sensor;
the CPU judges whether the image information acquired by any two sensors is synchronous or not according to the synchronous signal in the image information;
and the CPU performs compensation adjustment on the sensors of which the acquired image information is not synchronous.
21. A camera, comprising: a plurality of cameras and a system-on-chip SOC, the SOC comprising: the initialization synchronizer of any one of claims 1 to 12 wherein each of the cameras includes a sensor, each of the sensors being connected to the initialization synchronizer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/108445 WO2020062076A1 (en) | 2018-09-28 | 2018-09-28 | Initialization synchronization device and method and camera |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112689991A CN112689991A (en) | 2021-04-20 |
| CN112689991B true CN112689991B (en) | 2022-12-27 |
Family
ID=69950994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201880097091.1A Active CN112689991B (en) | 2018-09-28 | 2018-09-28 | Initialization synchronization device, initialization synchronization method, and camera |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN112689991B (en) |
| WO (1) | WO2020062076A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113949817A (en) * | 2021-11-30 | 2022-01-18 | 东风商用车有限公司 | Camera power-on initialization control method, device, equipment and readable storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105298758A (en) * | 2015-09-29 | 2016-02-03 | 重庆科凯前卫风电设备有限责任公司 | Acceleration sensing system of wind driven generator |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4071157B2 (en) * | 2003-05-27 | 2008-04-02 | セイコーインスツル株式会社 | Image sensor |
| CN101991426A (en) * | 2009-08-21 | 2011-03-30 | 上海境彩环保科技有限公司 | High resolution digital imaging detector |
| DE102010009775B4 (en) * | 2010-03-01 | 2012-06-21 | Rittal Gmbh & Co. Kg | Cabinet monitoring device |
| US10180340B2 (en) * | 2014-10-09 | 2019-01-15 | Invensense, Inc. | System and method for MEMS sensor system synchronization |
| US20170249464A1 (en) * | 2015-05-28 | 2017-08-31 | Telefonaktiebolaget Lm Ericsson (Publ) | METHOD FOR ENABLING SIMULTANEOUS CONTROL OF A PLURALITY OF TPMs AND RELATED COMPONENTS |
| CN106131461A (en) * | 2016-06-28 | 2016-11-16 | 湖北久之洋红外系统股份有限公司 | A kind of multiple image sensor synchronous control system and image processing module |
| CN108282600A (en) * | 2017-01-06 | 2018-07-13 | 北京京东尚科信息技术有限公司 | Refrigerator inside image capture apparatus and refrigerator |
-
2018
- 2018-09-28 WO PCT/CN2018/108445 patent/WO2020062076A1/en active Application Filing
- 2018-09-28 CN CN201880097091.1A patent/CN112689991B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105298758A (en) * | 2015-09-29 | 2016-02-03 | 重庆科凯前卫风电设备有限责任公司 | Acceleration sensing system of wind driven generator |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020062076A1 (en) | 2020-04-02 |
| CN112689991A (en) | 2021-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10999568B2 (en) | Method and apparatus for 3D capture synchronization | |
| US8205017B2 (en) | Systems and methods for addressing and synchronizing multiple devices | |
| US20110149116A1 (en) | Imaging device and method for sharing memory among chips | |
| JP2013214952A (en) | Imaging device | |
| US20230117027A1 (en) | Spi-based data transmission system | |
| JP6007509B2 (en) | Serial I / F bus control device and imaging device | |
| JP7494126B2 (en) | COMMUNICATION DEVICE, COMMUNICATION METHOD, AND PROGRAM | |
| JP6330873B2 (en) | Imaging device | |
| CN106851183B (en) | Multi-channel video processing system and method based on FPGA | |
| CN112689991B (en) | Initialization synchronization device, initialization synchronization method, and camera | |
| US20080228968A1 (en) | Image forming apparatus, image processing device, control device, and connection device | |
| US8032332B2 (en) | Semiconductor inspecting apparatus | |
| KR102176447B1 (en) | PCIe FPGA Frame Grabber based DisplayPort standard | |
| JPWO2020166378A1 (en) | Communication equipment and methods, and programs | |
| CN111757051B (en) | Data transmission method, intelligent terminal and radar system | |
| CN111970448B (en) | Optical anti-shake drive circuit, drive system, control method of drive system, and electronic device | |
| CN114205530A (en) | Self-adaptive control method and system for vehicle-mounted camera module | |
| CN110336992B (en) | Electronic equipment, calibration method and computer storage medium | |
| US6052151A (en) | Editing apparatus | |
| US11995012B2 (en) | High speed interface for multi image sensor device | |
| US20230143944A1 (en) | Information processing system, image processing apparatus, and communication control method | |
| CN110024372B (en) | Arrangement to prevent false image orientation for rear view camera | |
| JP3817741B2 (en) | Editing device | |
| KR20210080753A (en) | TRANSMITTING SYSTEM AND METHOD FOR Multi Channel Image | |
| KR20090029911A (en) | Apparatus and method for controlling camera sensor and connecting beetween board in portable terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |