JP3817741B2 - Editing device - Google Patents

Description

Technical field
The present invention relates to a distributed processing type editing apparatus including a CPU (Central Processing Unit) that controls the entire apparatus and a plurality of CPUs that respectively control a plurality of devices necessary for editing processing such as video editing. Is.
Background art
For example, there is a distributed processing method as a form in which a computer system processes a job. This distributed processing method combines each job or one job divided into small units, combined with each other, in contrast to the centralized processing method that centrally processes all jobs on one computer. This is a method of processing by distributing to calculation elements.
The editing device adopting the distributed processing method as described above is composed of a Main CPU that controls the entire device and a plurality of Sub CPUs that control various editing devices and input / output devices necessary for editing processing. The main CPU and the plurality of sub CPUs are connected by a communication line. Each Sub CPU has a process for executing a part of the editing process. Then, the Main CPU sends a command to each Sub CPU, and the Sub CPU that receives the command performs operation control of the editing device by executing a process based on the command.
In this way, in a conventional editing apparatus that employs a distributed processing method, a plurality of CPUs connected via a communication line exchange information with each other to advance editing processing.
However, in the conventional editing apparatus as described above, the Main CPU has to send a command to each Sub CPU separately. For this reason, as the number of Sub CPUs increases, the control program for the Main CPU becomes complicated and the processing speed decreases. Further, when performing video editing or the like, it is necessary to control several editing devices (hereinafter referred to as devices) at the same time, but it is difficult to synchronize for the control.
Further, as described above, when video editing or the like is performed, it is necessary to synchronize, and therefore, a timing control process is incorporated in the control program of the Main CPU. However, in video editing and the like, timing adjustment is concentrated on a single time, so when adding a device with different timing due to system expansion or changing the timing of the device, etc., control of the Main CPU The program had to be modified significantly. Further, since it is difficult to predict the timing of a device to be controlled, it has been necessary to gradually expand and correct the device. Furthermore, a great deal of time has been spent on the correction work and the debugging work for the large correction of the control program due to the expansion. Furthermore, it is difficult to add devices with different timings or change device timings while maintaining the conventional timing.
Also, when trying to develop an editing apparatus that performs advanced editing processing, the editing processing control program is concentrated in the Main CPU, so that it takes a lot of time for development time, control program correction work, and debugging work. Time was spent.
As described above, the conventional editing apparatus cannot smoothly expand the apparatus or expand the scale. In addition, when the device is expanded or scaled up, the performance of the device is reduced accordingly.
Accordingly, the present invention has been made in view of the above-described conventional situation and has the following objects.
That is, an object of the present invention is to provide an editing apparatus that can smoothly perform editing processing and can accurately and easily synchronize the apparatus.
It is another object of the present invention to provide an editing apparatus that can be easily expanded and scaled up without degrading the performance of the apparatus.
Disclosure of the invention
In order to solve the above-described problems, the present invention provides a main control unit that controls the entire apparatus in synchronization with a synchronization signal, a plurality of editing units, and a plurality of editing units. A plurality of sub-control means for controlling the operation of each editing means based on the control of the means; and a connection means for connecting the plurality of sub-control means and the main control means in a bus form by a simultaneous broadcast bus. The control means simultaneously sends control information to the plurality of sub-control means by the simultaneous broadcast bus, or selectively sends control information to the plurality of sub-control means. Each of the control means, when the control information from the main control means sent out via the simultaneous broadcast bus is for the corresponding editing means, is based on the control information. A distributed processing type editing apparatus that performs operation control, wherein the main control unit performs transmission processing along an editing program for executing editing processing including reprocessing for handling an error and a time axis. Based on the program, an edit list that is a list of control sequences in the editing process is created, and the created edit list is sent to the plurality of sub-control means by the simultaneous broadcast bus as the control information. A preparation command for instructing preparation for editing processing is sent to the plurality of sub-control means by means of a simultaneous broadcast bus, and the system time, start time of editing processing, and Edit processing time Each of the plurality of sub-control means is individually set, and a start command for instructing start of editing processing is transmitted by the simultaneous broadcast bus.
In the distributed processing type editing apparatus according to the present invention, the main control means transmits control program information as the control information.
In the distributed processing type editing apparatus having such a configuration, the main control means includes an editing program for executing editing processing including reprocessing for handling an error and a transmission program for performing transmission processing along the time axis. Based on this, an edit list, which is a list of control sequences in the editing process, is created, and the created edit list is sent as control information to a plurality of sub-control means by means of a simultaneous broadcast bus. A preparation command for instructing preparation for editing processing is sent to the plurality of sub-control means, and the system time, editing processing start time, and Edit processing time Set individually for the plurality of sub-control means, and send out a start command for instructing the start of editing processing through the simultaneous broadcast bus. Each of the plurality of sub-control means is connected via the simultaneous broadcast bus. When the sent control information from the main control means is for the corresponding editing means, the operation control of the editing means is performed based on the control information. Therefore, the main control means is specific to the editing means. There is no need to finely control processing and timing. For this reason, even when adding new editing means or incorporating editing means with different timings in the apparatus, it is possible to minimize the necessity of correcting the control program of the main control means. Further, it is possible to easily cope with the problem by adding a control program to the sub control means corresponding to the editing means to be added. Therefore, the editing apparatus can smoothly expand the apparatus and expand the scale without degrading the performance of the apparatus.
Further, in the editing apparatus according to the present invention, the main control means sends a start command for instructing the execution start of the editing process through the simultaneous broadcast bus as the control information, so that the horizontally distributed editing process is smoothly performed. And synchronization within the device can be easily and accurately achieved.
Furthermore, the control information in the editing apparatus according to the present invention is, for example, control program information. That is, the main control means simultaneously sends control program information to a plurality of sub-control means by means of a simultaneous broadcast bus of the connection means. As a result, the same control program information is sent to each editing apparatus. Therefore, it is possible to prevent the editing control program from concentrating on the main control means. For this reason, even when an editing apparatus that performs advanced editing processing is developed, operations such as correction and debugging can be reduced, and the apparatus can be smoothly expanded and scaled up.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an editing apparatus according to the present invention.
FIG. 2 is a diagram for explaining a connection state between the main CPU and the sub CPU of the editing apparatus.
FIG. 3 is a flowchart showing the control process of the Main CPU.
FIG. 4 is a flowchart showing the control process of the Sub CPU.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
The editing apparatus according to the present invention is configured, for example, as shown in the block diagram of FIG. The editing apparatus 100 includes a main CPU module 10, a plurality of sub CPU modules 20, 30,..., N 0,..., And an interrupt latch circuit 300, and the main CPU module 10 and the plurality of sub CPU modules 20, 30. ,..., N0,... And the interrupt latch circuit 300 are connected by a system bus 200.
The Main CPU Module 10 includes a Main CPU 11, a Main Memory 12, and a Main CPU Device 13. Although not shown, the Main CPU Module 10 is connected to a man-machine interface device such as a display device, a host system, and other systems. In addition to performing communication and interface control with devices and systems, it also controls operation of the entire device. Further, as the Main CPU Module 10, for example, a 25 MHz CPU is used.
.., N0,... Are shared memories 21, 31,..., N1,... And Sub CPUs 22, 32,. .., N3,..., And each of the Sub CPUs 22, 32,..., N2,. .., N3,... Are controlled. Further, as each of the Sub CPUs 22, 32,..., N2,..., For example, a 25 MHz CPU similar to the Main CPU 11 as described above is used.
Sub CPU Devices 23, 33,..., N3,... Are various editing devices and input / output devices necessary for editing processing, such as switchers, effectors that generate image effects, and video tapes that output video sources. This corresponds to a recorder, a camera, and a computer that outputs characters and figures. Sub CPU Devices 23, 33,..., N3,... Are controlled by the Sub CPU Modules 20, 30,. Yes.
The system bus 200 includes a data bus 201 and an address bus 202, and a simultaneous broadcast bus is used as the data bus 201 and the address bus 202. Further, the system bus 200 connects the main CPU module 10 and the sub CPU modules 20, 30,..., N0,. Therefore, via such a system bus 200, the Main CPU Module 10 to the Sub CPU Modules 20, 30,..., N0,... Or the Sub CPU Modules 20, 30,. ,... Can transmit various types of information to the Main CPU Module 10.
As described above, since 25 MHz CPUs are used as the Main CPU 11 and Sub CPUs 22, 32,..., N2,..., The data transfer speed in each CPU is 1 clock 40 nsec. Therefore, when it can be performed in 2 waits and 1 cycle, data transfer of 33 Mbyte / sec can be performed with 120 nsec × Bus width of 4 bytes. Further, the Main CPU 11 and the Sub CPUs 22, 32,..., N2,... Are connected by a system bus 200 using a serial link method, so that the maximum transfer speed is 1.3 Mbyte / sec at 20 Mbps. It becomes.
Next, the connection state between the Main CPU 11 and the Sub CPUs 22, 32,..., N2,.
The Main CPU 11 sends a broadcast signal indicating whether the signal sent from the Main CPU 11 is a broadcast information signal sent to all Sub CPUs or an individual information signal sent to a specific Sub CPU, to a specific Sub CPU. I / O Select signal that designates the Sub CPU when transmitting information, I / O Read signal and I / O Write signal indicating the operation mode of information reading or writing, and Data signal for transmitting and receiving data Address signals for transmitting and receiving address information are respectively output or input. As shown in FIG. 2, the I / O Select signal, the I / O Read signal, and the I / O Write signal are input to the AND circuit 11b, and the output from the AND circuit 11b and the Broadcast signal are input to the OR circuit 11a. Have been entered.
.., N0,... Have the same configuration. For example, as shown in FIG. 2, the Sub CPU Module n0 is connected to the shared memory n1. The sub CPU n2 has an I / O Read signal and an I / O Write signal indicating an operation mode for reading or writing information, a Data signal for transmitting / receiving data, and address information. Address signals for transmission and reception are respectively input and output. The I / O Read signal and the I / O Write signal are input to the OR circuit n2a.
Then, each signal from the Main CPU 11, that is, an output signal of the OR circuit 11a, an I / O Write signal, a Data signal, and an Address signal is sent to all the Sub CPU Modules 20, 30,..., N0,. .. Are supplied to terminals CS, R / W, D0... Dn, A0. In addition, the other terminals CS, R / W, D0... Dn, A0... An of each shared memory 21, 31,. That is, the output signal of the OR circuit n2a, the I / O Write signal, the Data signal, and the Address signal are supplied via the system bus 200.
The sub CPUs 22, 32,..., N2,... Are the same as the sub CPU n2, and thus detailed description thereof is omitted.
As described above, each Sub CPU Module 20, 30,..., N0,... Is provided with a shared memory that can be shared and used by each Sub CPU Module and the Main CPU 11. Information transmission from the Main CPU 11 to the Sub CPU n2 is performed via the shared memory via the data bus 201 and the address bus 202 using the simultaneous broadcast bus as described above.
At this time, the Broadcast signal sent from the Main CPU 11 is a signal in which the Address signal sent to each Sub CPU sends the same address to all the Sub CPUs 22, 32,..., N2,. This is an address signal or a signal indicating whether an arbitrary Sub CPU is selected and an address is transmitted only to that Sub CPU, that is, an individual address signal.
More specifically, for example, when the main CPU 11 sends information such as an instruction requiring synchronization to all the Sub CPU Modules 20, 30,..., N0,. Are broadcast address signals. As a result, information such as the same command is sent to all the Sub CPUs 22, 32,..., N2,. Then, all the Sub CPUs 22, 32,..., N2,... That have received information such as commands from the Main CPU 11 each determine whether or not the information is sent to their own devices. Then, the operation control of the Sub CPU Device in the same Module is performed according to the determination result.
Also, the Main CPU 10 sends control information for controlling the Sub CPU Device n3 only to a specific Sub CPU n2, for example, when setting the Sub CPU n2, etc., to the Sub CPU n2. The Address signal is an individual address signal. As a result, the Sub CPU n2 is selected, and normal address allocation is performed for the Sub CPU n2. The Main CPU 11 reads / writes data from / to the Sub CPU n2.
On the other hand, when information is transmitted from the Sub CPU Modules 20, 30,..., N0,... To the Main CPU 11, each Sub CPU uses the Interrupt signal and the individual address of the Main CPU 11 to generate Main. The CPU 11 can be accessed.
Therefore, for example, when information is transmitted from the Sub CPU n2 to the Main CPU Module 11, the Sub CPU n2 writes information in the shared memory n1 and interrupts the Main CPU 11 using an Interrupt signal. The Main CPU 11 recognizes that an interrupt from the Sub CPU n2 has been applied based on the Interrupt signal from the interrupt latch circuit 300. Then, the Main CPU 11 sets the I / O Select signal as the Sub CPU n2 and uses the I / O Read signal and the I / O Write signal in the same manner as when accessing the Sub CPU n2, and the Sub CPU Module n0. The information is read from the shared memory n1.
As described above, since the editing apparatus 100 uses a simultaneous broadcast bus for the data bus 201 and the address bus 202, the main CPU 11 may have many sub CPUs, regardless of the number of sub CPUs existing. Information can be transmitted to all the Sub CPUs by one writing. For this reason, the Main CPU Module 10 can simultaneously interrupt all the Sub CPUs by using the Interrupt signal.
Next, the control processing in the Main CPU 11 and Sub CPUs 22, 32,..., N2,.
First, although the control program incorporated in the Main CPU 11 varies depending on the purpose of use and application, it is assumed here that the editing apparatus 100 is used in a video system. For this reason, the Main CPU 11 needs to control the entire apparatus in synchronization with the horizontal periodic signal.
Therefore, the control program incorporated in the Main CPU 11 includes an editing process control program (hereinafter referred to as an editing program) and a transmission process control program (hereinafter referred to as a transmission program). In both cases, various control objects are controlled in accordance with a horizontal synchronization signal.
The main CPU 11 creates a control list based on each control program as described above, sends the created control list to the Sub CPUs 22, 32,..., N2,. Start processing and so on.
Here, for example, the editing program and the sending program share the above-described control by the horizontal synchronization signal, but the following points are different. The editing program has to wait for cueing, etc., so it must be processed again even if an error occurs, but the sending program has no waiting and there is almost no need to perform processing again. Has been made to process along.
Therefore, in the editing apparatus 100, the main CPU 11 uses the data bus 201 and the address bus 202, that is, the simultaneous broadcast bus, to control the Sub CPU by the horizontal synchronization signal that is a common point between the editing program and the sending program. Further, information from the individual Sub CPU Devices 23, 33,..., N3,... To the Main CPU 11 is performed by information transmission by individual addresses from the individual Sub CPUs to the Main CPU 11 as described above.
3 and 4 are flowcharts showing the control processing of the Main CPU 11 and Sub CPUs 22, 32,..., N2,. Hereinafter, each control process will be described with reference to FIGS.
First, as shown in FIG. 3, for example, when an instruction to execute editing is given to the Main CPU 11 by a keyboard (not shown), the Main CPU 11 lists a control sequence in editing processing (hereinafter referred to as an editing list). .) Is created (step S1). Then, the Main CPU 11 sends the created edit list to all the Sub CPUs 22, 32,..., N2,. At the same time, the Main CPU 11 uses the simultaneous broadcast bus to prepare for Sub CPU Devices 23, 33,..., N3,... (Hereinafter referred to as ST-BY instructions). .., N2,... (Step S3).
Next, the Sub CPU 22, 32,..., N2,... Receives the ST-BY command, and the Main CPU 11 receives the ST-BY of the Sub CPUs 22, 32,. It is determined whether or not the sub CPU devices 23, 33,..., N3,... Are in a waiting state by the control based on the command (step S4). Then, the main CPU 11 repeats this step process until the sub CPU devices 23, 33,..., N3,.
When the sub CPU devices 23, 33,..., N3,... Are in a waiting state, the main CPU 11 sets the system time, the start time of the editing process, the editing processing time, and the like to the sub CPUs 22, 32,. , N2,... Are set individually (step S5).
Next, the Main CPU 11 issues an instruction to start execution (hereinafter referred to as a start command) through the simultaneous broadcast bus. Are sent to the Sub CPUs 22, 32, ..., n2, ... (step S6).
Next, the main CPU 11 receives the start command from the Sub CPUs 22, 32,..., N2,..., And is based on the start commands of the Sub CPUs 22, 32,. It is determined whether the sub CPU devices 23, 32,..., N3,. The Main CPU 11 repeats this step process until the Sub CPU Devices 23, 33,..., N3,. After that, when the Sub CPU Devices 23, 32,..., N3,... Finish each editing process, the Main CPU 11 ends this process.
Next, the Sub CPUs 22, 32,..., N2,... Determine whether the Sub CPU n2 has received a command from the Main CPU 11 as shown in FIG. Step S11), this step process is repeated until a command from the Main CPU 11 is received.
When receiving a command from the main CPU 11, the sub CPU n2 determines whether or not the command indicates an edit list (step S12).
When determining that the command received by the Sub CPU n2 indicates an edit list, the Sub CPU n2 fetches the edit list from the Main CPU 11 via the simultaneous broadcast bus (step S13). Although not shown, the Sub CPU n2 creates a protocol or the like necessary for control of the Sub CPU Device n3 based on the imported edit list, and ends this process. Therefore, the following processing is performed based on this protocol.
On the other hand, if it is determined in step S12 that the command received by the Sub CPU n2 does not indicate an edit list, the Sub CPU n2 determines whether or not the received command indicates an ST-BY command. (Step S14).
When determining that the command received by the Sub CPU n2 indicates the ST-BY command, the Sub CPU n2 sends the ST-BY command to the Sub CPU Device n3 (Step S15). Thereby, the Sub CPU Device n3 performs preparatory operations such as cueing, opening a file, and seeking a file.
Next, the Sub CPU n2 receives the ST-BY command from the Sub CPU Device n3, and the operation preparation as described above is completed (hereinafter referred to as ST-BY completion). (Step S16), and repeats this step process until the Sub CPU Device n3 is in the ST-BY completion state.
When the Sub CPU Device n3 enters the ST-BY completion state, the Sub CPU n2 recognizes that the Sub CPU Device n3 has completed the ST-BY and sets the wait state of the Sub CPU Device n3 (Step S17). Exit.
On the other hand, if it is determined in step S14 that the received command does not indicate an ST-BY command, the Sub CPU n2 determines whether or not the received command is a start command (step S18).
If it is determined that the received command is a start command, the Sub CPUn2 takes in the system time from the Main CPU 11 (step S19).
Next, the sub CPU n2 determines whether the fetched system time is the start time of the editing process set by the main CPU 11, that is, the operation start time of the Sub CPU Device n3 in the process of step S5 shown in FIG. Whether or not (step S20) is determined, and the processes of step S19 and step S20 are repeated until the system time reaches the operation start time of the Sub CPU Device n3. At this time, the Sub CPU n2 adjusts the delay of the Sub CPU Device n3 according to the set operation start time.
When the system time reaches the operation start time of the Sub CPU Device n3, the Sub CPU n2 adjusts the operation execution timing of the Sub CPU Device n3 and controls the Sub CPU Device n3 to start the operation (step S21). . Thereafter, the Sub CPU n2 ends this process.
On the other hand, if it is determined in step S18 that the received command is not a start command, that is, if it is determined that the command is a command other than the edit list, the ST-BY command, and the start command described above, the Sub CPU n2 Then, processing based on the command indicated by the received command is performed (step S22), and this processing is terminated.
As described above, the Main CPU 11 does not need to finely control device-specific processing, timing, and the like. For this reason, even when a new device is added or a device with a different timing is incorporated in the apparatus, it is possible to minimize the necessity of correcting the control program of the Main CPU 11. In this case, it is possible to easily cope with this by adding a control program to the Sub CPU of the device to be added. Therefore, the editing apparatus 100 can smoothly expand the apparatus or expand the scale without degrading the performance of the apparatus.
In addition, a command requiring synchronization, for example, a synchronization command such as recording start, playback start, and pause, is sent to each device by the simultaneous broadcast bus. Therefore, it is possible to smoothly perform the horizontal dispersion type editing process and to easily synchronize the apparatus. Further, for example, when the Main CPU 11 transmits the common time to all the Sub CPUs 22, 32,..., N2,.
In the editing device 100 described above, the Mian CPU 11 and the Sub CPUs 22, 32,..., N2,... Are connected by the serial link method, but the Ethernet method (Xerox Corporation) using a coaxial cable is used. You may connect. In this case, if it is 10 Mbps, the maximum transfer rate is 800 Kbyte / sec.
However, when the CPUs are connected by a serial bus method such as the Ethernet method, transmission data collision occurs when the Sub CPUs 22, 32,..., N2,. Etc. occur. For this reason, in this case, it can be used as a simultaneous broadcast bus for transferring a broadcast address as described above via a serial bus, and the Main CPU 1 is connected to the Sub CPUs 22, 32,. , N2,... Can be individually handled. Thereby, the collision of the transmission data by a serial bus can be avoided, and high-speed CPU can be used as Main CPU11 and Sub CPU22,32, ..., n2, .... Moreover, the restriction | limiting of the number of connections of Sub CPU Module20,30, ..., n0, ... can be reduced significantly.

Claims (2)

Main control means for controlling the entire apparatus in synchronization with the synchronization signal, a plurality of editing means, and a plurality of editing means are provided corresponding to the operation control of each editing means based on the control of the main control means. A plurality of sub-control means to perform, and a connection means for connecting the plurality of sub-control means and the main control means in a bus type by a simultaneous broadcast bus, wherein the main control means has the plurality of the plurality of sub-control means by the simultaneous broadcast bus. Send control information to the sub-control means at the same time, or selectively send control information to the plurality of sub-control means, each of the plurality of sub-control means via the simultaneous broadcast bus. When the control information sent from the main control means is for the corresponding editing means, the distributed processing type editing apparatus controls the operation of the editing means based on the control information. Te,
The main control means is a list of control sequences in the editing process based on an editing program for executing an editing process including a reprocessing for handling an error and a sending program for performing a sending process along a time axis. A preparation command for creating an edit list, sending the created edit list to the plurality of sub-control means as the control information to the plurality of sub-control means, and instructing preparation for editing processing by the simultaneous broadcast bus Is sent to the plurality of sub-control means, the system time, the editing process start time and the editing process time are individually set for the plurality of sub-control means, and the editing process is executed by the simultaneous broadcast bus. A distributed processing type editing apparatus, wherein a start command for instructing start is transmitted. 2. The distributed processing type editing apparatus according to claim 1, wherein the main control means transmits control program information as the control information.

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