JPS60200357A - Inter-processor interface control system - Google Patents

Abstract

PURPOSE:To improve the data transfer capacity without increasing the number of interface lines by attaining the bidirectional control of both bus-in and bus-out lines and also extending both lines simultaneously. CONSTITUTION:The BUS-A and BUS-B function as bus-out and bus-in lines respectively and can be controlled in both directions. When both BUS-A and BUS-B are extended and used, a data selection control circuit 19 controls selection circuits 11 and 13 via a receiver 21 after a line EXT IN107 receives an indication of an extension mode. In other words, the write data on an internal output bus 101 is set to buffers A12 and B14 in a write system. Then the data on the buffer A12 and the data on the buffer B14 are sent to the BUS-A and BUS- B respectively. While the data on the BUS-A and BUS-B are set to the buffers A12 and B14 respectively and then sent to an internal input bus 102. Thus it is possible to improve the data transfer capacity without increasing the number of interface lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an interface control system between a central processing unit and an input/output control unit.

[Background of the invention]

Generally, in an information processing system, a central processing unit and an input/output control unit are connected through a standardized I10 interface to perform input/output operations.

However, in recent years, data processing by input/output devices has become faster and faster.
As the number of data buses increases, the data transfer capacity of the conventional I10 interface tends to be difficult to keep up with.As a countermeasure to this problem, for example, a method of expanding the number of data buses is used. However, this method increases costs due to the increase in cables and the number of bins of connected devices.
There are disadvantages such as the connector becoming larger.

[Purpose of the invention]

The object of the present invention is to
An object of the present invention is to provide an interface control method between processing devices that improves data transfer capability.

[Summary of the invention] In the standardized I10 interface in large-scale computer systems, etc., data buses are prepared separately for bus-in and bus-out, and both are not used at the same time in a data transfer sequence; Buses are typically unused. Therefore, in the present invention,
These bus-in lines and bus-out lines can be controlled bidirectionally, and both bus lines can be used together as an expansion bus-in line or an expansion bus-out line.

[Embodiments of the invention]

FIG. 1 shows a schematic configuration of an information processing system.

In the figure, a central processing unit (CPU) 1 and an input/output control unit (IOC) 2 are connected by an I10 interface line 3. One or more input/output devices are connected to each l0C2, but they are omitted in FIG. 1. I10
The interface line 3 includes a tag out line and a bus out line as lines from CPU1 to l0C2, and l0
The line from C2 to the CPUI is the tag-in line and the bus line.
There is an inline. The tag out line is the address out (A
DR0UT), command out (CMDOUT), select out (SEL 0UT), operation
Out (OPL 0UT), Service Out (SRV
It is a general term for control/response lines such as 0UT), and tag-in lines are address in (ADRIN), status in (STA IN), and operational in (OPL).
IN) is a general term for control/response lines such as service in.

Bus out (BUS 0UT) line, bus in (BU
The address (ADR>, command (CM
D), data (DT), status (STAT), and other information are carried, and input/output operations are executed in response to tag line responses.

FIG. 2 is a timing chart of a typical example of I10 interface operation. The I'/O interface operation is performed in startup sequence 5EQ1. Data transfer sequence 5EQ
2. Consists of end sequence 5EQ3.

The startup sequence 5EQI is a sequence for starting l0C2 from CPU1, and first the CPU is connected to BUS OUT.
Put the address on the line, set the ADROUT line to '1', and raise the SEL OUT line.In contrast, the l0C
2, if it can be started, raise the OPL IN line and turn on the BU
Put the receiving address on the S IN line and send it back, as well as AD.
Set the RIN line to II II. Next, C:PUl puts the command on the BtJS 0tJT line and sends CMD OU
The T line is set to P1''', and in response, l0C2 becomes BU
Put the status on the S IN line and connect the STA IN line to 11
Make 1 gl. When this status is received normally, CPU1 sets the SRV OUT line to 01gl to l0
In response to C2, the startup sequence is terminated.

The data transfer sequence 5EQ2 is executed when the startup sequence ends normally and the command requires data transfer. In data transfer, either a write-related command or a read-related command is executed, and both commands are never executed at the same time. For write-related commands, l0C2 sets the 5RVIN line to 'l' and requests data transfer to the CPUI. In response, the CPUI puts write data (WRDT) on the BUS OUT line and sends SRV O
UT line 'l' 4: L, TE QC24: Respond.

For read-related commands, l0C2 is read data (R
D DT) on the BUS IN line and the 5RVIN line “
1'', and when the CPUI receives the data, SRV O
The UT line is set to "1" in response to l0C2. Thereafter, similar operations are repeated to transfer a predetermined number of data.

The termination sequence 5EQ3 is executed following the termination of the start-up sequence or data transfer sequence, in which l0C2 sets the 5RVIN line to gl I II,
The status is put on the BUS IN line and the completion of execution of the command is reported to the CPUI, and in response, cPtJl sends a
Respond by setting the EV OUT line to "1".

Here, focusing on the data transfer sequence, the data to be transferred is transferred to the BUS OUT line for write-related commands and to the BUS IN line for read-related commands, but in any case, the other bus line is in an empty state. It is.

Therefore, in the present invention, this BUS OUT line, BUSIN
By making the lines bidirectionally controllable and using vacant bus lines to transfer data, the data transfer capability is improved.

FIG. 3 is a timing diagram of a data transfer sequence according to the method of the present invention. here.

BUSfA and BUS-B are BUS OUT in Figure 2.

It corresponds to BUS IN, but BUS OUT
, BUS IN is fixed in one direction, whereas BUS
-A and BUS-B can be bidirectionally controlled.

In the startup sequence and termination sequence in Figure 2,
BUS-A functions similarly to BUS OUT,
B functions similarly to BUS IN.

On the other hand, in the data transfer sequence, BUS-A,
BUS-B is both l0C2 or l0 from CPUI.
It functions as a bidirectional data bus that sends data from C2 to l0CI.

FIG. 3(a) shows a data transfer sequence in the case of a read-related command. In this case, l0C2 makes the 5RVIN line It I 11 and reads the read data (RD D
T) on both BUS-A and BUS-B and connect to the CPU
send to When the CPUI receives the read data, the CPU
The RV OUT line is set to "lII" and a response is made to l0C2. FIG. 3(b) shows the data transfer sequence in the case of a write command.

In this case, l0C2 connects the SRV IN line to It l II
requests data transfer to the CPUI, and in response,
PUI sets SRV OUT line to 111 II and writes write data (WRDT) to BUS-A and BUS-B.
and send it to l0C2.

That is, in FIG. 3, the data transfer width is substantially doubled compared to the I10 interface of FIG. 2, so the data transfer capacity is doubled.

FIG. 4 is a block diagram of one embodiment of the present invention, and for convenience, the CPU
The configuration on the IOC side, which shows the interface section on the side, is also almost the same as this. During the boot sequence.

Addresses, commands, etc. on the internal output bus 101 enter the buffer 12 from the selection circuit 11 and are sent to the BUS-A 105 via the driver 16. Also, BUS-81
Addresses, status, etc. arriving from 06 are sent to receiver 1.
7. Enters the buffer 14 via the selection circuit 13 and rides on the internal input bus 102. The same goes for the end sequence, and the status arriving from BUS-B 106 is transferred onto the internal input bus 102 via the receiver 17° selection circuit I3 and the buffer 14. Even in the case of a normal data transfer sequence, if it is a write command, the internal output bus 10
1 write data is sent to the selection circuit 11, buffer 12 . It is sent to BUS-A105 via the driver 16, and when it is a read command, it is sent to the read command on BUS-8106.
Data is transferred onto the internal input bus 102 via the receiver 17, the selection circuit 13, and the buffer 14.

The operation of the selection circuit 11.13 and the driver 16.18 is controlled by the data selection control circuit 1 via control lines tto and ttt.
9. The data selection control circuit 19 is connected to the internal processing section via a signal line 103. Furthermore, the data selection control circuit 19 is connected to an extended mode instruction input line (EXT IN) 107 via a driver 21. EXTIN line 107 is introduced according to the present invention. The interface control circuit 20 controls the tag out line 108 via the driver 22 and at the same time controls the tag out line 108.
The state on the in-line 109 is taken in via the receiver 23 and given to the internal processing section via the signal 1!104.

Next, one feature of the present invention is BUS-Al 05 and BUS
The case where the -B 106 is expanded and used will be explained. In this case, the data selection control circuit 19 via the receiver 21 selects EXT INI! When the to line receives an expansion mode instruction at It I II, it is sent via control lines 110 and 111 to activate the driver 16.18 and select the internal output bus 101 in the case of a write command. In addition, in the case of a read command, the selection circuit l controls the selection circuits 11 and 13 to disable the drivers 16 and 18 and select the receivers 15 and 17.
l.

13. Therefore, in a write command, one of the write data on the internal output bus 101, for example, the first byte, is set in the buffer 12, the second byte is set in the buffer 14, and the data in the buffer 12 is set in the driver 16.
The data in the buffer 14 is sent via the driver 18 to the BUS-B 106. On the other hand, in Lee I-type commands, 'EXT IN line 1
Since 07 is “1”, BUS-A105 and BUS
-B 106, for example, 2-byte read data arrives. Of these, data on BUS-A 105 is set to buffer 12 via receiver 15 and selection circuit 11, and data on BUS-B 106 is set to receiver 17.
, are set in the buffer 14 via the selection circuit 13, and both are sent to the internal input bus 102.

In the above embodiments, the I10 interface between the central processing unit and the input/output control unit has been described, but it goes without saying that the present invention is not limited to this.

〔Effect of the invention〕

As explained above, according to the present invention, at the time of data transfer,
Data transfer capacity can be increased without newly expanding the inter-device interface bus, and as a result, data transfer time can be shortened.

This results in an improvement in the processing power of the entire system.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a schematic configuration diagram of an information processing system, FIG. 2 is a diagram showing an example of operation of a conventional I10 interface, and FIG. 3 is a diagram showing an example of operation of an I10 interface according to the present invention. FIG. 4 is a block diagram of an embodiment of the present invention. 1... Central processing unit, 2... Input/output control device, 3.
...I10 interface. (α) SRV OsuT (b) 5RV OαT

Claims (1)

[Claims] (1) Processing devices are connected by an interface consisting of separate data buses for transmission and reception, and tag lines that control the data buses, and commands, data, etc. are placed on the data buses, and responses are sent from the tag lines. In the interface control method for performing a predetermined operation between the processing devices, the separate transmission and reception data buses can be bidirectionally controlled, and these data buses can be expanded collectively for transmission or reception. An inter-processing device interface control method characterized in that it is used.