JPS60183661A - Information processing unit - Google Patents

Abstract

PURPOSE:To execute the processing request from a peripheral unit or the like without deteriorating the execution efficiency of a CPU program by processing automatic data transfer between a special register in the peripheral unit side and an RAM in the CPU. CONSTITUTION:When an input/output request from a peripheral unit or the like is generated and an input/output processing execution request line 4 goes to an active level, an execution section 2 intermits a program under execution and receives the input/output request. When the level of an input/output processing execution mode designation line 5 is at a high level in this case, the execution section 2 processes the request as an automatic data transfer request between the special register provided to the peripheral unit side and the RAM by using the memory section 3. The automatic data transfer is conducted via a data transfer line 6 under the control of the execution section 2, and since a status and a data in the execution section 2 are stored in the location as it is, no overhead processing is required. Thus, the processing request from the peripheral unit or the like is executed without deteriorating the program excution efficiency of the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus that has an external or internal circuit that generates processing requests and has a function that can perform processing based on those requests.

Generally speaking, there are two main ways to respond to processing requests from peripheral devices and the like. One is the central processing unit (
This is a method called polling in which the CPU (hereinafter referred to as CPU) constantly monitors the presence or absence of processing requests from peripheral devices etc. using a program. In this method, until a processing request is generated from a peripheral device, the CPU only monitors the presence or absence of a processing request and cannot take the initiative to perform actual data processing, resulting in extremely poor program execution efficiency. . Therefore, the second method is an interrupt method. In this system, the CPU does not directly monitor peripheral devices, etc., but on the contrary, only when a processing request in the form of an interrupt occurs from a peripheral device, etc. to the CPU, desired data processing is performed using a single interrupt processing program. . This is the first
Compared to the above method, the program execution efficiency can be greatly improved. However, in interrupt handling mode.

To resume normal program execution, the contents of the VC, program counter, program status number word, or register contents are saved and restored.

A series of processing (overhead processing) such as branching to an interrupt vector and return processing is always required in addition to the originally required data processing. therefore.

The overhead processing described above must be performed even for processes where the requested interrupt is completed in a short time, such as transferring data from a peripheral device to a buffer in memory. , the waste of processing time cannot be ignored.

However, in application systems where such interrupts occur frequently, the program execution efficiency of the CPU actually decreases.

Therefore, it is an object of the present invention to provide an information processing apparatus that can execute processing requests from peripheral devices and the like without reducing the program execution efficiency of the CPU.

In the present invention, an information processing apparatus includes a processing request generation unit that requests processing 1 to be executed by a CPU, an execution unit that performs processing based on the processing request, and a memory unit that stores processing data, programs, etc. a first processing mode in which the processing request is processed by executing a program corresponding to the processing request stored in the memory unit, and a state of the execution unit during program execution is maintained; An information processing apparatus is obtained that includes an execution control means for executing processing in a second processing form, and a processing form specifying means for selectively specifying the processing form 'f' of the execution control means.

In the present invention, interrupt processing requests from outside the CPU chip (e.g., keyboards, displays, printer peripherals) and processing requests generated within the chip are not distinguished, but are processed at the same level (hereinafter referred to as t-l10). (called a request).

The I10 request is processed in one of two processing modes in response to an instruction signal to be described later.

The first processing mode is a conventional interrupt processing mode, in which the l10 request is processed by program processing. Here, the contents of the program counter, registers, flags, etc. are saved and released for interrupt processing. In other words, overhead processing is not executed.
This system transfers data between RAM (hereinafter referred to as RAM) and a memory (hereinafter referred to as RAM) provided in the CPU and capable of reading and writing data without performing overhead processing. This data transfer (hereinafter referred to as
This is called automatic data transfer. ) mode, the CPU interrupts the running program when a request occurs, and
The CPU itself performs one automatic data transfer process while leaving the various states (hereinafter referred to as status) and data in their current locations as they are. No special hardware is required for automatic data transfer processing.

When the CPU finishes automatic data transfer processing.

Resume execution of an interrupted program. Since there is no need for overhead processing at this time, the interrupted program processing can be resumed immediately. Therefore, the interruption of the program is not visible to the software, and it appears as if the transfer command was automatically inserted into the program processing and processed.

Automatic data transfer processing has the effect of minimizing the frequency of occurrence of interrupts, which are mainly caused by software processing, and reducing the burden on software processing. Therefore, this process is, for example, a percentage of data transmission and reception with a serial interface device.
It is used for reading converted data in an A/D converter device, and for simple data transfer between a peripheral device and a buffer area of a memory, which was conventionally handled by interrupt processing. on the other hand.

When performing editing, averaging processing, etc. of a series of data transferred by the rotation data transfer processing based on the l101t=request, the conventional interrupt processing in the first mode is used. In other words, the first mode can be applied to interrupt processing that requires the use of registers, flags, etc., and the second mode can be applied to data transfer between memory within the CPU and peripheral devices, or between internal circuits of the CPU. It can be applied to simple data transfer processing such as data transfer. Therefore, since the second mode does not require overhead processing time, the effective processing efficiency of the CPU can be significantly improved.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of its main parts. In this embodiment, the I10 request control unit 1.1 controls processing requests from peripheral devices, etc. an execution unit 2 that performs processing in response to a processing request output from the I10 request control unit 1; 3. I10 processing cost request line to which the I10 request signal is transferred; 4. I10 processing mode designation line 5 that specifies the processing form; data between the execution unit 2 and the memory unit 3; It has a data transfer line 6 for sending and receiving data.When an I10 request is generated from a peripheral device etc. and the I10 processing execution request line 4 becomes active level, the execution unit 2 interrupts the program being executed.
The I10 request is accepted. The execution unit 2 is I10 at this time.
Depending on the level of the processing mode designation line 50, one of two types of processing modes is selected and the processing is performed. In this example, I1
If the 0 processing processing mode designation line 5 is at a low level, the I10 processing request is processed as an interrupt request, while if it is at a low level, it is processed as an automatic data transfer request from the SFR in the memory unit 3 to the RAM or from the RAM to the SFR. do. Automatic data transfer is performed via the data transfer line 6f under the control of the execution unit, but in order to maintain all the status and data in the execution unit 2 as they are, the program required for one interrupt processing is There is no need for saving or restoring the contents of the 2M counter, program status word, or various registers, or so-called overhead processing.

Next, FIG. 2 shows a block diagram of the I10 request control section 1 in FIG. 1, and the operation will be explained using it. Here, three types of I10 request generation sources, A, B, and C, will be explained as examples. The I10 request control unit 1 controls the I10 request generation sources A, B,
I10 request generation units 7, 8.9 generate I10 requests corresponding to C, respectively, and I10 request line 11A for issuing I10 requests.

11B and IIC, I10 processing form at-specifying I1
0 processing type designation lines 12A, 12B and 12C1 are connected to the priority determination and I10 processing designation unit 10 that controls the priority determination process and the process of transmitting the I10 processing type to the execution unit, and to the execution unit 2 in FIG. I10 process execution request #
4, and an I10 processing type designation line 5.

When an I10 request is generated from an I request generation source, the I10 request line from the corresponding I10 request generator becomes active level. At the same time, the I10 request generation unit appeared
When 10 requests are to be processed by interrupt processing (first mode), I10 processing mode designation M12 is set to all low level.

On the other hand, when automatic data transfer processing (second mode) is desired, the designation line 12 is set to a high level. each I10
Request lines 11A, IIB and 1ICU priority determination and processing 10 processing specification section 10'''I', 11A>11B>I
It is assumed that priority is given in the order of IC. The priority determination unit selects the request with the highest priority among the input I10 requests. Furthermore, the highest priority I
I10 from the I10 request generator generating the 10 request
The level of the processing mode designation line is determined and outputted to the 't-l10 processing execution mode designation line 5.

Next, FIG. 3 shows a detailed block diagram of the execution section 2 and the memory section 3 in FIG. 1, and the operation will be explained. VO processing execution request line 4 and I10 of billing control unit 1 in the first cause
The processing mode designation line 5 is an I1 that controls the operation of the execution unit 2.
0 request reception is connected to section 15. A program storage unit 13 stores a program for interrupt processing programs, etc.
The program counter 14 accesses the program counter 14. The operating status of the entire execution section is stored in the program-status word register 16. Furthermore, the execution unit has an arithmetic and logic operation function of 20 nits (hereinafter referred to as ALU)17. An instruction register 1'8 that holds a group of instructions to be executed. It includes an instruction decoder 19 that generates various control signals based on the contents of the instruction register, and an execution control section 20t that controls the operation of the entire execution section based on the output of the critical decoder 19.

In addition, each execution unit has a memory pointer (hereinafter referred to as MP) that can point to an address in the RAM of the memory unit 3, and an SFR that can point to an address in SFH on the peripheral device side.
A pointer (hereinafter referred to as 5FRP), a terminal counter (hereinafter referred to as TC) that stores the number of automatic data transfers, and a group of three registers 21 for automatic data transfer processing into which any value t-V can be stored using no-toware.
, 22 and 23.

The execution unit normally transfers the instruction stored at the address of the program storage unit 13 corresponding to the contents of the program counter 14 to the instruction register 18.
The instruction transferred to the instruction decoder 19 is decoded,
Based on the results, the execution control unit 20 performs various controls to execute the program. And every time you execute one instruction.

The value of the program 2 Mukakunta 14 is updated to the address where the next instruction to be executed is stored.

Here, when the I10 request reception section 15 detects that the I10 processing cost request line 4 has reached the active level, it interrupts the execution of the program and samples the level of the I10 processing type designation line 5 at that time. If the I10 processing type designation line 50 level is low level, the I10 request reception section 15 recognizes that the request is an interrupt processing request.

In this state, based on the control signal from the execution control unit 20, the contents of the program counter 14 and the contents of the program status word register 16 are saved to the memory unit 3, and then the program counter 14 is stored at the starting address required by the interrupt processing program. Set. This starts the interrupt processing program. When the interrupt processing program is completed through a series of program processing, the program counter 14 and the program status word register 16 that were saved in the memory section 3 are returned to the state at the time of interruption. So-called overhead processing is executed.

On the other hand, when the I10 processing mode designation line 5 is at a high level, the request receiving unit 15 recognizes that the request is an automatic data transfer request, and registers the program counter 14, program status word register 16, etc. (10) The register group corresponding to the request source is referenced while the contents of the registers are held in their respective locations. Here, the register group 21 is I
10 request source A register group 22 is I10 request source B
, the register group 23 corresponds to the I10 request source C, respectively. Assuming that the I10 request generation source that is determined to have the highest priority by the priority determination and I10 processing specification unit 10 and whose I10 processing type specification line 5 is at a high level is 1, for example, I10 request generation source A, the register group 21
is referenced. Furthermore, the I10 request reception unit 15 controls the execution control unit 20 to send the contents of the address pointed to by the MP to the 5FRP.
or transfer the contents of the address pointed to by 5FRP to the address pointed to by MP. This can be performed using the same control as normal transfer command execution. Therefore, the operation of the execution unit is not stopped during automatic data transfer processing. After that, the VO request is accepted by the ALU 17 in the section 15.
and controls the execution control unit 20 to add 1 to the value of MP and store the answer in MP again, and subtract t-1 from the value of TC and store the answer in TC again. Terminates the automatic data transfer process. However, if the value of TC is subtracted and becomes 0, the I
10. Control is performed to generate an interrupt request corresponding to the request generation source, and a series of automatic data transfer processing is completed. Therefore, since an interrupt request has been generated when the automatic data transfer process is finished, the interrupt process can be subsequently started and the data transferred by the automatic data transfer process can be processed by the interrupt process program.

Next, FIG. 4 shows the I10 request generation section 7.8 in FIG.
9 and the priority order determination and I10 processing designation unit 10 will be shown in detail, and their detailed operations will be explained together with the execution unit 2. I/D request generation unit and priority determination and I1
The 0 processing designation section includes a control circuit 100 including an I10 request generation section 7 and a priority determination and I10 processing designation section 10 shown in FIG. 2, and control circuits 200 and 300 having completely equivalent circuit configurations to the control circuit 100. Control unit 13200
The I10 request generation unit 8 is connected to the control circuit 300, and the I10 request generation unit 8 is connected to the control circuit 300.
Each of them includes a request generating section 9. Since the operations are exactly the same, an example of the control circuit 100t will be explained here. The control circuit 100 has a set/reset clip-flop (hereinafter referred to as R) that stores the occurrence of the I10 request.
It is abbreviated as 8F/F. ) is I10 request 7 lip/70 tub (hereinafter referred to as l10RQF/F) 104. Interrupt mask pin for inhibiting interrupt processing requests) 105.
Automatic data transfer processing permission F/F that is an R S F/F that permits automatic data transfer processing 113. and a vector holding unit 120 for knowing which address the program should branch to when the execution unit accepts an interrupt request.

It includes an I10 process execution request line 30 and an I10 process type designation line 34 connected to the execution unit 2 in FIG. The request line 101 from the I10 request source is connected to the set input of the I10RQF/F104, and the request line 101 is connected to the set input of the I10RQF/F104.
When becomes high level, l1 through or gate 103
0R, QF/F104 are set. Interrupt mask bit 105 and automatic data transfer processing enable F/F 113
can be freely set and reset by a program; 1 interrupt mask bit 105 is set when interrupt request 'x%' is stopped, and automatic data transfer processing enable VFF 113 is set when all automatic data transfer processing is desired to be performed.

When the interrupt mask bit 105 is reset and the automatic data transfer enable F/F 113 is reset, the request line 101 from the I10 request generation source goes high, and the I10RQF/F 104 is set. On operation! 5? , reveal.

The output of the automatic data transfer permission F/F 113 is low level, the control manual 111 for controlling the priority is low level, and the output of the RQF/F 104 and the output of the interrupt mask pin 105 are low level, so the ant game) 107 is The output becomes high level, and the outputs of OR gates 108 and 110 become high level. Since the output of the OR game 1-110 is connected to the OR gate 210, and the output of the OR game 210 is connected to the OR gate 310, the I10 process execution request! 3 (1: or
The state of the output of the gate 108 becomes high level. When the I10 request reception unit 15 of the execution unit 2 detects that the I10 process execution request line 30 has become high level, it interrupts the program being executed.

Indicates that an I10 request has been accepted. I10 request reception outputs a signal (hereinafter referred to as I10ACK signal) 32,
This is an RS F/F indicating that the I10 request has been accepted through the AND gate 109. Engineering 10 request reception F
/F (hereinafter referred to as ISF/F) 112t-Set. At this time, even if the I10 request is generated in the control units 200 and 300, the outputs of the OR gates 110 and 210 are at a high level, so the OR gate 1 in the control circuit 100
The outputs of the OR gates in the control circuits 200 and 300 corresponding to 08 do not become high level, and the control circuit 200
and ISF/F in 300 are never set.

In other words, the ISF/F has an I10 request source with a higher priority than the I10 request of its own control circuit.
This is a 7 lip-flop that accepts I10 requests when no I10 requests are generated. When ISF/F112 is set, a rising edge is detected by the rising edge detection circuit 119 to which the output of ISF/F112 is connected, and l10RQF/F104 is reset and the primary I
10 Prepare for request reception. Also, 115, which is a tri-state buffer, is made active.

Contents of automatic data transfer permission F/F 113 'tI10 Output to process execution mode designation line 34. In order to receive a request from the execution unit, the execution unit recognizes that it only needs to perform one interrupt process to sample the low level of the automatic data transfer permission F/F 113 output to the I10 process type specification line 34, and executes the program. Starts interrupt processing such as saving counters and program status words. After the interrupt processing is started, when the execution section receives the I10 request, the execution section sets the vector read signal 36 to a high level to determine the address of the beginning of the interrupt processing program. As a result, -ISF/F1
12 is high level, automatic data transfer permission F/F 11
3 is at a low level, the output of the inverter gate 122 becomes a high level, so the output of the AND gate 121 becomes a high level and the tristate buffer 119 becomes active. Therefore, vector information in the vector holding section 120 is output to the bus 31 of the execution section. At this time, the output of the AND gate 118 is the automatic data transfer permission F/F 11.
3 is at low level, it does not go to high level and tristate buffer 116 does not become active. When the execution unit receives the I10 request, the unit takes in the data on the bus 31, controls the execution control unit 20 in FIG. 3, branches to the address corresponding to the taken data, and starts executing the interrupt processing program. The ISF/F 112t is reset by setting a signal 33 indicating that the I10 request processing has been completed (hereinafter referred to as an EOP signal) to a high level. When you finish a series of interrupt processing programs, the saved programs
The contents saved in the counter, program status, word register, etc. are restored and the interrupted program execution is resumed.

Next, when automatic data transfer permission F/F 113 is set, an I10 request occurs and l10RQF/F
The operation when 104 is set will be explained. At this time, the output of the l10RQF/F 104 and the output of the automatic data transfer permission F/F 113 are at a high level, and the control input 111 for priority control is at a low level, so the output of the AND gate 106 becomes a high level, and the OR gate 108 The outputs of 110 and 110 become high level. The output of OR gate 110 is connected to the input of OR gate 2100,
Also, since the output of the OR gate 210 is connected to the OR gate 3100 input, the I10 process execution request 1tj30 becomes high level unconditionally. The execution unit accepts the I10 request when it detects that the I10 processing cost request line 30 has become high level.

It accepts the I10 request, interrupts the running program a/-), outputs the 5I10ACK signal 32, and outputs the AND gate 108.
Set ISF/F112 through.

The l10RQF/F104 is reset by the output of the rising edge detector 119 to which the output of the ISF/F112 is connected. In addition, the output of ISF/F112 is set to active with tri-state buffer 7115 and automatic data transfer permission F/F112.
The contents of F113 are output to the I10 processing type designation line 34. At this time, the execution unit receives the I10 request.
In order to sample the high level of the processing execution designation line 34,
We fully recognize that automatic data transfer processing is a good thing. Then, in order to obtain the information necessary for automatic data transfer processing, I1
0 request reception, the vector read signal 36 is set to high level in the section, and the processing information holding section 1 which sets the tri-state buffer 116't active and holds the information necessary for automatic data transfer processing.
17 information @i is output to the bus 31 of the execution unit. At this time, the information output from the processing information holding unit 117 includes register group selection information indicating which register group should be selected and the direction of automatic data transfer, that is, from SFR to RAM or from RAM to SFR. Consists of specified information. The I10 request reception section refers to the register group based on the information obtained from the bus 31.

The execution unit 1tlliil1 of the execution unit is controlled by the referenced register group pointer and transfer direction designation information, and the transfer process is completed by performing the same control as when executing a normal data transfer instruction. After that, %MP is added by 1 and TC is subtracted by 1, and when the result of the subtraction becomes TC = 0, the I10 request reception is an automatic data transfer prohibition signal to prohibit automatic data transfer and perform 1 interrupt processing. As a 35tl-no level, automatic data transfer permission F/F113e no.
-Forcibly reset on Doquaa. Also ISF/F11
Since the output of 2 is at a high level, the automatic data transfer inhibit signal 35 is set to a high level, so that the I10RQF/F is
104 is set. After that, the I10 request reception section sets the EOP signal 33 to the no-y level, and the ISF/F1
12 and completes a series of automatic data transfers.

However, here self d + I, + data transfer permission F/F
Since 113 is reset and 10RQF/F 104 is set, a normal interrupt request is generated, 1 interrupt processing is activated, and the program branches to 1 interrupt processing program. The interrupt processing program executes various program processes based on data transferred by automatic data transfer processing.

Next, the above embodiment will be explained using an actual application as an example.

Considering the A/D converter as the I10 request source, I1
A 0 request occurs at the end of an A/D conversion operation. Normal A/
The D-converted value is used by averaging several sampled values through calculation.

Therefore, set the number of data you want to average in TC.

Also, set the address where the result of the A/D conversion value is stored in the 5FRP, set the address of an appropriate buffer area in the memory pointer, set the automatic data transfer permission F/F 113, and reset all 1 interrupt mask bits 105. The processing information holding unit 117 has the direction of automatic data transfer from fil-8FR to R.
Specify it in the form of AM to start A/D conversion. Then, each time A/D conversion is completed, the A/D converted value is automatically stored in the buffer area, and an interrupt occurs when the operation of adding 1 to MP and subtracting 1 from TO is performed the number of times specified in TC. . Therefore, in the interrupt processing program, by simply averaging the data stored in the buffer area and resetting the MP and TC, the number of occurrences of one interrupt can be greatly reduced and the execution efficiency of the program can be improved.

Furthermore, in this embodiment, the automatic data transfer process does not completely stop and control the operation of the execution unit, but rather uses hardware for controlling instruction execution during normal program execution in order for the execution unit to perform the transfer process. can be realized without adding special /1-ware for automatic data transfer processing. Further, although the present embodiment shows an example in which the priority order is fixed, it is possible to easily handle processing request control in which the priority order is variable. In addition, automatic data transfer processing was considered only for data transfer, but by combining this with control such as normal instruction comparison instructions, it can be used for even more advanced applications without adding special hardware. A highly flexible information processing device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...I10 request control unit, 2...Execution unit, 3...Memory unit, 4...I10 process execution request line, 5... ...I10 Processing mode designation line, 6...Data transfer line. FIG. 2 is a block diagram showing the I10 request control section 1. As shown in FIG. 7.8.9...I10 request generation section, 10...
...Priority determination and I10 processing specification section, IIA, 1
1B, IIC...I10 request line, 12A, 12
B. 12C...I10 processing mode designation line. The third factor is a detailed block diagram of the execution unit 2 and a block diagram showing the memory unit. 14...Program φ counter, 15...
...I10 request reception is in section 16...Program status word, 21, 22, 23...
register group. FIG. 4 is a logic diagram of the I10 request generation units 7, 8.9 and the priority determination and I10 processing designation unit IO. 100.200,300...control unit, 101.
...Request line, 104...l10RQF/
F, 105... Interrupt mask bit, 112...
...ISF/F. 113... Automatic data transfer permission F'/F, 11
7...Processing information holding unit, 120...Vector holding unit, 30...I10 Processing execution request line%
34...I10 processing processing mode designation line.

Claims (1)

[Claims] The program processing unit includes a processing request generation unit that generates a processing request, an execution unit that selectively executes a program process and a process based on the processing request, and a memory unit, and that is executed in response to the processing request. is interrupted and displays the current status.
- selectively executing a first processing mode in which the processing request is received after saving data, and a second processing mode in which the processing request is received without saving data indicating the state. Information processing device.