JPS63118947A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To perform an interruption processing with superior responsiveness, by setting the interruption requesting level of a macro service executed without performing the saving of a register, etc., higher than another interruption requesting level. CONSTITUTION:When a processing request 8 is generated from a processing request generating source, and a request flag group 103 is set, an interruption request control part sets a flag 103 based on the content of a processing type designating flag when it requests a macro service processing executed without performing the saving of a register group, and sets an interruption processing type signal line 104 at a high level, and when a general interruption processing is performed, it sets the signal line at a low level. An execution part 2 interrupts a program in executing currently when the signal line 14 is set at the high level, and executes the macro service processing by obtaining the address information and the content of data processing of a macro service channel register 303. The flag 103 is reset by a signal 10 by which a processing is completed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides computer functions on a single semiconductor chip! The present invention relates to a single-chip microcomputer having a built-in function, and particularly relates to a single-chip microcomputer having a built-in function of processing processing requests from various peripheral devices.

[Conventional technology]

2. Description of the Related Art In recent years, as integrated circuit manufacturing technology has progressed, a higher degree of integration has been promoted in single-chip microcomputers (hereinafter referred to as SMCs) that realize computer functions on a single semiconductor chip. Additionally, peripheral devices such as timer counters, A/D converter circuits, serial transmitter/receiver circuits, etc. are also becoming more sophisticated by providing multiple channels of various types of devices. For this reason, the central processing unit (hereinafter referred to as CPU) not only needs to execute data processing based on instructions at high speed, but also needs to execute data processing efficiently and at high speed in response to processing requests from peripheral devices, etc. ing.

Conventionally, a method called an interrupt has been widely used as a means for a CPU to execute and control high-speed data processing in response to a processing request from a peripheral device or the like. For interrupts, CP
When U detects an interrupt request from an interrupt request source such as a peripheral device, it interrupts the program processing currently being executed and transfers control to a routine of an interrupt processing program that performs data processing corresponding to the interrupt request. In general, there are cases where it is necessary to perform specific processing such as real-time data processing with peripheral devices with priority over other processing, regardless of the program currently being executed by the CPU. For processing requests that are generated asynchronously, the CPU uses hardware to check for the occurrence of an interrupt processing request at each break in the execution sequence of each instruction.If a processing request is generated from a peripheral device, etc. Sometimes, the CPU interrupts the currently executing program and moves to interrupt processing. When processing interrupts, registers, programs, etc. are
It is necessary to save the contents of a counter (hereinafter referred to as PC), a program status word register (hereinafter referred to as PSW), etc. to a memory section called a stack. When the interrupt processing is completed, the PC and P saved in the stack
By restoring information such as SW and register values to their original locations, execution of the interrupted program is resumed. In addition, in application systems that require execution control of multiple processing requests,
Usually, a technique called pectoral interrupt, which will be described below, is used.

This is selection data (vector) from a peripheral device or interrupt request control unit to select a program corresponding to the processing request source from among multiple interrupt processing programs.
is sent and matched. The vector encodes the position of the interrupt processing program in the program memory, and the CPU can obtain the start address of the interrupt processing routine based on the value of the vector. A branch destination table address is determined based on the vector value sent to the CPU following the interrupt processing request, and a branch is made to the processing routine based on the data value within the table address.

On the other hand, depending on the content of the application program, it may be desirable to prohibit acceptance of interrupt processing. For example, when another interrupt handling routine is already being executed and you want to avoid the stack from becoming any deeper, or when you are directly manipulating the contents of the stack with instructions. For this reason, an SMC equipped with an interrupt processing system is equipped with an interrupt enable flag (hereinafter referred to as EI flag) that controls the acceptance of interrupt request processing.
Interrupt acceptance is inhibited/enabled depending on the contents of the efrag. The EI72 flag is set when it is necessary to accept interrupt processing, and is reset when it is desired to prohibit acceptance of interrupt processing, such as when executing an interrupt processing program. ′! In addition, since the EI Effrag is automatically reset in terms of hardware when interrupt processing is started, it can be set again (
interrupts enabled) state.

Next, a conventional interrupt processing system in an SMC will be explained using a specific example. FIG. 5 is a block diagram of a main part of an interrupt processing system in a conventional SMC, which consists of the following components.

The interrupt request control unit 1 has an interrupt request flag IP (hereinafter referred to as IP) that stores the occurrence of processing requests from various peripheral devices.
IF103d, IF103e, vector code constant part 101 containing vector information corresponding to each processing request, and the contents of IP and EI7 lag signals 6. Interrupt request reception is performed by priority control that performs condition judgment priority control and interrupt request reception. generates an interrupt processing request INTRQ (hereinafter referred to as INTRQ) 5 to the determination circuit unit 102 and the execution unit 2, transmits a request to start interrupt processing, and also requests a vector code output request 0BVC (hereinafter referred to as 0EVC) from the execution unit 2. 7
A control logic that outputs a predetermined vector code to the bus 9 according to the IP clear signal LRIFIO from the execution unit 2
This includes various control logics for resetting the IP in response to processing requests.

Execution unit 2 internally disables and enables pecter interrupts.
I7=7g201. It includes a PC, PSW, ALU, instruction register, program memory, various registers, and memory in which microprograms for executing instructions and interrupt processing are stored, and handles interrupt processing based on INTRQ5 generated from the interrupt processing request control unit 1. It has the function of controlling the interrupt request control section 1.

The memory unit 3 stores processing data related to peripheral devices such as timers, A/D converters, and serial transmitter/receiver circuits, and the execution unit 2
It includes a data storage area 301 for the instruction execution results obtained by the CPU, and a stack area (hereinafter referred to as stack) 302 used to save PC, psw, and registers when starting an interrupt process. Data is input and output via the

Furthermore, it has a group of peripheral devices such as a timer, an A/D converter, and a serial transmitter/receiver circuit that have a processing request generation function, that is, a processing request generation source. In FIG. 5, processing requests 8d and 13e are generated from a processing request generation source 4d on a single semiconductor chip and a processing request generation source 4e external to the board, respectively, and these are transmitted to the interrupt request control unit 1 and the corresponding interrupts are generated. Request flag F'1oaa and IF103e are set.

Furthermore, a special register section (
A register (hereinafter referred to as 8F) 401 is provided, and the registers in the 7'c8FR 401 corresponding to the processing request generation sources 4d and 4e are accessed by the execution unit 2 via the server 9.

Next, the interrupt processing operation in the SMC shown in FIG. 5 will be explained.

First, a case will be described in which the fiEI flag is set by an instruction in the execution unit 2 and a predetermined program is executed while checking the occurrence of INTRQ5. In this example, two types of processing request sources will be described below: an internal processing request source 4e located on a single semiconductor board and an external processing request source 4e located outside the board.

When an interrupt factor occurs in each processing request source, such as a counter overflow operation or a serial data reception operation, each processing request source generates a processing request gd,
8e and sets the interrupt request flags IF103d and IF103e in the interrupt request control unit 1. The interrupt request control unit 1 includes each IF 103d.

Based on the contents of the IF 103e and the contents of the EI flag 201 obtained via the EI flag signal line 6, the interrupt reception conditions are determined and priority control is performed. Here, since the EI7 lag 201 has been set in advance and interrupt acceptance is enabled, the interrupt request control section 1 activates INTRQ5 to notify the execution section 2 of the occurrence of an interrupt processing request.

When the execution unit 2 detects that INTRQ5 has become active, it interrupts the program processing that is being executed, and
w, 0EV to save the contents of registers to the stack 302 of the memory unit 3 via the bus 9 and output the position information of the interrupt processing program to the interrupt request control unit 1;
Activate C signal 7. Interrupt request control unit 1 is 0
When EVC signal 7 becomes active, vector code constant 1
A predetermined vector code corresponding to the processing request generation source is selected from 01 and transmitted to the execution unit 2 via the bus 9. The execution unit 2 branches to the interrupt processing program based on the transmitted vector code, and also resets the EI flag 201 to disable interrupt reception, and at the same time activates the IF flag clear signal (hereinafter referred to as CLRIF) 10 to select the interrupt processing program. Clears the IF hook corresponding to the processing request origin. If processing requests are generated from multiple processing request sources and multiple IP flags are set, only one process with the highest priority is selected, and the others are put on hold with their IP flags set. be done. Therefore, in FIG. 5, the priority order of the processing request generation sources 4d and 4e is set as 4d>4e,
If processing requests gd and ge are generated at the same time, the processing request source 4d is selected, and the vector code output by 0EVC7 described above is output as a code corresponding to the processing request source 4d, and is cleared by the CL IF signal 10. The interrupt request flag to be sent is IF103d. The interrupt processing program executes processing corresponding to the processing request source. For example, when receiving sampling values by A/D conversion,
Processing of transferring the data to the data storage area 301 in the memory unit 3, processing of changing mode settings of peripheral devices, etc. are performed. These operations are performed by the execution unit 2 accessing the register in the 8FR 401 corresponding to the processing request source via the bus 9 and performing data processing. When the above interrupt processing program ends, the PC and PSW are saved to the stack 301.
, restores the contents of registers, and sets the EI flag 2.
01 is set again, that is, interrupt acceptance is enabled, and the original program whose execution was interrupted is returned to. In some SMCs, setting the EI flag 201 here is done by instruction processing such as the EI instruction, but it is also possible to set the EI flag 201 in a PSW that is saved by hardware when starting an interrupt process or in a register. A method of simultaneously returning to the previous state (the set state of the EI flag 201) when executing the process of restoring the PSW and registers is widely used because it eliminates the need to execute the EI instruction and is more efficient.

Next, even if the EI flag 201 is reset and processing requests gd and 8e are generated from the processing request sources 4d and 4e, the interrupt request controller 1 sends an INTRQ5 to the execution unit 2.
A case in which the signal does not become an active signal will be described. In this case, the execution unit 2 cannot detect the occurrence of a processing request even if it checks INTRQ5, so in the program processed by the execution unit 2, the 8FR4
The occurrence of processing requests 8d and 8e can be detected by monitoring the operating status by reading the contents of the register 01, or by polling the contents of IF103d and 103e of the interrupt request control unit 1. If the interrupt processing rate is high, processing such as branching to a predetermined interrupt processing program is performed.

[Problem that the invention seeks to solve]

In a single-chip microcomputer with a built-in interrupt processing system based on the conventional vectored interrupt described above, in order to normally return to the original program when vectored interrupt processing is started, it is necessary to save the PC, PSW, registers, etc.
Flag reset processing and branch processing to the interrupt processing program are required, and when returning from the interrupt processing program, the overhead of restoring the saved PC, PSW, registers, and EI near-yg contents is required.
It has always been necessary in addition to the original interrupt processing program execution processing. Additionally, during the execution of a vectored interrupt processing program, due to stack area limitations, even if an extremely simple processing request such as a data transfer between a peripheral device and memory occurs, it cannot be processed. In application systems where a large number of processing requests are generated from a request source in a short period of time, there is a drawback that, contrary to the purpose of having a built-in interrupt processing system, efficient and high-speed data processing cannot be realized.

[Means for solving problems]

The SMC of the present invention is an SMC in which computer functions are integrated on a single semiconductor chip, and includes an interrupt processing request control unit that generates an interrupt processing request in response to processing requests from various peripheral devices, and a user program that generates the interrupt processing request. The first processing mode is processed by a microprogram, and the second processing is processed by a microprogram while retaining the internal state related to program execution.
and a control means for selectively prohibiting only the execution of the interrupt processing according to the first processing method, and the control means selectively inhibits execution of the interrupt processing according to the second processing method executed by the execution section. The interrupt processing is executed at high speed by having the interrupt request control section designate the operation control of various peripheral devices and the special register section for data buffer.

The present invention is characterized in that processing requests from processing request generation sources existing inside and outside of the same semiconductor chip, such as peripheral devices or internal circuits, are processed in two types of processing formats as specified by a program. The first processing type is conventional interrupt processing, in which an interrupt request is processed by program processing (hereinafter, the first processing type is referred to as a vector interrupt). The second processing form is SFR, which is used as an operation specification and data buffer for processing request sources such as peripheral devices and internal circuits.
A series of data processing such as read and write data transfer, data exchange, and content update (increment, decrement, and inversion) to a writable memory is performed by microprogram processing without user program intervention. (Hereinafter, the second processing form will be referred to as a macro service). In the macro service, when an interrupt processing request occurs, the running program is interrupted and the CPU is
The normal program execution operation of the CPU is stopped, and data processing corresponding to the processing request source is executed while various internal statuses of the CPU and data of general-purpose registers and the like are held. Macro services are realized by utilizing the existing hardware of the CPU itself, and there is no need to add special hardware such as FIFO or DMA circuits. CPU
When the macro service ends, the suspended program is restarted using the status and data that it held. Therefore, the interruption of the program is not visible to the software, and it appears as if the instruction was automatically inserted during program processing. The macro service minimizes the frequency of vectored interrupts that require operations such as saving and restoring internal status information from the stack, thereby reducing the software processing load.

For example, simple data processing between the SPR of a peripheral device and the buffer area of the memory, which was previously handled by Pector interrupt processing, such as when receiving data from a serial interface circuit is transferred to memory, or when reading converted values from an A/D converter/device. can be executed very quickly and efficiently using this macro service processing.

〔Example〕

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing its components. Interrupt request control includes flags necessary for controlling and controlling processing requests 8 from processing request generation sources 4 such as peripheral devices, and constant parts necessary for interrupt processing. unit 1, an execution unit 2 that controls execution operations of the entire 8MC including operations in response to interrupt processing requests generated from the interrupt request control unit 1, a stack 302 used when executing vector interrupt processing, a data storage area 301, and Memory section 3 containing registers used in macro services
, 8F including special registers used for specifying the operation of the processing request generation source 4 such as peripheral devices and the processing request generation source 4, and for exchanging data.
R401, signal line INTRQ5 through which the interrupt request control unit 1 transmits an interrupt processing request to the execution unit 2, an interrupt processing type designation signal line that specifies whether the interrupt processing type is to be performed by vector interrupt processing or macro service processing. M
8/lNT14 (hereinafter referred to as M8/lNT14), interrupt request control unit 1. Execution unit 2. )Mo I) Part 3.5FR40
a signal line bus 9 for exchanging data between 1ty);
Set by processing requests from each processing request source,
Each IF stores the occurrence of a processing request.

Interrupt request flag group IF 103, processing mode specification flag group MSF 104, which is a processing mode specification flag (hereinafter referred to as MSF) that stores the processing execution mode when processing the processing request of each processing request source by interrupt, and vector interrupt. A vector code constant unit 10 that stores vector code information to be output in response to a constant output request 12 from the execution unit 2 during processing execution.
1. A macroservice channel register MSC (hereinafter referred to as MSC) 303 that stores the processing contents of the macroservice and memory address information to be used when executing the macroservice, and an MSC 303 that corresponds to the macroservice startup processing request source 4. MSC that stores the address information of and outputs it in response to the constant output request 12 from the execution unit 2.
Address constant part 1o5, 8FB address constant part 106 and SPR address which store address information of 8FR401 corresponding to each processing request source accessed by macro service and output in response to SPR address constant output request 13 from execution part 2 Specified line 15, CLRIF signal 10, which instructs the execution unit 2 to terminate interrupt processing and clears the IP corresponding to each processing request source in Ir2O3; A processing mode designation flag clear signal CLRM8 (hereinafter CL
RMS) 11, and a signal line 6 for transmitting the contents of the EI flag 201 to the interrupt request control unit IK.

Next, the operation of this embodiment will be explained using FIG.

When a processing request 8 is generated from the processing request generation source 4 and Ir2O3 corresponding to the processing request generation source is set, the interrupt request control unit 1 uses the EI flag 201 and the contents of the MSF 104 corresponding to the processing request generation source. The priority order and interrupt acceptance are determined by determining the conditions and processing NTRQ5. MS/lNT
14, the execution unit 2 is informed of the occurrence of the interrupt request. Here, the interrupt request control unit 1 executes interrupt acceptance by determining conditions and INTRQ5. The signal level of MS/1NT14 is the EI flag 201 and MSF1 corresponding to the interrupt request.
It is divided into the following three states according to the contents of 04.

The first is EI7. F/201. When both MSF104 are reset, at this time [INTRQ5, M
Both S/1NT14 are at non-active level, and Ir2O3 is set and the interrupt request is held in good condition.

The second one is set with EI7 lug 201.

This is a case where the M8F104 is reset, and at this time, INTRQ5 is at an active level and MS/1NT14 is at a non-active level. Execution unit 2 is INTRQ5
When it detects that the current level has reached the active level, the program being executed is temporarily suspended and processing of the interrupt request begins.

Furthermore, depending on the level of the execution unit 2dM8/lNT14 signal, it is selected whether the interrupt processing is accepted by pecter interrupt processing or macro service processing, and the processing is performed. Therefore, interrupt requests are processed using Pector interrupt processing in the same way as conventional interrupt processing. The third is MSF1
If 04 is set, at this time EI7? KINTRQ5, MS/lNT
14 to the active level.

The execution unit 2 detects the active level of INTRQs,
When it learns that the MS/lNT14 is at the active level, it selects to process the interrupt request with the macro service, suspends the currently running program, and moves to the micro program processing operation of the macro service. . That is, the execution unit 2 activates the constant output request 12 and causes the interrupt request control unit 10M8C address constant unit 105 to output address information of the MSC 303 corresponding to the processing request generation source via the bus 9.

Furthermore, based on this M8C address information, the MSC 303 in the memory unit 3 is read out, and the address information of the data storage area 303 in the memory unit 3 used in the macro service,
After obtaining information such as data processing contents, macro service processing is started. At this time, if the macro service processing specified by the contents of M80303 is, for example, an operation to set data for mode setting in the 8FR401 corresponding to the processing request source 4, the execution unit 2 SFR
Outputs the constant output request 13 and interrupts the SF of the interrupt request control unit 1.
The SFR address information corresponding to the processing request generation source is output from the R address constant section 106, and 5FR401 is specified via the SFR address designation line 15, and at the same time, the MSC3Q
Data storage area 3 in memory unit 3 specified by the contents of 3
Data is output from 01 via bus 9, and 5FR40
Transfer to 1. Contrary to the above-mentioned content, when the processing content of the macro service is to transfer the content of the 8FR 401 corresponding to the processing request generation source 4 to the data storage area 302, the execution unit 2 also sends the SFR to the interrupt request control unit 1. The address constant section 106 outputs SPR and constant, and SFR.

This is done by reading the specified 8FR401 data via the address designation line 15 onto the bus 9 and transferring it to the data storage area 302 of the memory section 3 specified by the contents of M80303.

CLRIF signal 10 when macroboobis ends
Activate to reset Ir2O3 and INTR
Q5 is returned to the non-active level, the interrupt processing is terminated, and the interrupted original program is resumed.

In addition, the number of executions of data transfer processing by these macro services is counted, and when a predetermined number of data transfer processing is completed, Pector interrupt processing is subsequently started, and data averaging and calculation processing are performed by the interrupt processing program. This can also be easily achieved. For example, in the data storage area 302, a buffer area for transfer data, a pointer memory (hereinafter referred to as MP) indicating the address of the transfer buffer area, and a counter memory (hereinafter referred to as TC) for counting the number of transfers are allocated. wear. It is assumed that the address information of MP and TC is specified by the contents of M80303, and the number of transfers set in TC is set in advance by a program. The sequence in which the macro service is activated is the same as that shown in the previous example, but the buffer area for transfer data used during transfer processing is now specified by the contents of MP. When the transfer process between the memory specified by the contents of MP and the SPR is completed, the execution unit 2 next adds 1 to the contents of MP and sets the contents of TC to 1.
After subtraction, the values are stored in MP and TC respectively, and then it is checked whether the contents of TC are O# or not. If it is TC-irO here, activate the CLRIFIO signal,
Reset Ir2O3 corresponding to the processing request source, and
Return NTRQ5 to the non-active level and end the macro service.

If it is TC~0, the CLRM811 signal is activated to reset the M8F104 corresponding to the processing request generation source, Ir2O3 is left set as it is, and the macro service processing is terminated. As a result, E
INTRQ if I7 lug 201 is set
5 is at the active level, and only M8/1NT14 is at the non-active level, so that the execution unit 2 can subsequently start processing of the vector interrupt. Also, if the EI7 lag 201 has been reset and an application program that does not have a deep stack is being executed, the I
NTRQ5 should be at non-active level, Ir2O3
It is possible to end the macro service while the vector interrupt is still set and the vector interrupt is pending.

Macro service processing is carried out via the bus 9 under the control of the execution unit 2, but the status and contents of the PC and registers are all retained.

It becomes unnecessary to save and restore the PC, psw, and registers, and to set and reset the EI flag, which are required in vector interrupt processing. Furthermore, the memory used by the macro service is only that specified by the contents of M3C303, and multiple macro service processes are mutually exclusive and are not nested.
Unlike vectored interrupts, there is no need to limit the startup of macro service processing due to stack capacity limitations.

If you also want to prohibit interrupt processing by macro services, you can reset the MSF 104 corresponding to each processing request source by program. There is no need to provide special hardware to control the prohibition and permission of

Next, the priority control and interrupt request reception included in the interrupt request control unit 1 in FIG.
A somewhat detailed block diagram of O3 and MSF 104 is shown in FIG. 2, and its operation will be explained. Here, the processing request source is a
, b, and c.

FIG. 2 shows processing requests 8 from processing request sources a, b, and c.
a, 8b, 8c, IFs 103a, 103b, 103c that are set by the processing request, and MSFs 104a, 104b that specify the interrupt processing form for each processing request.

104C, IF, MSF, and EI Effrag signal 6. Acceptance of each processing request is an AND-O that performs condition judgment.
RCI chics 501a, 501b, and 501c, a priority control circuit unit 109 that performs priority control, vector code constants, M8C address constants, and CLRIF signals 10 and CLR from the 81 address constant designation and execution unit.
Interrupt request selection signal lines 505a and 505b specifying IB' and MSF to be reset by the MS signal 11
, 505c and an interrupt processing request IN to the execution unit.
TRQ5. Processing mode designation line M8/1NT14 and EI flag signal 6 which conveys the contents of the EI flag.

First of all, both IF and MSF are in reset state,
The case where the processing request 8a is generated when the EI7 eff flag signal 6 is at the high level will be explained. Processing request 8a
103a is set due to the occurrence of IF10.
The output of 3a is transmitted to AND-OR gate 501a,
If the output of the MSF 104a or the E-effrag signal 6 is at a high level, the output of the AND-OR gate 501 also becomes a high level and is transmitted to the priority control circuit section 109.

Here, the level of the M8F104a is low, but the output of the Efrag signal 6 is high level, so the AND-
The output of the zero gate 501a becomes high level. When the output of the AND-0 gate becomes high level, the priority control circuit section 109 selects the one with the highest priority among the outputs of the AND-OR gates that have become high level, and outputs the corresponding interrupt request selection signal line. to a high level. Here, the AND-OR gate that has become high level is AND-OR
Since there is only gate 5o1a, interrupt request selection signal 5
05a is selected and becomes high level. Furthermore, the priority control circuit 109 receives the INT signal at the same time as the interrupt request selection signal is generated.
It activates RQ5 to notify the execution unit of the occurrence of an interrupt processing request, and outputs the contents of MSF corresponding to the selected interrupt request selection signal to MS/lNT 14 to designate the interrupt processing mode. Here M8F104a
is selected and communicated to the MS/lNT 14. That is, MS/1NT14 is at a low level. When the INTQ5 goes high, the execution unit starts interrupt processing according to the level of the MS/1NT14.
Since I NT 14 is at a low level, Pector interrupt processing is activated. When pecta interrupt processing is started, the contents of the pecta code constant output by the interrupt request control section in response to a constant output request sent from the execution section are determined by the interrupt request selection signal and the level of the MS/1NT 14. Further, the IF selected by the interrupt request selection signal line 505a by the CLRIF signal 10 from the execution section is reset, so that the output of the AND-OR gate 501a is at a low level, and the IF 103a is reset.

When all INTRQs are at low level, the startup of the vector interrupt process ends.

Second, a case will be described in which the processing request 8a occurs when the M8F 104a is in the set state.

When the processing request 8a occurs and the IF 103a is set,
Regardless of the level of the EI7 lag signal 6, the output of the AND-OR signal 501a is at a high level and is transmitted to the priority control circuit 10a. The priority control circuit 10a selects the one with the highest priority among the AND-OR gates outputting a high level, and sets the corresponding interrupt request selection signal to a high level. Here, AND-OR gate 501
Since only a is at high level, interrupt request selection signal 5
05a becomes high level. Furthermore, priority control circuit 1
0a sets INTRQ5 to high level, transmits an interrupt processing request to the execution unit, and also outputs the interrupt request selection signal 505.
M8/lNT14 the contents of M8F104a corresponding to a.
Output on top. Here, MSF104a is set, so MS/1NT14 becomes high level. In the execution part, INTRQ5=high level, M8/lNT14=
Detects that the level is high and executes macroboobice processing. When a macro service is executed, the interrupt request control unit selects the interrupt request selection signal line 505a and MS/l in response to a constant output request and an 8FR address constant output request from the execution unit.
MSC address constant and S selected by NT14
Outputs FR address constant. Also, when the macro service processing completion execution unit #) CLRIF signal 10 is output, the IP I O3a, AND-OR gate 501a,
When the interrupt request selection signal line 505a and INTRQ5 are all set to low level, the macro service process ends. However, if the execution unit 1) CLRIF signal 10 is not output and the CLRM8 signal 11 is output, only the MSF 104a selected by the interrupt request selection signal 505a is reset, and the contents of the IF 103a do not change.

Therefore, if the EI flag signal 6 is at a high level, the AND
-OR) 501a remains at high level, interrupt request selection signal 505a and INTRQ5 remain at high level, and only the level of MS/1NT14 changes from high level to low level. As a result, the execution unit detects INTRQ5=high level and M8/1NT14=low level, and after the macro service processing is completed, it is possible to proceed to the vector interrupt processing. Furthermore, if the EI flag signal 6 is at a low level, when the M8F 104a is reset by the CLRMS signal 11 from the execution section, the A
The output level of the ND-OR gate 501a becomes a low level, the interrupt request selection signal line 505a and INTRQ5 also become a low level, and the macro service processing ends with the IF 103a set.

Third, a case will be described in which the processing request 8a occurs when the M8F 104a is in the reset state and the EI7 lag signal 6 is at a low level. At this time, the IF
Even if 103a is set, AND-O) I gate 50
Since the output of 1a remains at a low level, the occurrence of a processing request is not transmitted to the priority control circuit 10a, and the interrupt processing request is suspended.

This is the same state as when the execution section outputs the CLRM8 signal 11 and ends the macro service process when the EI72 signal 6 is at a low level in the explanation of the second macro service process.

In the first, second, and third explanations above, the operations corresponding to the processing request generation source a have been explained, but the operations corresponding to the processing request generation sources G, C, as well as the IFs 103b, 103c, MSF 104b,
104c, AND-OR game) 501b and 501c are performed in exactly the same sequence using interrupt request selection signal lines 505b and 505c. As explained above, in this embodiment, the PC interrupt processing is prohibited/permitted depending on the contents of the EI flag.

Macro service processing that does not require operations such as psw is E.
Regardless of the contents of the I flag, it is possible to always accept and process processing requests. It is also easy to execute vector interrupt processing following macro service processing, and the prohibition/enablement control of vector interrupt processing at this time is exactly the same as the control of acceptance of normal vector interrupt processing based on the contents of the EI flag. It will be done.

In the 8MC according to the present invention described above, by processing processing requests using macro services, operations such as saving and restoring internal status information from the stack are unnecessary, compared to the case where processing requests are processed only by vector interrupt processing. This has the effect of greatly increasing the execution efficiency of the program. Also, during macro service processing, the interrupt request controller can directly specify the 8FR corresponding to the processing request source. Processing such as data transfer processing between the data back 78FR of the serial transmitting/receiving circuit and internal memory can be executed at very high speed. This means that if we consider a case where 8FB address information is set in the memory section, etc., the execution section will extract the address information of the memory in which the necessary 8FB address information is set from the interrupt request control section or the contents of M2O. After accessing the memory and obtaining 8FR address information based on this,
The sequence is to access the SFR corresponding to the processing request source and execute data processing.
This becomes clear when comparing the above method with the method of this embodiment in which the interrupt request control section directly specifies the 8FR address and immediately performs data transfer. Furthermore, since macro service processing is executed by microprogram processing similar to decoding and executing normal instructions, the execution processing is mutually exclusive, and like pectoral interrupt processing, the internal status is stored in the stack area. Since there is no need to save information, problems such as limitations on nesting due to the capacity of the internal stack area do not occur at all. Therefore, there is no need to use the EI7 lag to prohibit or allow acceptance of interrupt processing requests as in Pectoral interrupt processing, and processing requests from processing request sources that require high-speed data processing are not accepted, contrary to the user's intention. This makes it possible to minimize wasted time such as being put on hold.

FIG. 3 is a block diagram showing the main parts of a second embodiment of the present invention. FIG. 3 shows an IFI 03 that is set by a processing request generated from each processing request source, an MSF 104 that specifies the form of interrupt processing based on each processing request, and an interrupt mask that controls permission to prohibit acceptance of each side request. An interrupt mask flag group MK510 consisting of flags MK (hereinafter referred to as MK). A vector code constant section 101 containing pecta code information used in the execution of pecta interrupt processing, M
MSC address constant section 10 containing SC address information
5. SFR address constant section 106 that includes 8F address information corresponding to the processing request generation source; reception of each processing request is performed by condition determination and priority control; interrupt request reception is performed by the judgment circuit 102 or above; and the INTRQ generated by the interrupt request control unit 1.
5. Controls acceptance of interrupt processing requests based on MS/1NT14, and outputs CLIFto, CLMSII, constant output request signal 12゜SFR address constant output request signal 13
, an EI that controls the prohibition/enablement of acceptance of vectored interrupts.
Signal line 6 that conveys the contents of the flag 201 and the EI flag
It also controls the operation of the interrupt request control unit 1, and
Performs execution control of the entire SMC. Execution unit 2 and execution unit 2
A stack 302 that is accessed via the Yoshibus 9 and used for pecter interrupts, an MS used for macro services
C303 and a memory unit 3 including a storage area 301 for various data, and a peripheral device having a function of generating processing requests such as an A/D conversion circuit, a timer, and a counter.
Interrupt request control unit 1 via Yoshibus 9
5FR4 accessible via B addressing line 15
01, and a processing request generation source 4 that transmits a processing request 8 to the interrupt request control unit 1.

In the second embodiment, as is clear from FIG. 4, an MK510 is newly provided in the interrupt request control section 1 of the first embodiment.

MK510 is IF103. Similar to the Mf9F104, it is provided for each processing request generation source and performs individual prohibition and permission control for each side request. In other words, even if a processing request 8 is generated from the processing request source 4 in which the MK 510 is set, the corresponding IF 103 is only set.
MSF104. INT regardless of the contents of EI 201
RQ5 is not activated, interrupt processing is not activated, and the contents of each individual MK have no effect on the control logic when accepting other processing requests. Therefore, in the first embodiment, the prohibition and permission control of each vector interrupt processing is performed with an EI7 lag of 20
1 could only be controlled all at once, but the 2nd
In this example, both the macro service and the vector interrupt processing can be individually controlled by the MK, and in a system with multiple processing request sources, only the required processing request can be executed by the interrupt processing. It becomes possible to control.

Next, in FIG. 4, the interrupt request controller 1 in FIG. IF103, MS
F104. A block diagram of the MK510 is shown to explain the control logic and operation. This FIG. 5 corresponds to FIG. 2 of the first embodiment, and here there are three types of processing request generation sources, a, b, and c. FIG. 4 shows IF 103a set by processing requests 8a, 8b, and 8c.

103b, 103c, MS that specifies interrupt processing type
F104a, 104b, 104c, individual processing request reception ffe prohibited, allowed MK510g, 510b, 510
c. AND-OR gate 502a for reception control;
502b.

502c, a control signal CLRIF signal 10. from the priority control circuit section 109 and the execution section. The CLRM8 signal 11°, the interrupt processing request INTRQ5 to the execution section, the interrupt processing mode designation line M8/1NT14, the EI flag signal 6, and the interrupt request selection signal lines 505a, 505b, and 50C.

Here, the operation corresponding to the processing request generation source aK will be explained, but the same sequence as in the first embodiment is performed also when the processing request generation source AK corresponds to the processing request generation source cK. When multiple processing requests occur simultaneously, an interrupt request corresponding to the processing request source with the highest priority is issued based on the priorities set in hardware and software in the priority control circuit section 10a. Similarly to the first embodiment, a processing request is accepted and processed when the selection signal line is at a high level.

As a first operation, a case will be described in which a processing request 8a occurs when the MK 510a has been reset in advance. When the 9 IF 103a is set by the processing request 8a, the AND-OR gate 502a is activated only when the EI flag signal 6 or the MSF 104a is set, similar to the operation shown in FIG. 2 of the first embodiment. The high level output is transmitted to the priority control circuit section 109. The priority control circuit unit 10a sets IN'l'Q5 to high level and changes the contents of MSF104a to MS/lN.
The interrupt request selection signal line 505a is transmitted to the read execution unit on T14, and the interrupt request selection signal line 505a is set to high level. The execution part is INT
When it detects that RQ5 has become No. 1 Repel, MS/
Interrupt processing is executed in a processing format based on the level of the 1NT14. Below is a summary of the contents of M8F104a M8/lN
Depending on the level on T14, vector interrupt processing or macro service processing is executed, but since these operations are completely the same as in the first embodiment, their explanation will be omitted.

As a second operation, a case where the processing request 8a occurs when the MK 510a is set in advance will be described. At this time, even if the output F103a is set by the processing request 8a, the output of the AND-OR gate 502a remains at the low level regardless of the contents of the EEF flag 6 and M8F104a. Therefore, the occurrence of the processing request 8a is not transmitted to the execution section via the priority control circuit section 109, and the interrupt processing is not activated. Therefore, the processing request 8a is held pending with its occurrence being stored in the IF 103a.

As described above in the first and second operation descriptions, the MK 510a can be used to prohibit or permit acceptance of the processing request 8a.

The SMC in the second embodiment has all the features of the first embodiment by simply providing an MK flag corresponding to the processing request generation source, and also allows the contents of the MSF to be used in an application system having multiple processing request generation sources, for example. Prohibition of accepting individual processing requests while retaining the information.

It has a highly versatile interrupt processing system that can be used for applications such as permission control.

〔Effect of the invention〕

As explained above, in the single-chip microcomputer according to the present invention, there are two processing modes in which processing requests from a processing request source are processed by an interrupt processing program using vectored interrupts that are controlled depending on the contents of the EI flag, and one processing mode in which processing requests are processed by an interrupt processing program based on the contents of the EI flag. This system is efficient and has a processing mode in which processing is performed by a macro service that can perform high-speed and real-time processing by using SFR address information corresponding to the processing request source that is accepted regardless of the interrupt request control unit and output from the interrupt request control unit. By incorporating a versatile interrupt processing system, the system provides high-speed data processing with excellent responsiveness and high hardware efficiency, even for application systems where processing requests from multiple processing request sources occur frequently in a short period of time. There is an effect that processing can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a block diagram of the priority control/interrupt request acceptance determination circuit 102, Ir2O3, and M8F 104 in FIG.
FIG. 3 is a block diagram showing the configuration of the second embodiment of the present invention, FIG. 4 is a block diagram of the priority control/interrupt request acceptance determination circuit 102 and Ir2O3°MSF 104 of FIG.
FIG. 5 is a block diagram showing the configuration of a conventional SMC. 1... Interrupt request control unit, 2... Execution unit, 3...
Memory section s 4a+4b, 4c...processing request source, 4d...internal processing request source, 4e...external processing request source, 5...INTRQ signal, 6...EI7
Lag signal line, 7...0EVC signal, 8, 8a, 8b,
8C-Processing request, 8d... Processing request from internal processing request source, 8e... Processing request from external/processing request source, 9... Bus, 10... CLRIF signal,
11... CLRMS signal, 12... Constant output request signal, 13... SFR address output request signal, 14...
・M8/lNT115...SFR, address designation line,
101...Vector code constant part, 1o2...Determination circuit for priority control/interrupt request reception, 103...Interrupt request flag group, 103a, 103b, 103c, 10
3d, 103e... Interrupt request flag, 104...
Processing mode designation flag group, 104a, 104b, 104
c.--Processing mode specification flag, 105...MSC buttress constant section, 1o6° SFR address constant section, 201
...EI flag, 301...Data storage area, 30
2...Stack area (stack), 303...Macro service channel register MBC, 401--Special register section 8FR, 501a. 5ρlb, 501c...AND-OR gate, 502
a, 502b, 502c...AND-OR gate, 505a, 505b. 505c...Interrupt request selection signal line, 510...Interrupt mask flag group, 510a, 510b, 510c
...-Interrupt mask flag.

Claims (1)

[Claims] A single-chip microcomputer in which computer functions are integrated on a single semiconductor chip includes an interrupt request generation section that generates an interrupt request in response to a processing request from a peripheral device, and an execution section that performs interrupt processing based on the interrupt request. In preparation, the execution unit selectively executes a first processing mode in which the interrupt request is processed by a user program, and a second processing mode in which the interrupt processing is performed while maintaining an internal state regarding the program being executed. A single-chip microcomputer, characterized in that only execution of interrupt processing according to the first processing mode is selectively prohibited.