JPH023876A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To eliminate the need for performing the interruption processing of other processor, and to quickly respond to plural interruption causes by providing an address control means which loads address data to be received at an input/output port to a program counter according to an interruption response for an interruption request. CONSTITUTION:At first, a chip select deciding means 42 outputs the interruption request 44 to its own machine according to chip select data to be received at the input/output port 40 in an input mode or by a control signal to be inputted directly to the chip select deciding means 42. Then, after waiting for the interruption response 45, the address control means 30 loads the 8-bits address data of the input/output port 40 as low-order address data to the program counter 31 according to index designation, and acts so as to transfer the control of the processor to this address. Thus, the unnecessary interruption of the program due to the interruption processing from other processor is removed, and it becomes possible to respond to the unrestricted interruption request quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement in the interrupt function of a single-chip microcomputer.

(b) Conventional technology Advances in semiconductor manufacturing technology have enabled arithmetic and logic units,
It has become possible to form not only an accumulator, but also a memory and various interfaces on one silicon chip. This type of microcomputer is called a single-chip microcomputer, and initially it was mostly oriented toward application purposes, but today it has processor functions comparable to general-purpose microcomputers, expandability, and versatile interface functions. We are prepared.

Therefore, multiprocessor systems using such high-performance, highly functional single-chip microcomputers are beginning to be considered.

Now, in a multiprocessor system, each processor is rarely able to operate independently, and often continues to operate while exchanging data with each other, but one processor's data generation or data request is received from another processor. Since this occurs randomly, an interrupt function is used for data communication between brokers.

For this reason, multiprocessor systems using general-purpose microcomputers use dedicated interrupt controllers or interrupts via external interrupt input, but in multiprocessor systems using single-chip microcomputers, dedicated interrupt controllers are In many cases, the use of a dedicated interrupt controller is not possible due to the difference in performance, and the use of a dedicated interrupt controller has the disadvantage that a good cost/performance ratio cannot be obtained. Furthermore, interrupts caused by external interrupt inputs have the disadvantage that single-chip microcomputers cannot handle many causes of interrupts due to limitations on the number of pins and other factors, and the data and control buses become large.

Therefore, a data communication system between single-chip microcomputers, which is common today, will be explained with reference to FIG. Multiprocessor systems of the drawings using single-chip microcomputers usually have serial or parallel interfaces (
40), data communication/interrupts between processors are performed through the communication pro!・Coll is as follows: (1) The master/slave processor (3) sets the input/output board (40) to input mode, and the other processor (
Wait for data communication in 1).

(2) Input/output interface (4) of processor (3)
0) outputs an interrupt request upon receiving address data.

(3) The processor (3) determines whether the address data received by the interrupt process specifies itself.

(4) The designated processor <3) then receives data and, if necessary, executes a predetermined interrupt process after executing an interrupt process branch routine.

That is what it is.

However, in this data communication method, even when communicating between specific processors, all processors use interrupt processing to determine whether or not they are designated, and interrupt requests are frequently made between specific processors. A system in which interrupts occur or a large-scale system has the disadvantage that each processor is forced to handle interrupts without making a decision. Furthermore, in order to handle multiple interrupt causes, an interrupt processing branch routine must first be executed, which has the drawbacks of slowing down processing speed and placing a heavy burden on the software required to distinguish between interrupt causes. .

(c) Problems to be Solved by the Invention The present invention eliminates the need for other processors to process interrupts in the case of specific inter-processor communication, and furthermore quickly responds to multiple interrupt causes without burdening software. An object of the present invention is to provide a single-chip microcomputer with an interrupt function capable of interrupting.

(d) Means for Solving the Problems In order to solve the above-mentioned problems, the single-chip microcomputer of the present invention includes a chip select determination means (42) that outputs an interrupt request (44) to its own machine, and (44
), the input/output boat (
40) and an address control means (30) for loading address data received by the program counter (31) into the program counter (31).

(f) Effect In the configuration of the present invention described above, the chip select determination means (42) first selects the input/output board (40) which is in the input mode.
Based on the chip select data received by the chip select data or the control signal input directly to the chip select determination means (42), an interrupt request (44) is output to the own machine, and the address is output after waiting for an interrupt response (45). Control means (30)
The 8-bit address data of the input/output port (40) is loaded into the program counter by specifying the index P as low-order address data, thereby transferring control of the processor to that address.

(F) Embodiment Referring to FIG. 1, the present invention will be described in detail by taking inter-processor data communication as an example. In the figure, (3) is a single-chip microcomputer of the present invention. For convenience, this will be referred to as a slave processor, and processor (1) will be referred to as a mask processor.

The slave processor (3) controls equipment (not shown) via the input/output port (41) through original program processing, or generates and updates data dat 1, dat 2, etc. required by the mask processor (1). death,
Each time, data dat1 is stored in the RAM (33) at address 0000H, dat2 is stored at address 0OOIH, and so on.

Then, for example, at address 0030H of the ROM (32) of the slave processor (3), "ooo of RAM (33).

The command "to output the data at address H to the input/output port (40)" is written, and the "instruction to output the data at address 0OOIH of the RAM (33) to the input/output port (input/output port)" is written at address 0Q38H of the ROM (32).
40>, all instructions to be output are written in the ROM (32), and a plurality of instructions are similarly written in the ROM (32).

Therefore, when the mask processor (1) needs the data dat2 of the slave processor (3) to perform its own program processing, it first transfers the chip select data or control signal for chip selection to the system bus (2). Output to. The chip select determination means (42), which may then consist of a programmable decoder or simply one bit of a register, may be configured based on the particular chip select data received by the input/output port (40) or An interrupt request (44) is generated directly from the control signal. The above operation is performed independently of the processor function, and the slave processor (3) can continue its own program during this time. Further, it is naturally possible for other processors (not shown) to continue their own programs after this point.

When the chip select determining means (42) detects chip select data specifying itself or outputs an interrupt request (44) by a control signal, the slave processor (3) interrupts the program being processed and starts the program counter ( 31), an accumulator (34), and a flag register (37), etc., and then outputs an interrupt response (45). As a result, an interrupt response flag is set in the interrupt flag register (43).

When the mask processor (1) detects the interrupt response flag by any means, it then outputs 8-bit address data 38H which becomes an interrupt vector. Note that when the control signal can be used for chip selection, the interrupt vector 38H can be output simultaneously with the output of the control signal, and in this case, the processing speed can be further improved.

Upon receiving the interrupt response (45), the address control means (30) generates 16-bit address data 0038H from the 8-bit address data of the input/output port (40) by index designation or other known means, and sends the address data 0038H to the program counter. (
31). This allows the slave processor (
3) transfers control to address Q Oa 8H, and it becomes possible to execute the command "output the data at address 0OOIH to input/output capo (40)" of RAM (33) written there.

When the data dat2 is thus output to the input/output port, the mask processor (1) can learn the value of the data dat2 via the system bus (2) and continues processing its own program that requires this data. This makes it possible.

Note that in the above communication method, the slave processor (3)
If the mask processor (1) needs it before it generates data, for example dat 2, the mask processor (1) continuously outputs an interrupt vector 38H and generates the data dat 2 of the slave processor (3). However, this problem can be solved by taking measures such as not accessing interrupt vectors that have not output data for a certain period of time.

When the single-chip microcomputer of the present invention is used as described above, any data requested by a processor can be obtained from other processors at any time,
There is no need to reserve a data area for the processor, and a particularly remarkable effect can be expected when constructing a multiprocessor system using a single-chip microcomputer with relatively limited RAM capacity.

(g) Effects of the Invention The single-chip microcomputer of the present invention does not need to use interrupt processing to determine whether address data is specified for itself each time it is sent from another processor. There is no program interruption, and since interrupt vectors are provided via an 8-bit bus, it is possible to quickly respond to an unlimited number of interrupt requests.
Suitable for use in multiprocessor systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiprocessor system using a single-chip microcomputer according to the present invention, and FIG. 2 is a block diagram of a multiprocessor system using a conventional single-chip microcomputer. (1) and (3) are single-chip microcomputers, (2) is a system bus, (30) is an address control means, (31) is a program counter, (32) is a ROM,
(33) is a ram, (34) is an accumulator, (35〉
is - hour register, (36) is arithmetic logic unit, (
37) is a flag register, (38) is an instruction decoder, (
39) is an internal bus, (40) and (41) are input/output interfaces, (42) is a chip select judgment means, (
43) is the interrupt flag register, <44) is the interrupt request, (
45) is an interrupt response.

Claims (2)

[Claims] (1) Chip select determination means for outputting an interrupt request;
A single-chip microcomputer comprising address control means for loading address data received at an input/output port into a program counter based on an interrupt response to the interrupt request. (2) The single-chip microcomputer according to claim 1, wherein the chip selection determining means is constituted by a programmable decoder.