WO2020062076A1 - Initialization synchronization device and method and camera - Google Patents

Abstract

Embodiments of the present application provide an initialization synchronization device and method and a camera, relating to the technical field of video processing. The initialization synchronization device comprises: a CPU, one or more controllers, and a signal processing circuit. Each of the one or more controllers is coupled to the CPU and the signal processing circuit. The signal processing circuit is connected to one or more sensors on an outer portion of the initialization synchronization device. The CPU controls the signal processing circuit to be in a first state, and the first state is used to instruct a first controller to connect to each of the one or more sensors by means of the signal processing circuit. The first controller simultaneously sends, via the signal processing circuit, an initialization signal generated by the CPU to each of the one or more sensors, such that each sensor simultaneously receives the initialization signal, and initialization configuration is simultaneously completed.

Description

Initialization synchronization device, initialization synchronization method, and camera Technical field

The present application relates to the technical field of video processing, and in particular, to an initialization synchronization device, an initialization synchronization method, and a camera.

Background technique

Video stitching technology refers to the technology of stitching video images obtained by several cameras to form a panoramic image. This video stitching technology is usually applied in panoramic cameras.

Traditional panoramic cameras include: multiple cameras and SOC (System On Chip), each camera includes an image sensor, and each image sensor is connected to the SOC. Before each camera acquires an image normally, the SOC sends an initialization configuration instruction to the image sensor of each camera to complete the initialization configuration of the image sensor. After the initial configuration of each image sensor is completed, each image sensor transmits the acquired images to the SOC, and the SOC can stitch the images acquired by different image sensors to form a panoramic image.

However, at present, the SOC is not synchronized to complete the initialization configuration of multiple image sensors, which causes the images acquired by the image sensors to be not synchronized. The SOC stitches the asynchronous images to obtain a poorly displayed panoramic image.

Summary of the Invention

The present application provides an initialization synchronization device, an initialization synchronization method, and a camera, which can initialize multiple sensors in synchronization, so that the images of each image sensor can be output synchronously.

In a first aspect, an initialization synchronization device is provided, including: a central processing unit CPU, one or more controllers, and a signal processing circuit, wherein each of the one or more controllers is coupled to the CPU And the signal processing circuit, the signal processing circuit is connected with one or more sensors outside the initialization synchronization device; the CPU is used to control the signal processing circuit in a first state, and the first state is used to instruct the first controller It is connected to each of the one or more sensors through the signal processing circuit, and the first controller is a controller of the one or more controllers; the first controller is used for the signal processing circuit. When in the first state, the initialization signal generated by the CPU is simultaneously sent to each of the one or more sensors through the signal processing circuit.

In this application, when the CPU controls the signal processing circuit in the first state, the first controller sends the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit at the same time, so that each sensor is It can receive the initialization signals at the same time and complete the initialization configuration at the same time, avoiding the phenomenon that the images acquired by the sensors are not synchronized. If the initialization synchronization device is integrated on the SOC, when the SOC stitches the images acquired by the sensors to obtain a panoramic image, the initialization signals can be sent to each image sensor through the signal processing circuit at the same time, so that the images acquired by each sensor are output synchronously. , So the display effect of the stitched panoramic image is better.

Optionally, the CPU is further configured to control the signal processing circuit in a second state, and the second state is used to instruct each of the one or more controllers to be connected to a sensor through the signal processing circuit; Each controller is configured to send the initialization signal or parameter modification signal generated by the CPU to a sensor corresponding to each controller when the signal processing circuit is in the second state, and the parameter modification signal is used for The initialization parameters recorded in the sensor are adjusted, and the initialization parameters are parameters carried in the initialization signal received by the sensor during the initialization process of each sensor.

In the present application, due to manufacturing errors between the sensors, when the same initialization parameters are configured for each sensor, the display quality (for example, sharpness or color depth, etc.) of the images acquired by each sensor may be different. In order to enable each sensor to obtain an image with higher display quality, the CPU can control the signal processing circuit to be in the second state after the initialization configuration of each sensor is completed by the initialization synchronization device, and each controller can set the parameters generated by the CPU The modification signal is sent to the sensor corresponding to each controller. This parameter modification signal is used to adjust the initialization parameters recorded in the sensor's register to ensure that each sensor can obtain an image with higher display quality. Since the initialization parameters in each sensor can be adjusted by the corresponding controller, it is more efficient to adjust the initialization parameters in each sensor through the initialization synchronization device after the initialization configuration is completed.

Optionally, the signal processing circuit includes: an output processing circuit and an input processing circuit; when the signal processing circuit is in the first state, the first controller passes the output processing circuit to each of the one or more sensors. Sensors send signals generated by the CPU; when the signal processing circuit is in the first state, the first controller receives response signals generated by each of the one or more sensors through the input processing circuit.

In this application, the CPU in the initialization synchronization device may send a signal to each of the one or more sensors through the output processing circuit, and the CPU may also receive the signal generated by each sensor through the input processing circuit, and the CPU performs the signal deal with.

Optionally, the output processing circuit includes: one or more digital selectors, and an output terminal of each digital selector in the one or more digital selectors is connected to a corresponding sensor; when the signal processing circuit is in the first In the state, the input end of each digital selector in the one or more digital selectors is connected to the first controller; when the signal processing circuit is in the second state, the one or more digital selectors The input of each digital selector is connected to the corresponding controller.

Optionally, each digital selector includes a first input port, a second input port, a state selection port, and an output port. The first input port of each digital selector is connected to the first controller. The second input port of the selector is connected to the corresponding controller, the state selection port of each digital selector is connected to the CPU, and the output port of each digital selector is connected to the corresponding sensor; When the state selection port of the digital selector receives an instruction signal sent by the CPU to indicate that the signal processing circuit is in the first state, the first input port is in an open state, and the second input port is in an off state Off state; for each digital selector, when the state selection port of the digital selector receives an instruction signal sent by the CPU to indicate that the signal processing circuit is in the second state, the first input port is in an off state State, the second input port is in an open state.

Optionally, the input processing circuit includes an AND gate logic circuit; and when the signal processing circuit is in the first state, the AND gate logic circuit will receive a response generated by each of the one or more sensors, respectively. After the signal is processed, it is sent to the first controller; when the signal processing circuit is in the second state, each of the one or more controllers receives a response signal generated by a corresponding sensor.

Optionally, the input processing circuit further includes: a signal selector; each of the one or more sensors is connected to an input terminal of the AND logic circuit, and an output terminal of the AND logic circuit is connected to the signal selection. The first input of the signal selector is connected, the output of the signal selector is connected to the first controller, and the first sensor corresponding to the first controller is also connected to the second input of the signal selector; When the signal processing circuit is in the first state, the AND gate logic circuit sends the processed signal to the first controller through the signal selector; when the signal processing circuit is in the second state, the signal selector Sending a response signal generated by the first sensor to the first controller.

Optionally, the initialization synchronization device further includes a connection bus. Each of the one or more controllers is coupled to the CPU and the signal processing circuit through the connection bus. The connection bus is an integrated circuit I2C connection bus. Connect one or more of the buses to the synchronous serial port SSP.

Assuming that the connection bus in this application is an I2C connection bus, the output processing circuit includes: a first output processing circuit for outputting a data signal, and a second output processing circuit for outputting a clock signal; the first output processing The first input port of each digital selector in the circuit is connected to the data port of the first controller, and the second input port of each digital selector in the first output processing unit is connected to the data of the corresponding controller. Port connection, the first input port of each digital selector in the second output processing circuit is connected to the clock port of the first controller, and the second input of each digital selector in the second output processing circuit The port is connected to the clock port of the corresponding controller.

The input processing circuit includes a first input processing circuit for inputting a data signal and a second input processing circuit for inputting a clock signal.

Optionally, the initialization synchronization device further includes: a system register, the system register is respectively connected to the CPU and the signal processing circuit; the CPU controls a register value of the system register to a first value so that the signal processing circuit In the first state; the CPU is further used to control a register value of the system register to a second value, so that the signal processing circuit is in the second state, wherein the first value is different from the second value.

Optionally, the initialization synchronization device further includes one or more input / output IO interfaces, and the signal processing circuit is connected to the one or more sensors one by one through one or more IO interfaces; wherein the signal processing circuit is located in the In the first state, the one or more IO interfaces are connected to the first controller; when the signal processing circuit is in the second state, each controller is connected to a corresponding sensor through an IO interface respectively.

Optionally, the CPU is further configured to: before performing initialization processing on each sensor, send a reset instruction to each sensor to clear initialization parameters in each sensor.

Optionally, the CPU is further configured to: after initializing each sensor, receive image information acquired by each sensor; and determine whether image information acquired by any two sensors is synchronized according to a synchronization signal in the image information; Compensate and adjust the sensor whose image information is not synchronized. As a result, the images acquired by the sensors 200 are synchronized, thereby improving the display effect of the panoramic images formed by subsequent stitching.

According to a second aspect, an initialization synchronization method is provided and applied to an initialization synchronization device. The initialization synchronization device includes a CPU, one or more controllers, and a signal processing circuit. Each of the one or more controllers Each controller is coupled to the CPU and the signal processing circuit. The signal processing circuit is connected to one or more sensors outside the initialization synchronization device. The method includes: the CPU controls the signal processing circuit in a first state, and the first A state for instructing the first controller to connect with each of the one or more sensors through the signal processing circuit, the first controller being one of the one or more controllers; the first control The processor sends an initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit.

Optionally, the method further includes: the CPU controls the signal processing circuit in a second state, and the second state is used to instruct each of the one or more controllers to be connected to a sensor through the signal processing circuit ; Each controller sends the initialization signal or parameter modification signal generated by the CPU to a sensor corresponding to each controller, and the parameter modification signal is used to adjust initialization parameters recorded in the sensor, and the initialization parameter is In the process of initializing each sensor, parameters carried in the initialization signal received by the sensor.

Optionally, the signal processing circuit includes: an output processing circuit and an input processing circuit; after the CPU controls the signal processing circuit in a first state, the method further includes: the first controller sends the signal processing circuit to the one through the output processing circuit. Each of the one or more sensors sends a signal generated by the CPU; the first controller receives a response signal generated by each of the one or more sensors through the input processing circuit.

Optionally, the output processing circuit includes: one or more digital selectors, and an output terminal of each digital selector in the one or more digital selectors is connected to a corresponding sensor; and the first controller processes the data through the output. The circuit sends a signal generated by the CPU to each of the one or more sensors, and includes: each digital selector of the one or more digital selectors controls a respective input terminal connected to the first controller, So that the first controller sends the signals generated by the CPU to one or more sensors through the one or more digital selectors; after the CPU controls the signal processing circuit in a second state, the method further includes: the one Each of the digital selectors or multiple digital selectors controls a respective input terminal connected to a corresponding controller.

Optionally, the input processing circuit includes an AND gate logic circuit, and the first controller receives a response signal generated by each of the one or more sensors through the input processing circuit, and includes: the first controller Receiving a processed signal of a response signal generated by each of the one or more sensors received by the AND logic circuit; after the CPU controls the signal processing circuit to be in a second state, the method further includes : Each of the one or more controllers receives a response signal generated by a corresponding sensor.

Optionally, the input processing circuit further includes: a signal selector, each of the one or more sensors is connected to an input terminal of the AND logic circuit, and an output terminal of the AND logic circuit selects the signal. The first input of the signal selector is connected, the output of the signal selector is connected to the first controller, and the first sensor corresponding to the first controller is also connected to the second input of the signal selector; the first The controller receives a processed signal of the response signal generated by each of the one or more sensors received by the AND logic circuit, and includes: after receiving the AND logic circuit, the first controller receives the processed signal. The signal sent by the signal selector; after the CPU controls the signal processing circuit in the second state, the method further includes: the signal selector sends a response signal generated by the first sensor to the first controller .

Optionally, the initialization synchronization device further includes: a system register, the system register is respectively connected with the CPU and the signal processing circuit, the CPU controls the signal processing circuit in a first state, and includes: a register that the CPU controls the system register The value is a first value, so that the signal processing circuit is in a first state; the CPU controls the signal processing circuit in a second state, including: the CPU controls the register value of the system register to a second value, so that the signal is processed The circuit is in a second state, wherein the first value is different from the second value.

Optionally, the initialization synchronization device further includes one or more input / output IO interfaces, and the signal processing circuit is connected to the one or more sensors one by one through one or more IO interfaces; the CPU controls the signal processing circuit at After the first state, the method further includes: the signal processing circuit controls the one or more IO interfaces to be connected to the first controller; after the CPU controls the signal processing circuit in the second state, the method further includes: The signal processing circuit controls each controller to be connected to a corresponding sensor through an IO interface.

Optionally, the method further includes: before performing initialization processing on each sensor, the CPU sends a reset instruction to each sensor to clear initialization parameters in each sensor.

Optionally, the method further includes: after initializing each sensor, the CPU receives image information acquired by each sensor; and the CPU judges image information acquired by any two sensors according to a synchronization signal in the image information Whether to synchronize; the CPU compensates and adjusts the sensor for which the acquired image information is not synchronized.

It should be noted that, for the principle of the initialization synchronization method in the second aspect, reference may be made to the corresponding part of the initialization synchronization device in the first aspect, which is not repeated in this application.

According to a third aspect, a camera is provided, including: a plurality of cameras and a system-on-chip SOC. The SOC includes: any of the initialization synchronization devices of the first aspect, each camera includes a sensor, and each sensor is associated with the initialization Sync device connection.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a panoramic camera provided by related technologies; FIG.

2 is a block diagram of another panoramic camera provided by the related art;

3 is a block diagram of an initialization synchronization device according to an embodiment of the present application;

FIG. 4 is a block diagram of another initialization synchronization device according to an embodiment of the present application; FIG.

5 is a schematic structural diagram of an output processing circuit according to an embodiment of the present application;

6 is a schematic diagram of signal transmission in the output processing circuit shown in FIG. 5;

7 is a schematic structural diagram of an input processing circuit according to an embodiment of the present application;

FIG. 8 is a schematic diagram of signal transmission in the output processing circuit shown in FIG. 7.

Through the above drawings, the specific embodiments of the present application have been shown, which will be described in more detail later. These drawings and descriptions are not intended to limit the scope of the concept of the present application in any way, but to explain the concepts of the present application to those skilled in the art by referring to specific embodiments.

detailed description

The embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Please refer to FIG. 1. FIG. 1 is a block diagram of a panoramic camera provided by the related art. The panoramic camera includes: SOC01 and a plurality of cameras (not shown in FIG. 1), and each camera may include an image sensor 02. The SOC 01 is internally provided with an I2C (Inter-Integrated Circuit) bus 011 and a plurality of INCK (Input Clock) circuits 012, and each image sensor 02 is connected to the I2C bus 011, and the plurality of INCKs The circuit 012 is connected to the plurality of image sensors 02 in a one-to-one correspondence.

When a panoramic camera acquires a panoramic image, SOC01 needs to send an initialization configuration instruction to all image sensors 02 through the I2C bus 011 and multiple INCK circuits 012. After each image sensor 02 receives the initialization configuration instruction, it performs initialization configuration. After the initial configuration of the image sensor 02 is completed, an image can be acquired and the obtained image is sent to the SOC01, so that the SOC01 stitches the images acquired by different image sensors 02 to obtain a panoramic image.

However, when all image sensors 02 are connected through an I2C bus 011, SOC01 needs to control multiple image sensors 02 one by one for initial configuration, that is, after an image sensor is initialized and configured, SOC01 can be controlled. An image sensor is initialized for configuration. Generally, after the initial configuration of the image sensor 02 is completed, the image sensor 02 immediately sends the acquired image to the SOC 01, and the SOC 01 cannot control multiple image sensors 01 to complete the initial configuration at the same time, so each image sensor 02 The acquired images are not synchronized. SOC01 stitches the asynchronous images, and the obtained panoramic image has a poor display effect.

Please refer to FIG. 2. FIG. 2 is a block diagram of another panoramic camera provided by the related art. The SOC01 in the panoramic camera is provided with multiple I2C buses 011 and multiple INCK circuits 012. The multiple I2C buses 011 and multiple The image sensors 02 are connected one-to-one correspondingly, and the plurality of INCK circuits 012 are connected one-to-one correspondingly to the plurality of image sensors 02. At this time, SOC 01 does not need to control multiple image sensors 02 one by one for initialization and configuration. Although the multiple image sensors 02 can be initialized and configured at the same time, due to the sequential execution of software, SOC 01 needs to be configured one by one through the multiple I2C buses. The initialization image instruction is sent to each image sensor 02, and the time to complete the initialization of each image sensor 02 will still be delayed in order. SOC01 still cannot control multiple image sensors 01 to complete the initialization configuration at the same time, resulting in The images are not synchronized. SOC 01 stitches the asynchronous images, and the resulting panoramic image displays poor results.

Please refer to FIG. 3. FIG. 3 is a block diagram of an initialization synchronization device according to an embodiment of the present application. The initialization synchronization device 100 may include:

A central processing unit (CPU) 10, one or more controllers 20, and a signal processing circuit 30, wherein each of the one or more controllers 20 is coupled to the CPU 10 and the signal processing The circuit 30 is connected to one or more sensors 200 outside the initialization synchronization device. Exemplarily, the sensor 200 in the embodiment of the present application may be an image sensor.

The CPU 10 is used to control the signal processing circuit 30 in a first state, and the first state is used to instruct the first controller 20a to be connected to each of the one or more sensors 200 through the signal processing circuit 30. A controller 20 a is one of the one or more controllers 20.

The first controller 20 a is configured to simultaneously transmit the initialization signal generated by the CPU 10 to each of the one or more sensors 200 through the signal processing circuit 30 when the signal processing circuit 30 is in the first state.

Exemplarily, the signal processing circuit 30 has multiple input and output interfaces, wherein the multiple input and output interfaces are connected to the sensors one by one. When the signal processing circuit 30 is in the first state, the multiple input and output interfaces of the signal processing circuit 30 are all Connected to the first controller 20a, when the CPU 10 generates an initialization signal, the initialization signal is sent to each sensor 200 through the first controller 20a through multiple input and output interfaces at the same time, and each sensor 200 receives the first controller After the initialization signal sent by 20a, the initialization parameters (for example, image resolution, refresh rate, exposure time, and gain, etc.) carried in the initialization signal can be written into a register in the sensor 200. After the initialization parameters are written, , The sensor 200 can complete the initial configuration. Since the first controller 20a sends an initialization signal to each of the one or more sensors 200 at the same time through the signal processing circuit 30, each sensor 200 can simultaneously receive the initialization signal and complete the initialization configuration at the same time. The phenomenon that the images acquired by the sensors 200 are not synchronized is avoided. If the initialization synchronization device 100 is integrated on the SOC, when the SOC stitches the images acquired by each sensor 200 to obtain a panoramic image, the initialization signal can be sent to each image sensor 200 through the signal processing circuit 30 at the same time, so that each sensor 200 acquires The images are output synchronously, so the panoramic image obtained by stitching displays better.

Further, the CPU 10 is also used to control the signal processing circuit 30 in a second state, and the second state is used to instruct each of the one or more controllers 20 to communicate with the sensor 200 through the signal processing circuit 30 Connected. Each controller 20 is configured to send an initialization signal generated by the CPU 10 to the sensor 200 corresponding to each controller 20 when the signal processing circuit 30 is in the second state.

For example, when the signal processing circuit 30 is in the second state, each sensor 200 is connected to the CPU 10 through its own controller 20, and the CPU 10 can independently control each sensor 200.

In the embodiment of the present application, after the initialization synchronization device 100 completes the initial configuration of each sensor 200, each sensor 200 can acquire an image, but due to manufacturing errors between each sensor 200, when the same configuration is performed for each sensor 200, When the parameters are initialized, there will be differences in the display quality (such as sharpness or color depth) of the images acquired by each sensor 200. In order to enable each sensor 200 to obtain an image with higher display quality, after the initialization configuration of each sensor 200 is completed by the initialization synchronization device 100, the CPU 10 controls the signal processing circuit 30 to be in a second state, and each controller 20 can The parameter modification signal generated by the CPU 10 is sent to the sensor 200 corresponding to each controller 20. This parameter modification signal is used to adjust the initialization parameters recorded in the register of the sensor 200 to ensure that each sensor 200 can obtain an image with a higher display quality. Since the initialization parameters in each sensor 200 can be adjusted by the corresponding controller 20, after the initialization configuration is completed, the initialization parameters in each sensor 200 are adjusted by the initialization synchronization device 100 with high efficiency.

In an optional implementation manner, as shown in FIG. 4, FIG. 4 is a block diagram of another initialization synchronization device provided by an embodiment of the present application. The initialization synchronization device 100 may further include a system register 40, which is connected to the CPU 10 and the signal processing circuit 30, respectively. The CPU 10 is used to control the register value of the system register 40 to a first value so that the signal processing circuit 30 is in the first state; the CPU 10 is also used to control the register value of the system register 40 to a second value so that the signal The processing circuit 30 is in a second state. The first value is different from the second value. For example, the first value may be 1 and the second value may be 0. It should be noted that FIG. 4 uses the register value of the CPU 10 control system register 40 to control the signal processing circuit 30 in the first state or the second state. In another optional implementation manner, the CPU 10 may The direct control signal processing circuit 30 is in a first state or a second state, which is not specifically limited in the embodiment of the present application.

Optionally, the initialization synchronization device 100 may further include one or more input / output (IO) interfaces, and the signal processing circuit 30 is connected to one or more sensors 200 one by one through one or more IO interfaces. It should be noted that FIG. 4 is only a schematic diagram schematically showing an IO general interface 50, and the IO general interface 50 includes one or more IO interfaces connected to the one or more sensors 200 one by one. In the embodiment of the present application, when the signal processing circuit 30 is in the first state, one or more IO interfaces are connected to the first controller 20a, so that the first controller 20a and each of the one or more sensors 200 Sensor connection; when the signal processing circuit 30 is in the second state, each controller 20 is connected to the corresponding sensor 200 through an IO interface, so that each of the one or more controllers 20 controls 20 and the corresponding sensor 200 connection.

In the embodiment of the present application, the initialization synchronization device 100 further includes a connection bus 60. Each of the one or more controllers 20 is coupled to the CPU 10 and the signal processing circuit 30 through the connection bus 60. The signal processing circuit 30 and the IO general interface 50 may also be connected through the connection bus 60. . Optionally, the connection bus 60 may be one or more of an integrated circuit (Inter-Integrated Circuit) (I2C) connection bus and a synchronous serial port (Synchronous Serial Port (SSP) connection bus). It should be noted that the I2C connection bus may include data traces for transmitting data signals and clock traces for transmitting clock signals; the SSP connection bus may include three types of signal traces: Input and output data traces (also known as bidirectional data traces), clock traces used to transmit clock signals, and chip select traces used to transmit chip select signals; this SSP connection bus can also contain four types of signal traces : Input data traces for transmitting data signals, output data traces for transmitting data signals, clock traces for transmitting clock signals, and chip selection traces for transmitting chip select signals. It should be understood that the embodiments of the present application divide the initialization synchronization device from the perspective of functions. In actual implementation, there may be another division manner, for example, multiple modules may be combined or integrated into another system. The coupling between the various modules can be achieved through some interfaces. These interfaces are usually electrical communication interfaces, but it is not excluded that they may be mechanical interfaces or other forms of interfaces. Therefore, the modules described as separate components may or may not be physically separated, and may be located in one place or distributed to different locations on the same or different devices. In various embodiments of the present application, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices.

Optionally, as shown in FIG. 4, the signal processing circuit 30 in the initialization synchronization device 100 includes: an output processing circuit 31 and an input processing circuit 32.

When the signal processing circuit 30 is in the first state, the first controller 20a sends a signal generated by the CPU 10 to each of the one or more sensors 200 through the output processing circuit 31. For example, the signal generated by the CPU 10 may be Is an initialization signal; the first controller 20a receives a response signal generated by each of the one or more sensors 200 through the input processing circuit 32, for example, the response signal of each sensor 200 is Initialization response signal generated after receiving the initialization signal.

When the signal processing circuit 30 is in the second state, each of the one or more controllers 20 sends a signal generated by the CPU 10 to the corresponding sensor 200 through the output processing circuit 31, for example, the signal generated by the CPU 10 Signals can be modified for the parameters; each of the one or more controllers 20 receives the response signal of the corresponding sensor 200 through the input processing circuit 32, for example, the response signal of each sensor 20 is the signal received by the sensor 200 Parameter modification response signal generated after parameter modification signal.

It should be noted that after receiving the response signal sent by the sensor 200, each controller 20 in the embodiment of the present application sends the response signal to the CPU 10, and the CPU 10 performs signal processing.

Please refer to FIG. 5, which is a schematic structural diagram of an output processing circuit 31 according to an embodiment of the present application. The output processing circuit includes one or more digital selectors 311. In the embodiment of the present application, at least one of the digital selectors 311 corresponds to a sensor and a controller. The output terminals of the one or more digital selectors 311 are connected to corresponding sensors.

For example, as shown in FIG. 6, FIG. 6 is a schematic diagram of signal transmission in the output processing circuit 31 shown in FIG. 5. When the signal processing circuit is in the first state, the signal transmission direction in the output processing circuit 31 is the direction where the solid line in FIG. 6 is located, and the input port of each of the one or more digital selectors 311 Connected to the first controller, so that the first controller can send signals generated by the CPU to each of the one or more sensors at the same time; when the signal processing circuit is in the second state, the signal in the output processing circuit 31 is transmitted The direction is the direction where the dotted line in FIG. 6 is located. The input of each digital selector 311 in the one or more digital selectors 311 is connected to the corresponding controller, so that each of the one or more controllers controls The device can send signals generated by the CPU to the corresponding sensors.

Optionally, each digital selector 311 includes: a first input port T1, a second input port T2, a state selection port S, and an output port Z. A first input port T1 of each digital selector 311 is connected to a first controller; a second input port T2 of each digital selector 311 is connected to a corresponding controller; a state selection port S of each digital selector 311 Connected to the CPU. In an optional case, the state selection port S of each digital selector 311 is connected to the CPU through the system control register, that is, the state selection port S is connected to the system control register, and the system control register is connected to the CPU. ; The output port Z of each digital selector 311 is connected to the corresponding sensor.

For each digital selector 311, when the state selection port S of the digital selector 311 receives an instruction signal sent by the CPU to indicate that the signal processing circuit is in the first state, the first input port T1 of the digital selector 311 In the on state, the second input port T2 of the digital selector is in the off state, so that each of the one or more sensors is connected to the first controller through the output processing circuit 31.

For each digital selector 311, when the state selection port S of the digital selector 311 receives an instruction signal sent by the CPU to indicate that the signal processing circuit is in the second state, the first input port T1 of the digital selector 311 In the off state, the second input port T2 of the digital selector is on, so that each of the one or more sensors is connected to the corresponding controller through the output processing circuit 31.

Assuming that the connection bus in the initialization synchronization device in the embodiment of the present application is an I2C connection bus, the output processing circuit 31 may include a first output processing circuit 31a for outputting a data signal, and a second output processing circuit 31a for outputting a clock signal. The output processing circuit 31b. The data line in the I2C connection bus is connected to the first output processing circuit 31a, and the clock line in the I2C connection bus is connected to the second output processing circuit 31b. Each of the first output processing circuit 31a and the second output processing circuit 31b may include: one or more signal selectors 311. The first input terminal T1 of each digital selector 311 in the first output processing circuit 31a is connected to the data port of the first controller. The first output processing unit 31a of each digital selector 311 The two input ports T2 are connected to the data ports of the corresponding controller; the first input port T1 of each digital selector 311 in the second output processing circuit 31b is connected to the clock port of the first controller, and the second output A second input port T2 of each digital selector 311 in the processing circuit 31b is connected to a clock port of a corresponding controller.

Please refer to FIG. 7, which is a schematic structural diagram of an input processing circuit 32 according to an embodiment of the present application. The input processing circuit 32 may include an AND gate logic circuit 321. For example, as shown in FIG. 8, FIG. 8 is a schematic diagram of signal transmission in the output processing circuit 31 shown in FIG. 7. When the signal processing circuit is in the first state, the signal transmission direction in the input processing circuit 32 is the direction where the solid line in FIG. 8 is located, and each of the one or more sensors passes the response signal generated by each of the sensors through the AND gate logic circuit. 321 is sent to the first controller after processing; when the signal processing circuit is in the second state, the signal transmission direction in the input processing circuit 32 is the direction where the dotted line in FIG. 8 is located, and each of the one or more controllers Receive the response signal generated by the corresponding sensor.

Optionally, the input processing circuit 32 may further include a digital selector 322. In the embodiment of the present application, each of the one or more sensors is connected to the input terminal of the AND logic circuit 321; the output terminal of the AND logic circuit 321 is connected to the first input terminal of the signal selector 322; An output terminal of the signal selector 322 is connected to a first controller; a first sensor corresponding to the first controller is also connected to a second input terminal of the signal selector 322. As shown in FIG. 8, when the signal processing circuit is in the first state, the AND logic circuit 322 sends the processed signal to the first controller through the signal selector 322; when the signal processing circuit is in the second state, the signal selection The transmitter 322 sends a response signal generated by the first sensor to the first controller.

Assuming that the connection bus in the initialization synchronization device in the embodiment of the present application is an I2C connection bus, the input processing circuit 32 may include a first input processing circuit 32a for inputting a data signal, and a second input processing circuit for inputting a clock signal. The input processing circuit 32b. The data line in the I2C connection bus is connected to the first input processing circuit 32a, and the clock line in the I2C connection bus is connected to the second input processing circuit 32b. The first input processing circuit 32a and the second input processing circuit 32b each include an AND logic circuit 321 and a signal selector 322. The connection mode between the AND logic circuit 321 and the signal selector 322 is the same as that of the first input processing circuit. Both 32a and the second input processing circuit 32b are the same. The following embodiments schematically illustrate specific connection modes between the AND logic circuit 321 and the signal selector 322:

For example, the AND logic circuit 321 has an output port Z and one or more input ports (T0, T1, T2, ..., Tn) corresponding to one or more sensors, and the digital selector 322 has a first An input port T1, a second input port T2, a state selection port S, and an output port Z. Each of the one or more sensors is connected to a corresponding input port in the AND logic circuit 321; the output port Z of the AND logic circuit 321 is connected to the first input port T1 of the digital selector; the one or more A first sensor of the plurality of sensors is connected to the second input port T2 of the digital selector 322; an output port Z of the digital selector 322 is connected to the first controller; each of the one or more sensors except the first sensor The sensor is directly connected to the corresponding controller; the state selection port S of the digital selector 322 is connected to the CPU. For example, the state selection port S of the digital selector 322 is connected to the system control register, which needs to be connected to the CPU.

When the state selection port of the digital selector 322 receives an instruction signal sent by the CPU to indicate that the signal processing circuit is in the first state, the first input port T1 of the digital selector 322 is in an open state. The second input port T2 is in an off state. At this time, the response signals generated by each of the one or more sensors are processed by the AND logic circuit 321 and then sent to the first sensor. It should be noted that when the signal processing circuit is in the first state, the CPU can control the connection between the signal processing circuit and each of the one or more controllers except the first controller to be interrupted. At this time, one or Although the response signals generated by each of the multiple sensors except the first sensor can be sent to the corresponding controller, these controllers will not send the received response signals to the CPU, so the CPU can only receive To the signal sent by the first controller after being processed by the AND logic circuit, the CPU only needs to process the signal sent by the first controller.

When the state selection port of the digital selector 322 receives an instruction signal sent by the CPU to indicate that the signal processing circuit is in the second state, the second input port T2 of the digital selector 322 is in an open state. The first input port T1 is in an off state. At this time, the response signal generated by the first sensor may be sent to the first controller through the digital selector 322, and the response signal generated by each of the one or more sensors except the first sensor is directly sent to the corresponding control. Device. It should be noted that, when the signal processing circuit is in the second state, the CPU needs to control that it can be normally connected with each of the one or more controllers. At this time, each of the one or more sensors The generated response signals are sent to the CPU through the corresponding controller, so that the CPU can process the signals sent by each controller.

In an optional implementation manner, the output port of the digital selector 322 in the first input processing circuit 32a is connected to the data port of the first controller; the output port of the digital selector 322 in the second input processing circuit 32b is connected to the data port of the first controller. A controller's clock port is connected. Each of the one or more sensors except the first sensor is respectively connected to a data port and a clock port of a corresponding controller.

In the embodiment of the present application, as shown in FIG. 3 or FIG. 4, the CPU 10 is further configured to: before performing initialization processing on each sensor 200, send a reset instruction to each sensor 200 to clear each sensor 200. The registers store the initialization parameters. It should be noted that when the CPU 10 sends a reset instruction to each sensor 200, the CPU 10 can control the signal processing circuit 30 to be in the first state or the signal processing circuit 30 to be in the second state. This embodiment of the present application does not address this. Be limited.

In an optional implementation manner, because there are some manufacturing errors in each sensor 200, after the initialization synchronization device 100 performs the initialization processing on each sensor 200, each sensor 200 may obtain a different time period. Images are transmitted to the initialization synchronization device 100. Generally, if the time difference between the two sensors 200 transmitting the acquired images to the initialization synchronization device 100 is within 0.15 microseconds, the image information obtained by the two sensors may be considered to be synchronized . In the embodiment of the present application, in order to further improve the display effect of the subsequent synthesized mosaic image, the CPU 10 is further configured to: after performing initialization processing 30 on each sensor 200, receive image information acquired by each sensor 200; The synchronization signal in the image information determines whether the image information acquired by any two sensors 200 is synchronized; and the compensation adjustment is performed for the sensor 200 whose image information is not synchronized. As a result, the images acquired by the sensors 200 are synchronized, thereby improving the display effect of the panoramic images formed by subsequent stitching.

In summary, the initialization synchronization device provided in the embodiment of the present application includes a CPU, one or more controllers, and a signal processing circuit. When the CPU controls the signal processing circuit in the first state, the first controller sends the initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit at the same time, so that each sensor can receive the initialization at the same time Signal and complete the initial configuration at the same time, avoiding the phenomenon that the images acquired by the sensors are not synchronized. If the initialization synchronization device is integrated on the SOC, when the SOC stitches the images obtained by the sensors to obtain a panoramic image, the initialization signals can be sent to each image sensor through the signal processing circuit at the same time, so that the images obtained by each sensor are output synchronously , So the display effect of the stitched panoramic image is better. Further, the CPU can control the signal processing circuit to be in a second state, and each controller can send a parameter modification signal generated by the CPU to a sensor corresponding to each controller, and the parameter modification signal is used to register a sensor. The initialization parameters recorded in the camera are adjusted to ensure that each sensor can obtain images with higher display quality. Since the initialization parameters in each sensor can be adjusted by the corresponding controller, it is more efficient to adjust the initialization parameters in each sensor through the initialization synchronization device after the initialization configuration is completed.

An embodiment of the present application further provides an initialization synchronization method. The method is applied to the initialization synchronization device shown in FIG. 3 or 4. The method may include:

Step A1: The CPU controls the signal processing circuit in a first state. The first state is used to instruct the first controller to connect with each of the one or more sensors through the signal processing circuit. The first controller is one or more controllers. One of the controllers.

Step B1: The first controller sends an initialization signal generated by the CPU to each of the one or more sensors through a signal processing circuit.

Optionally, the initialization synchronization method may further include:

Step A2: The CPU controls the signal processing circuit in a second state, and the second state is used to instruct each of the one or more controllers to be connected to a sensor through the signal processing circuit;

Step B2: Each controller sends an initialization signal or a parameter modification signal generated by the CPU to a sensor corresponding to each controller.

Optionally, after the CPU controls the signal processing circuit to be in the first state, the initialization synchronization method may further include:

Step A3: The first controller sends a signal generated by the CPU to each of the one or more sensors through an output processing circuit.

Step B3: The first controller receives a response signal generated by each of the one or more sensors through an input processing circuit.

Optionally, the foregoing step A3 may include: each input of one or more digital selectors controls a respective input end of the digital selector to be connected to the first controller, so that the first controller passes one or more digital selectors Sends signals generated by the CPU to one or more sensors.

After the CPU control signal processing circuit is in the second state, the initialization synchronization method may further include: each digital selector of one or more digital selectors controls a respective input terminal to be connected to a corresponding controller.

Optionally, the above step B3 may include: the first controller receives a processed signal of a response signal generated by each of the one or more sensors received through an AND gate logic circuit.

After the CPU control signal processing circuit is in the second state, the initialization synchronization method may further include: each of the one or more controllers receives a response signal generated by a corresponding sensor.

Optionally, the above step B3 specifically includes: the first controller receives a signal sent by the AND logic circuit through the processed signal through a signal selector.

After the CPU controls the signal processing circuit in the second state, the initialization synchronization method may further include: the signal selector sends a response signal generated by the first sensor to the first controller.

Optionally, after the CPU controls the signal processing circuit in the first state, the initialization synchronization method may further include: the signal processing circuit controls one or more IO interfaces to be connected to the first controller;

After the CPU controls the signal processing circuit in the second state, the initialization synchronization method may further include: the signal processing circuit controls each controller to be connected to a corresponding sensor through an IO interface respectively.

Optionally, the CPU control signal processing circuit in the above step A1 is in the first state, which may include: the register value of the CPU control system register is the first value, so that the signal processing circuit is in the first state.

Optionally, the CPU control signal processing circuit in the above step A2 is in the second state, which may include: the register value of the CPU control system register is the second value, so that the signal processing circuit is in the second state, where the first value and The second value is different.

Optionally, the initialization synchronization method may further include: before performing initialization processing on each sensor, the CPU sends a reset instruction to each sensor to clear the initialization parameters in each sensor.

Optionally, the initialization synchronization method may further include:

Step A4: After initializing each sensor, the CPU receives image information acquired by each sensor.

Step B4: The CPU determines whether the image information acquired by any two sensors is synchronized according to the synchronization signal in the image information.

Step C4: The CPU compensates and adjusts the sensor for which the acquired image information is not synchronized.

It should be noted that, for the principle of the foregoing initialization synchronization method, reference may be made to corresponding parts in the foregoing embodiment of the initialization synchronization device, and details are not described herein again.

An embodiment of the present application further provides a camera. The camera may be a panoramic camera. The camera may include a plurality of cameras and a SOC. The SOC includes an initialization synchronization device shown in FIG. 3 or 4. Each camera includes a sensor. The sensor may be an image sensor, and each sensor is connected to an initialization synchronization device.

The above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection of the present application. Within range.

Claims (23)

1. An initialization synchronization device, comprising: a central processing unit CPU, one or more controllers, and a signal processing circuit, wherein each of the one or more controllers is coupled to the CPU And the signal processing circuit, the signal processing circuit is connected to one or more sensors outside the initialization synchronization device;

   The CPU is configured to control the signal processing circuit in a first state, and the first state is used to instruct a first controller to connect with each of the one or more sensors through the signal processing circuit, so that The first controller is one of the one or more controllers;

   The first controller is configured to simultaneously send an initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit when the signal processing circuit is in the first state. Sensors.
2. The initialization synchronization device according to claim 1, wherein:

   The CPU is further configured to control the signal processing circuit in a second state, and the second state is used to instruct each of the one or more controllers to be connected to a sensor through the signal processing circuit. ;

   Each controller is configured to send the initialization signal or the parameter modification signal generated by the CPU to a sensor corresponding to each controller when the signal processing circuit is in the second state, and The parameter modification signal is used to adjust initialization parameters recorded in the sensors. The initialization parameters are parameters carried in the initialization signals received by the sensors during the initialization process of each of the sensors.
3. The initialization synchronization device according to claim 2, wherein the signal processing circuit comprises: an output processing circuit and an input processing circuit;

   When the signal processing circuit is in the first state, the first controller sends a signal generated by the CPU to each of the one or more sensors through the output processing circuit;

   When the signal processing circuit is in the first state, the first controller receives a response signal generated by each of the one or more sensors through the input processing circuit.
4. The initialization synchronization device according to claim 3, wherein:

   The output processing circuit includes: one or more digital selectors, and an output terminal of each of the one or more digital selectors is connected to a corresponding sensor;

   When the signal processing circuit is in the first state, an input terminal of each digital selector in the one or more digital selectors is connected to the first controller;

   When the signal processing circuit is in the second state, an input terminal of each digital selector in the one or more digital selectors is connected to a corresponding controller.
5. The initialization synchronization device according to claim 4, wherein:

   Each of the digital selectors includes a first input port, a second input port, a state selection port, and an output port. The first input port of each of the digital selectors is connected to the first controller. A second input port of the digital selector is connected to a corresponding controller, a state selection port of each digital selector is connected to the CPU, and an output port of each digital selector is connected to a corresponding sensor. ;

   Wherein, for each of the digital selectors, when a state selection port of the digital selector receives an instruction signal sent by the CPU and used to indicate that the signal processing circuit is in the first state, the first An input port is in an on state, and the second input port is in an off state;

   For each of the digital selectors, when the state selection port of the digital selector receives an instruction signal sent by the CPU to indicate that the signal processing circuit is in the second state, the first input The port is in an off state, and the second input port is in an on state.
6. The initialization synchronization device according to claim 5, wherein:

   The output processing circuit includes a first output processing circuit for outputting a data signal and a second output processing circuit for outputting a clock signal;

   A first input port of each of the digital selectors in the first output processing circuit is connected to a data port of the first controller, and each of the digital selectors in the first output processing unit The second input port is connected to the data port of the corresponding controller,

   A first input port of each of the digital selectors in the second output processing circuit is connected to a clock port of the first controller, and each of the digital selectors in the second output processing circuit The second input port is connected to the clock port of the corresponding controller.
7. The initialization synchronization device according to claim 3, wherein:

   The input processing circuit includes an AND gate logic circuit;

   When the signal processing circuit is in the first state, the AND gate logic circuit processes the response signal generated by each of the one or more sensors received and sends it to the first Controller

   When the signal processing circuit is in the second state, each of the one or more controllers receives a response signal generated by a corresponding sensor.
8. The initialization synchronization device according to claim 7, wherein:

   The input processing circuit further includes: a signal selector;

   Each of the one or more sensors is connected to an input of the AND logic circuit, and an output of the AND logic circuit is connected to a first input of the signal selector, and the signal An output terminal of the selector is connected to the first controller, and a first sensor corresponding to the first controller is also connected to a second input terminal of the signal selector;

   Wherein, when the signal processing circuit is in the first state, the AND gate logic circuit sends the processed signal to the first controller through the signal selector;

   When the signal processing circuit is in the second state, the signal selector sends a response signal generated by the first sensor to the first controller.
9. The initialization synchronization device according to claim 7, wherein:

   The input processing circuit includes a first input processing circuit for inputting a data signal and a second input processing circuit for inputting a clock signal.
10. The initialization synchronization device according to any one of claims 2 to 9, wherein the initialization synchronization device further comprises: a system register, the system register being respectively connected to the CPU and the signal processing circuit;

    A register value used by the CPU to control the system register to a first value, so that the signal processing circuit is in the first state;

    The CPU is further configured to control a register value of the system register to a second value, so that the signal processing circuit is in the second state, wherein the first value and the second value are different.
11. The initialization synchronization device according to any one of claims 2 to 9, wherein the initialization synchronization device further comprises one or more input / output IO interfaces, and the signal processing circuit communicates with the One or more sensors are connected one by one;

    Wherein, when the signal processing circuit is in the first state, the one or more IO interfaces are connected to the first controller;

    When the signal processing circuit is in the second state, each of the controllers is respectively connected to a corresponding sensor through an IO interface.
12. The initialization synchronization device according to any one of claims 1 to 9, wherein:

    The CPU is further configured to: before performing initialization processing on each of the sensors, send a reset instruction to each of the sensors to clear initialization parameters in each of the sensors.
13. The initialization synchronization device according to any one of claims 1 to 9, wherein the CPU is further configured to:

    After performing initialization processing on each of the sensors, receiving image information acquired by each of the sensors;

    Judging whether the image information acquired by any two sensors is synchronized according to the synchronization signal in the image information;

    Compensate and adjust the sensor whose image information is not synchronized.
14. An initialization synchronization method is characterized in that it is applied to an initialization synchronization device, and the initialization synchronization device includes a CPU, one or more controllers, and a signal processing circuit, wherein each of the one or more controllers Each controller is coupled to the CPU and the signal processing circuit, and the signal processing circuit is connected to one or more sensors outside the initialization synchronization device, and the method includes:

    The CPU controls the signal processing circuit to be in a first state, and the first state is used to instruct a first controller to connect with each of the one or more sensors through the signal processing circuit, and the first The controller is one of the one or more controllers;

    The first controller sends an initialization signal generated by the CPU to each of the one or more sensors through the signal processing circuit.
15. The method according to claim 14, further comprising:

    The CPU controls the signal processing circuit to be in a second state, and the second state is used to instruct each of the one or more controllers to be connected to a sensor through the signal processing circuit;

    Each controller sends the initialization signal or parameter modification signal generated by the CPU to a sensor corresponding to each controller, and the parameter modification signal is used to adjust initialization parameters recorded in the sensor, The initialization parameter is a parameter carried in an initialization signal received by the sensor during an initialization process of each of the sensors.
16. The method according to claim 15, wherein the signal processing circuit comprises: an output processing circuit and an input processing circuit;

    After the CPU controls the signal processing circuit to be in a first state, the method further includes:

    Sending, by the first controller, a signal generated by the CPU to each of the one or more sensors through the output processing circuit;

    The first controller receives a response signal generated by each of the one or more sensors through the input processing circuit.
17. The method according to claim 16, wherein the output processing circuit comprises: one or more digital selectors, an output terminal of each digital selector in the one or more digital selectors and a corresponding sensor connection;

    The sending, by the first controller, a signal generated by the CPU to each of the one or more sensors through the output processing circuit includes:

    An input terminal for controlling each digital selector in the one or more digital selectors is connected to the first controller, so that the first controller provides one or more digital selectors to the one or more digital selectors through the one or more digital selectors. Multiple sensors sending signals generated by the CPU;

    After the CPU controls the signal processing circuit to be in a second state, the method further includes:

    A respective input terminal for controlling each of the one or more digital selectors is connected to a corresponding controller.
18. The method according to claim 16, wherein the input processing circuit comprises: an AND gate logic circuit;

    The receiving, by the first controller through the input processing circuit, a response signal generated by each of the one or more sensors includes:

    Receiving, by the first controller, a processed signal of a response signal generated by each of the one or more sensors received through the AND logic circuit;

    After the CPU controls the signal processing circuit to be in a second state, the method further includes:

    Each of the one or more controllers receives a response signal generated by a corresponding sensor.
19. The method according to any one of claims 15 to 18, wherein the initialization synchronization device further comprises: a system register, the system register is respectively connected to the CPU and the signal processing circuit,

    The CPU controlling the signal processing circuit to be in a first state includes:

    The CPU controls a register value of the system register to a first value, so that the signal processing circuit is in a first state;

    The CPU controls the signal processing circuit to be in a second state, including:

    The CPU controls a register value of the system register to a second value, so that the signal processing circuit is in a second state, wherein the first value and the second value are different.
20. The method according to any one of claims 15 to 18, wherein the initialization synchronization device further comprises one or more input / output IO interfaces, and the signal processing circuit communicates with the one or more IO interfaces through one or more IO interfaces. Multiple sensors are connected one by one;

    After the CPU controls the signal processing circuit to be in a first state, the method further includes:

    Connecting the one or more IO interfaces to the first controller through the signal processing circuit;

    After the CPU controls the signal processing circuit to be in a second state, the method further includes:

    Each of the controllers is connected to a corresponding sensor through an IO interface through the signal processing circuit.
21. The method according to any one of claims 15 to 18, wherein the method further comprises:

    Before performing initialization processing on each of the sensors, the CPU sends a reset instruction to each of the sensors to clear initialization parameters in each of the sensors.
22. The method according to any one of claims 15 to 18, wherein the method further comprises:

    After performing initialization processing on each of the sensors, the CPU receives image information acquired by each of the sensors;

    Determining, by the CPU, whether the image information acquired by any two sensors is synchronized according to a synchronization signal in the image information;

    The CPU compensates and adjusts the sensor for which the acquired image information is not synchronized.
23. A camera, comprising: a plurality of cameras and a system-on-chip SOC, the SOC includes: the initialization synchronization device according to any one of claims 1 to 13, each of the cameras includes a sensor, and each The sensors are connected to the initialization synchronization device.

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