WO2018157569A1

WO2018157569A1 - Memory control method and device

Info

Publication number: WO2018157569A1
Application number: PCT/CN2017/099101
Authority: WO
Inventors: 王增强; 杨谊峰
Original assignee: 华为技术有限公司
Priority date: 2017-02-28
Filing date: 2017-08-25
Publication date: 2018-09-07
Also published as: CN108509359A

Abstract

A memory control method and device, for use in reducing wiring difficulty and improving signal quality when controlling SDRAMs belonging to one RANK to execute an access instruction. The method comprises: generating an access instruction for two SDRAMs according to instruction requirements (S601), the two SDRAMs being fixed to two sides of a single board in a mirrored manner; generating two chip select signals according to the access instruction (S602), a first chip select signal in the two chip select signals being used for enabling a first SDRAM in the two SDRAMs, and a second chip select signal in the two chip select signals being used for enabling a second SDRAM in the two SDRAMs; making at least one chip select signal in the two chip select signals valid according to mode parameters (S603), the mode parameters being used for indicating the validity of each chip select signal in the two chip select signals; and outputting the access instruction and the first chip select signal to the first SDRAM, and outputting the access instruction and the second chip select signal to the second SDRAM (S604).

Description

Memory control method and device

The present application claims priority to Chinese Patent Application No. JP-A No. No. No. No. No. No. No. No. No. No. No. No. No. in.

Technical field

The present application relates to the field of storage technologies, and in particular, to a method and an apparatus for controlling a memory.

Background technique

In the field of storage technology, Synchronous Dynamic Random Access Memory (SDRAM) has become the first choice of many processor chips due to its high speed, high integration and low cost.

When the processor docks the SDRAM, the System On Chip (SOC) chip in the processor realizes access to the SDRAM by transmitting an access instruction conforming to the Joint Electron Device Engineering Council (JEDEC) protocol. Whether the SDRAM performs the access execution after receiving the access instruction is mainly indicated by a Chip Select (CS) signal for enabling the SDRAM. When the chip select signal received by the SDRAM is valid, the SDRAM is enabled, and the SDRAM performs the received access command; when the chip select signal received by the SDRAM is invalid, the SDRAM does not execute the received access command. Typically, a chip select signal can be used to enable SDRAM belonging to the same memory region (ie RANK). SDRAMs belonging to the same RANK can simultaneously execute access instructions and physically share address lines and control lines.

In the prior art, when multiple SDRAMs belonging to the same RANK are enabled, all SDRAMs are usually integrated on one side of the board when wiring on a Printed Circuit Board (also referred to as a single board). The signal is selected to enable all of the SDRAM, i.e., the chip select signal is used to indicate whether the SDRAM is executing the received access command. Since the SDRAMs belonging to the same RANK physically share the address lines and the control lines, when the SDRAMs belonging to the same RANK are arranged on the same side of the board, the wiring difficulty is increased, and crosstalk or noise between the signals is also Causes a drop in signal quality.

In summary, the existing memory control method has the problems of high wiring difficulty and poor signal quality.

Summary of the invention

The present application provides a memory control method and apparatus for reducing wiring difficulty and improving signal quality when controlling access commands of a plurality of SDRAMs belonging to the same RANK.

In a first aspect, the present application provides a method for controlling a memory, the method comprising: generating an access instruction for two SDRAMs mirrored on both sides of a board according to an instruction requirement; generating two chip selections according to the access instruction a signal; causing at least one of the two chip select signals to be valid according to the mode parameter; outputting the access command and the first chip select signal to the first SDRAM of the two SDRAMs, and outputting the access command and the second chip select signal To the second SDRAM of the two SDRAMs.

The first chip select signal of the two chip select signals is used to enable the first SDRAM, the second chip select signal is used to enable the second SDRAM, and the mode parameter is used to indicate each of the two chip select signals. The validity of the signal.

In the method provided by the first aspect, since the first SDRAM and the second SDRAM are mirror-fixed on both sides of the single board, the wiring manner is easier to implement when wiring the first SDRAM and the second SDRAM. This is because: by The first SDRAM and the second SDRAM are mirrored and fixed on both sides of the board, and the first SDRAM and the second SDRAM can share the address signal link, and each SDRAM is separately routed on the single board in the prior art. Compared with the method, the wiring area and the number of wiring layers are reduced, thereby reducing the wiring difficulty. At the same time, since the number of wirings on the single board, the wiring area, and the number of wiring layers are reduced during wiring, the memory control method provided by the first aspect can reduce crosstalk and noise between signals due to single board wiring, and improve signals. quality.

Furthermore, in the method provided by the first aspect, at least one of the two chip select signals is valid according to the mode parameter, and the access command and the first chip select signal are output to the first SDRAM, the access command and The second chip select signal is output to the second SDRAM. Therefore, when the first SDRAM is required to execute an access instruction that has strict requirements on the line order, the first chip select signal is valid and the second chip select signal is invalid by the indication of the mode parameter, so that the first SDRAM can perform the single SDRAM separately. Accessing the instruction, or when the second SDRAM is required to execute the access instruction having strict requirements on the line sequence, the first chip selection signal is invalid and the second chip selection signal is valid by the indication of the mode parameter, so that the second SDRAM can be separately Executing the access instruction; when the first SDRAM and the second SDRAM are required to simultaneously execute an access instruction that is not strictly required for the line sequence, the first chip selection signal and the second chip selection signal are both valid by the indication of the mode parameter, thereby The first SDRAM and the second SDRAM are enabled to execute the access instruction at the same time.

In one possible design, the access instruction can be a Mode Register Set (MRS) instruction or a data read and write instruction.

When the access instruction is an MRS instruction, the first SDRAM can be controlled to execute the MRS instruction by outputting the MRS instruction and the first chip selection signal to the first SDRAM, and the MRS instruction and the second chip selection signal are outputted to the second SDRAM. The second SDRAM executes the MRS instruction; when the access instruction is the data read/write instruction, the first SDRAM can be controlled to execute the data read/write instruction by outputting the data read/write instruction and the first chip select signal to the first SDRAM, and pass to the second SDRAM. The output data read/write instruction and the second chip select signal are used to control the second SDRAM to execute the data read/write instruction.

In the method provided by the first aspect, the mode parameter is used to indicate the validity of each of the two chip select signals. The mode parameter can be a sequence containing 2 bits. For example, when the mode parameter is 01, it indicates that the first chip selection signal is valid; when the mode parameter is 10, it indicates that the second chip selection signal is valid; when the mode parameter is 00 or 11, it indicates the first chip selection signal and the second The chip select signals are all valid. In other words, when at least one of the two chip select signals is valid according to the mode parameter, the method may be implemented as follows: when the mode parameter is the first preset value (such as 01), the first chip is selected. The signal is valid; when the mode parameter is the second preset value (such as 10), the second chip selection signal is valid; when the mode parameter is the third preset value (such as 00) or the fourth preset value (such as 11) , the first chip selection signal and the second chip selection signal are valid. Thus, by using an indication of a 2-bit mode parameter, the use of the validity of the two chip select signals can be covered, thereby enabling the validity of each chip select signal of the two chip select signals to be indicated by the mode parameter.

It should be noted that the number of bits included in the mode parameter is not limited to two, as long as the mode parameter can cover the validity of the two chip select signals.

In a second aspect, the present application provides a memory control device including a single board, a SOC chip, a first SDRAM, and a second SDRAM.

The first SDRAM and the second SDRAM are mirrored and fixed on both sides of the board, the SOC chip and the first SDRAM are fixed on the first side of the board, and the second SDRAM is fixed on the second side of the board. A first address signal link, a first chip select signal link, and a second chip select signal link are disposed on the first side of the board. The first address signal link is used for connecting the address signal pin of the first SDRAM and the address signal pin of the SOC chip, and the first chip selection signal pin is used. The chip select signal pin of the first SDRAM and the first chip select signal pin of the SOC chip are connected.

The board is further provided with at least one via, the first address signal link is communicatively coupled to the second address signal link on the second side of the board through the at least one via, and the second chip select signal passes through at least one The via is in communication with the third chip select signal link on the second side of the board, and the first address signal link and the second address signal link together address the address signal pin of the SOC chip and the address signal of the second SDRAM The pin communication connection, the second chip select signal link and the third chip select signal link together connect the second chip select signal pin of the SOC chip and the chip select signal pin of the second SDRAM.

The SOC chip includes: a processor, a dynamic memory controller, and a driver. The processor is configured to generate an access instruction for the first SDRAM and the second SDRAM according to the instruction requirement; the dynamic storage controller is configured to generate two chip select signals according to the access instruction, and select at least one of the two chip select signals according to the mode parameter The signal is valid; the driver is configured to output the first chip select signal of the access command and the two chip select signals to the first SDRAM, and output the second chip select signal of the access command and the two chip select signals to the second SDRAM . The first chip select signal is used to enable the first SDRAM, the second chip select signal is used to enable the second SDRAM, and the mode parameter is used to indicate the validity of each chip select signal of the two chip select signals.

In the memory control device provided by the second aspect, since the SOC chip and the first SDRAM are fixed on the first side of the board, the second SDRAM is fixed on the second side of the board, and the address signal pin of the first SDRAM And the address signal pin of the SOC chip is communicatively connected through the first address signal link, the chip select signal pin of the first SDRAM, and the first chip select signal pin of the SOC chip are communicatively connected through the first chip select signal link; The address signal pin of the two SDRAM and the address signal pin of the SOC chip are communicatively connected through the first address signal link and the second address signal link, the chip select signal pin of the second SDRAM, and the second chip select signal of the SOC chip. The pin is communicatively coupled through the second chip select signal link and the third chip select signal link. Thus, when wiring the first SDRAM and the second SDRAM, the first SDRAM and the second SDRAM can share the first address signal link. In addition, the first address signal link and the second address signal link are only connected by at least one via communication on the board, and the second chip select signal link and the third chip select signal link are also passed through at least one of the boards. A via communication connection, thus reducing the wiring area and the number of wiring layers in the control device of the memory provided by the second aspect, thereby reducing the wiring difficulty, compared with the single-board wiring scheme in the prior art. At the same time, since the number of wirings on the single board, the wiring area, and the number of wiring layers are reduced during wiring, the memory control device provided by the second aspect can reduce crosstalk and noise between signals due to single board wiring, and improve signals. quality.

In addition, since the dynamic memory controller in the SOC chip validates at least one of the two chip select signals according to the mode parameter, and the driver in the SOC chip outputs the access command and the first chip select signal to the first SDRAM, The access command and the second chip select signal are output to the second SDRAM. Therefore, when the first SDRAM is required to execute an access instruction that has strict requirements on the line order, the first chip select signal is valid and the second chip select signal is invalid by the indication of the mode parameter, so that the first SDRAM can perform the single SDRAM separately. Accessing the instruction; or, when the second SDRAM is required to execute an access instruction that has strict requirements on the line sequence, the first chip selection signal is invalid and the second chip selection signal is valid by the indication of the mode parameter, thereby making the second SDRAM available The access instruction is executed separately; or, when the first SDRAM and the second SDRAM are required to simultaneously execute an access instruction that is not strictly required for the line sequence, the first chip selection signal and the second chip selection signal are both indicated by the indication of the mode parameter. Effective so that the first SDRAM and the second SDRAM can simultaneously execute the access instruction.

In one possible design, the access instruction can be an MRS instruction or a data read and write instruction.

When the access instruction is an MRS instruction, the SOC chip can output the MRS instruction and the first slice to the first SDRAM Selecting a signal to control the first SDRAM to execute the MRS instruction, and controlling the second SDRAM to execute the MRS instruction by outputting the MRS instruction and the second chip selection signal to the second SDRAM; when the access instruction is a data read/write instruction, the SOC chip can pass The first SDRAM outputs a data read/write instruction and a first chip select signal to control the first SDRAM to execute the data read/write instruction, and controls the second SDRAM to perform the data read by outputting the data read/write instruction and the second chip select signal to the second SDRAM. Write instructions.

In the memory control device provided in the second aspect, the mode parameter is used to indicate the validity of each of the two chip select signals. The mode parameter can be a sequence containing 2 bits. For example, when the mode parameter is 01, it indicates that the first chip selection signal is valid; when the mode parameter is 10, it indicates that the second chip selection signal is valid; when the mode parameter is 00 or 11, it indicates the first chip selection signal and the second The chip select signals are all valid. In other words, when the dynamic memory controller in the SOC chip is enabled to enable at least one of the two chip select signals according to the mode parameter, the method may be implemented as follows: 01), the dynamic memory controller makes the first chip select signal valid; when the mode parameter is the second preset value (such as 10), the dynamic memory controller makes the second chip select signal valid; when the mode parameter is the third pre- When a value (such as 00) or a fourth preset value (such as 11) is set, the dynamic memory controller makes the first chip select signal and the second chip select signal valid. Thus, by using an indication of a 2-bit mode parameter, the use of the validity of the two chip select signals can be covered, thereby enabling the validity of each chip select signal of the two chip select signals to be indicated by the mode parameter.

The mode parameter may be set when the SOC chip is initialized, for example, the mode parameter is set to a sequence containing 2 bits at the time of initialization, that is, the value of the mode parameter may be 01, 10, 00, and 11. When the control device of the memory provided by the second aspect controls the first SDRAM and the second SDRAM to execute the access instruction, the processor issues the configuration value of the mode parameter to the dynamic storage controller. When the configuration of the mode parameter needs to be changed according to the instruction requirement, the processor re-issues the updated configuration value to the dynamic storage controller. For example, when the control device of the memory provided by the second aspect controls the first SDRAM to execute the MRS instruction, the processor configures the mode parameter to 01 according to the instruction requirement and delivers it to the dynamic storage controller; when the memory of the second aspect is controlled When the device controls the second SDRAM to execute the MRS instruction, the processor configures the mode parameter to 10 according to the instruction requirement and delivers the mode parameter to the dynamic storage controller.

DRAWINGS

1 is a schematic structural diagram of a SOC chip provided by the present application;

2 is a schematic diagram of an arrangement of a first plurality of SDRAMs on a board provided by the present application;

3 is a schematic diagram of a second plurality of SDRAMs arranged on a single board according to the present application;

4 is a schematic structural diagram of a memory control device provided by the present application;

FIG. 5 is a schematic diagram of a third plurality of SDRAMs arranged on a single board according to the present application; FIG.

6 is a schematic flow chart of a method for controlling a memory provided by the present application;

FIG. 7 is a schematic flowchart diagram of another method for controlling a memory provided by the present application.

detailed description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings.

The present application relates to a SOC chip accessing an SDRAM by transmitting an access instruction, and the SOC chip instructing the SDRAM whether to execute an access instruction received by itself by transmitting a chip select signal. The chip select signal is used to enable the SDRAM. When the chip select signal received by the SDRAM is valid, the SDRAM receiving the chip select signal is enabled, and the SDRAM executes the access command received by itself, and receives the SDRAM. When the chip select signal is invalid, the SDRAM does not execute the access command received by itself.

As shown in FIG. 1, the SOC chip may include a processor, a dynamic memory controller (DMC), and a driver. The processor, the dynamic memory controller and the driver are interconnected by a bus, and the SOC chip realizes communication connection with a plurality of external SDRAMs through the driver, so that the SOC chip controls the plurality of SDRAMs by transmitting the access command and the chip select signal. The processor is configured to generate an access instruction (such as a data read/write instruction, an MRS, etc.) according to the instruction requirement, and the dynamic storage controller is configured to generate a chip selection signal according to the access instruction, and then send the access instruction and the chip selection signal to the SDRAM through the driver. When the chip select signal received by the SDRAM is valid, the SDRAM performs corresponding read and write operations and register configuration operations according to the received access command; when the chip select signal is invalid, the SDRAM does not execute the received access command.

In the embodiment of the present application, the SDRAM includes, but is not limited to, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) and a DDR2 SDRAM (Double Data Rate Two Synchronous Dynamic Random Access Memory). Double Data Rate Synchronous Dynamic Random Access Memory, DDR3 SDRAM (Double Data Rate Three Synchronous Dynamic Random Access Memory), DDR4 SDRAM (Double Data Rate Four Synchronous Dynamic Random Access Memory, Fourth Generation double data rate synchronous dynamic random access memory).

When the SOC chip enables the SDRAM by transmitting a chip select signal to the SDRAM, a chip select signal can be used to enable multiple SDRAMs belonging to the same RANK. When the chip select signal is valid, the plurality of SDRAMs belonging to the same RANK execute the received access command; when the chip select signal is invalid, the plurality of SDRAMs belonging to the same RANK do not execute the received access command. The plurality of SDRAMs belonging to the same RANK can simultaneously execute the access instruction sent by the SOC chip, and the plurality of SDRAMs share the address line and the control line.

In the prior art, a plurality of SDRAMs belonging to the same RANK are generally arranged on a single board: a plurality of SDRAMs are integrated on one side of the single board, and the SOC chip sends the same chip select signal to the plurality of SDRAMs, that is, by sending The chip select signal enables multiple SDRAMs. Such a wiring manner can be as shown in FIG. 2. In FIG. 2, a chip select signal is used to enable two SDRAMs. In practice, the number of SDRAMs that can be used for one chip select signal is not limited to two. Further, CS in FIG. 2 denotes a chip select signal pin for transmitting a chip select signal, A11 denotes an address signal pin for transmitting address information in the SDRAM, and a communication link for connecting an address signal pin of the SOC chip and the SDRAM. Referring to the address signal link, the communication link connecting the SOC chip and the chip select signal pin of the SDRAM is called a chip select signal link.

It can be seen from FIG. 2 that when a chip select signal output by the SOC chip is used to enable two SDRAMs belonging to the same RANK, the commonly used wiring method is not only difficult to route, but also a signal output by the same pin is passed. When a communication link (chip select signal link or address signal link) is transmitted to two SDRAMs, the signal needs to be split into two channels and transmitted to two SDRAMs respectively, which causes a large difference in wiring between the two SDRAMs. Reducing the signal quality of this signal leads to problems with Signal Integrity (SI).

In order to overcome the problem of large wiring difficulty, if the two SDRAMs in FIG. 2 are simply mirrored and fixed on both sides of the single board (ie, one SDRAM is fixed on one side of the single board, and the other SDRAM is fixed on the other side of the single board). One side), although the address signal links of the two SDRAMs and the SOC chip can be communicated through the vias on the board, so that the signals in the address signal link do not have to be divided when the two SDRAM shared address signal links are realized. Two channels are transmitted to two SDRAMs, which reduces wiring difficulty and improves signal quality. However, this kind of wiring will bring some other problems, which are elaborated as follows:

After the two SDRAM images in FIG. 2 are fixed on both sides of the single board, the two SDRAMs and their connection relationship with the SOC chip can be as shown in FIG. 3. For simplicity of description, the SDRAM of FIG. 3 fixed to the same side of the board as the SOC chip is referred to as a first SDRAM, and the other SDRAM is referred to as a second SDRAM.

As can be seen from FIG. 3, in the wiring manner shown in FIG. 3, the address signal pins of the first SDRAM and the address signal pins of the second SDRAM are not all in one-to-one correspondence. For example, the address signal pin A11 of the first SDRAM corresponds to the address signal pin A13 of the second SDRAM, and the address signal pin A13 of the first SDRAM corresponds to the address signal pin A11 of the second SDRAM. When the SOC chip outputs an access instruction to the SDRAM, both SDRAMs will receive the access instruction, but since the address signals of the two SDRAMs are not one-to-one correspondence, the same access is received for the two SDRAMs. The address signal pins of the instruction may be different.

When the access command output by the SOC chip is a data read/write command, the wiring mode shown in FIG. 3 does not affect the execution result of the data read/write command. This is because: when the SOC chip sends a write command to write some data to the two SDRAMs, the address signal pin A11 of the SOC chip and the address signal pin A11 of the first SDRAM and the address signal of the second SDRAM are used. The pin A13 is connected, so that the SOC chip instructs the first SDRAM to write the data to the address A through the address signal pin A11, instructing the second SDRAM to write the data to the address B. Correspondingly, when the SOC chip sends a read command to read the data to the two SDRAMs, the read operation of the first SDRAM is mapped to the address A, and the read operation of the second SDRAM is mapped to the address B. That is to say, when the connection mode shown in FIG. 3 is adopted, although the same data is written to different addresses during the write operation, when the data is read, the read command is mapped to the corresponding correct address, It also successfully reads the data you want to read.

When the access instruction output by the SOC chip is an access instruction that has strict requirements on the line order, such as the MRS instruction, the wiring mode shown in FIG. 3 affects the execution of the access instruction because: for the line order is strictly required In terms of access instructions, each address signal pin of the SDRAM has its specific function. For example, when the SOC chip outputs an MRS command, the SDRAM needs to receive the SOC chip through a specific address signal pin (such as the address signal pin A11). The configuration value of the mode register. When the SOC chip transmits a certain configuration value of the mode register through the address signal pin A11, the configuration value is transmitted to the address signal pin A11 of the first SDRAM and the address signal pin A13 of the second SDRAM, for the first SDRAM. Said that it can receive the configuration value through the correct address signal pin, but for the second SDRAM, the address signal pin that receives the configuration value is wrong, causing the second SDRAM to pass the wrong address signal. The pin receives the configuration value, causing a configuration error in the mode register.

In summary, when multiple access control commands belonging to the same RANK are executed, if the SDRAM image is simply placed on both sides of the board as shown in FIG. 3, the wiring difficulty and signal quality can be reduced, but the impact is affected. These are the correct execution of access instructions that have strict requirements on the line order. Therefore, in the field of storage technology, there is still a need for a memory control method and apparatus for reducing wiring difficulty and improving signal quality when controlling access commands of a plurality of SDRAMs belonging to the same RANK.

The plurality referred to in the present application means two or more.

In addition, it should be understood that in the description of the present application, the terms "first", "second" and the like are used only to distinguish the purpose of description, and are not to be understood as indicating or implying relative importance, nor as an indication. Or suggest the order.

The control scheme of the memory provided by the present application will be specifically described below with reference to the accompanying drawings.

4 is a schematic structural diagram of a control device for a memory provided by the present application.

The memory control device 400 (hereinafter referred to as "device 400") shown in FIG. 4 includes a single board 401, a SOC chip 402, a first SDRAM 403, and a second SDRAM 404.

The first SDRAM 403 and the second SDRAM 404 are mirrored and fixed on both sides of the single board 401, the SOC chip 402 and the first SDRAM 403 are fixed on the first side of the single board 401, and the second SDRAM 404 is fixed on the second side of the single board 401. On the first side of the board 401, a first address signal link, a first chip select signal link, and a second chip select signal link are disposed. The first address signal link is used to connect the address signal of the first SDRAM 403. The pin and the address signal pin of the SOC chip 402, the first chip select signal pin is used to connect the chip select signal pin of the first SDRAM 403 and the first chip select signal pin of the SOC chip 402, and the board 401 is further provided. There is at least one via, the first address signal link is communicatively coupled to the second address signal link on the second side of the board 401 through the at least one via, and the second chip select signal is passed through the at least one via and the single A third chip select signal link on the second side of the board 401 is communicatively coupled. The first address signal link and the second address signal link together form an address signal pin of the SOC chip 402 and an address signal pin of the second SDRAM 404. Communication connection, second chip selection signal link and third chip selection signal Connecting the communication chip select signal pin 402 of the second sheet-SOC chip select signal pin and a second passage SDRAM404 together.

The SOC chip 402 includes a processor 402a, a dynamic memory controller 402b, and a driver 402c. In the SOC chip 402, the processor 402a is configured to generate an access instruction to the first SDRAM 403 and the second SDRAM 404 according to the instruction requirement; the dynamic storage controller 402b is configured to generate two chip select signals according to the access instruction, and make two according to the mode parameter. At least one chip select signal of the chip select signal is active; wherein a first chip select signal of the two chip select signals is used to enable the first SDRAM 403, and a second chip select signal of the two chip select signals is used for enabling a second SDRAM 404, the mode parameter is used to indicate the validity of each of the chip select signals; the driver 402c is configured to output the access command and the first chip select signal to the first SDRAM 403, and the access command and the second The chip select signal is output to the second SDRAM 404.

It should be noted that multiple address lines may be included in the first address signal link described in this application. For example, when the first address signal link includes N address lines, the first address signal link communicates with the second address signal link on the second side of the board 401 through at least one via on the board 401. Connection, wherein the second address signal link also includes N address lines.

In the embodiment of the present application, the SOC chip 402 and the first SDRAM 403 are fixed on the first side of the single board 401, and the second SDRAM 404 is fixed on the second side of the single board 401. For the first SDRAM 403, the address signal pin and the chip select signal pin need to be respectively connected with the address signal pin of the SOC chip 402 and the first chip select signal pin: the address signal pin and the SOC of the first SDRAM 403 The address signal pins of the chip 402 are communicatively coupled through the first address signal link, and the chip select signal pins of the first SDRAM 403 and the first chip select signal pins of the SOC chip 402 are communicatively coupled through the first chip select signal link; For the second SDRAM 404, the address signal pin and the chip select signal pin need to be respectively connected to the address signal pin and the second chip select signal pin of the SOC chip 402: the address signal pin of the second SDRAM 404 and the SOC chip. The address signal pin of 402 passes through the first address signal link and the second address signal link, the chip select signal pin of the second SDRAM 404, and the second chip select signal of the SOC chip 402 pass the second chip select signal. The link is in communication with the third chip select signal link.

In the device 400, the first SDRAM and the second SDRAM share the first address signal of the first side of the single board 401 a link, and when both the first chip select signal and the second chip select signal are valid, the access instruction and the first chip select signal are output to the first SDRAM through the SOC chip, and the access command and the second chip select are outputted to the second SDRAM The signal realizes that the first SDRAM and the second SDRAM simultaneously execute the access instruction, that is, to simultaneously control the first SDRAM and the second SDRAM to execute the access instruction, and therefore, the first SDRAM and the second SDRAM belong to the same RANK.

In apparatus 400, a mode parameter is used to indicate the validity of each of the two chip select signals. The mode parameter can be a sequence containing 2 bits. For example, when the mode parameter is 01, it indicates that the first chip selection signal is valid; when the mode parameter is 10, it indicates that the second chip selection signal is valid; when the mode parameter is 00 or 11, it indicates the first chip selection signal and the second The chip select signals are all valid. In other words, when the dynamic storage controller 402b in the SOC chip 402 is enabled to enable at least one of the two chip select signals according to the mode parameter, the dynamic memory controller 402b can be implemented by: when the mode parameter is the first preset value. (such as 01), the dynamic memory controller 402b makes the first chip select signal valid; when the mode parameter is the second preset value (such as 10), the dynamic memory controller 402b makes the second chip select signal valid; when the mode parameter The dynamic memory controller 402b asserts the first chip select signal and the second chip select signal when it is a third preset value (such as 00) or a fourth preset value (such as 11). Thus, by using an indication of a 2-bit mode parameter, the use of the validity of the two chip select signals can be covered, thereby enabling the validity of each chip select signal of the two chip select signals to be indicated by the mode parameter.

It should be noted that the mode parameter included in the present application is not limited to two, as long as the mode parameter can cover the validity of the two chip select signals.

In the present application, the SOC chip 402 outputs an access instruction and a first chip select signal to the first SDRAM 403, and outputs an access command and a second chip select signal to the second SDRAM 404, that is, in the device 400, through the SOC chip 402. The output first chip select signal and second chip select signal respectively control the first SDRMA 403 and the second SDRAM 404 to execute an access command. The access instruction may be an MRS instruction or a data read/write instruction.

When the access command is an MRS command, the SOC chip 402 can control the first SDRAM 403 to execute the MRS command by outputting the MRS command and the first chip select signal to the first SDRAM 403, and output the MRS command and the second chip select signal to the second SDRAM 404. The second SDRAM 404 is controlled to execute the MRS instruction; when the access instruction is the data read/write instruction, the SOC chip 402 can control the first SDRAM 403 to execute the data read and write instruction by outputting the data read/write instruction and the first chip select signal to the first SDRAM 403. The second SDRAM 404 is controlled to execute a data read/write command by outputting a data read/write command and a second chip select signal to the second SDRAM 404.

In the present application, the dynamic memory controller 402b in the SOC chip 402 validates at least one of the two chip select signals according to the mode parameter, and then the driver 403c in the SOC chip 402 outputs the access command and the first chip select signal. After the first SDRAM 403 is output and the access command and the second chip select signal are output to the second SDRAM 404, the execution of the access instruction by the first SDRAM and the second SDRAM can be classified into the following three cases:

First, the first chip select signal is valid, and the second chip select signal is invalid.

When the first chip select signal is valid and the second chip select signal is invalid, the first SDRAM receiving the first chip select signal can execute an access command received by itself, such as a data read/write command, an MRS command, etc., and receive the second The second SDRAM of the chip select signal does not execute the access command received by itself. For example, when the mode register of the first SDRAM needs to be configured, the first chip select signal for enabling the first SDRAM can be enabled by the indication of the mode parameter, so that the second chip select signal for enabling the second SDRAM is enabled. invalid. In this way, it is possible to separately configure the mode register of the first SDRAM.

Second, the first chip select signal is invalid, and the second chip select signal is valid.

When the first chip select signal is invalid and the second chip select signal is valid, the first SDRAM receiving the first chip select signal does not execute the access command received by itself, and the second SDRAM receiving the second chip select signal performs self reception. Access commands, such as data read and write instructions, MRS instructions, etc. For example, when the mode register of the second SDRAM needs to be configured, the second chip select signal for enabling the second SDRAM can be enabled by the indication of the mode parameter, so that the first chip select signal for enabling the first SDRAM is enabled. invalid. In this way, it is possible to separately configure the mode register of the second SDRAM.

3. The first chip selection signal and the second chip selection signal are valid.

When both the first chip select signal and the second chip select signal are valid, both the first SDRAM and the second SDRAM can execute access commands received by themselves, such as data read and write instructions. For example, when the mode registers of the first SDRAM and the second SDRAM are all configured, the first chip selection signal and the second chip selection signal are both valid by the indication of the mode parameter. In this way, the first SDRAM and the second SDRAM can simultaneously execute access instructions that are not strictly required for the line order, such as data read/write instructions.

In combination with the first case and the second case, when the configuration of the mode register is required for the first SDRAM and the second SDRAM in the device 400, the SOC chip can indicate that the first chip select signal is valid by the mode parameter, and the second chip selects The signal is invalid, thereby completing the configuration of the mode register of the first SDRAM by transmitting the configuration value of the mode register to the first SDRAM through the first address signal link; and then indicating that the second chip selection signal is valid by the mode parameter, thereby passing the first address signal The link and the second address signal link are configured to the second SDRAM transfer mode register to complete the configuration of the mode register of the second SDRAM.

Since the first SDRAM and the second SDRAM image are fixed on both sides of the single board 401, the address signal pins of the SOC chip 402 and the address sequence of the address signal pins of the first SDRAM are in one-to-one correspondence, and the address signal tube of the SOC chip The line order of the pin and the address signal pins of the second SDRAM are not necessarily one-to-one correspondence. For example, the address signal pin A11 of the SOC chip corresponds to the address signal pin A11 of the first SDRAM and the address signal pin A13 of the second SDRAM. That is, the configuration value of the mode register transmitted by the SOC chip through the address signal pin A11 is transmitted to the address signal pin A11 of the first SDRAM and the address signal pin A13 of the second SDRAM. Therefore, when the configuration value of the mode register is transmitted to the first SDRAM and the second SDRAM by the address signal pin of the SOC chip, the SOC chip knows the correspondence between the address signal pin of the second SDRAM and the address signal pin of the second SDRAM. The configuration value of the mode register is transferred to the corresponding address signal pin in the second SDRAM through the correct address signal pin.

It should be noted that the number of the first SDRAMs in the present application may be multiple. When the number of the first SDMMAs fixed to the first side of the single board is plural, the number of the second SDRAMs mirrored to the second side of the single board is also plural. That is, the plurality of first SDRAMs and the plurality of second SDRAMs are in one-to-one correspondence. For each of the first SDRAMs fixed to the first side of the single board, a mirror image is fixed on the second side of the single board. The second SDRAM corresponds to it. When the number of the first SDRAM and the second SDRAM is multiple, in the control device of the memory provided by the present application, the routing manner of the single board can be as shown in FIG. 5. Figure 5 shows the internal structure of the SOC chip and the operations performed by the various components and Figure 4 The SOC chip 402 is the same, so the internal structure of the SOC chip is not shown in FIG.

For the case where the number of the first SDRMA and the second SDRMA is multiple, if the control device of the memory provided by the present application controls the first SDRAM and the second SDRAM to execute the access instruction, the SOC chip can access the instruction and the first The chip select signals are respectively output to the plurality of first SDRAMs, and the access instructions and the second chip select signals are respectively output to the plurality of second SDRAMs. Then, when the access instruction is executed, the plurality of first SDRMAs determine whether the access instruction needs to be executed according to the first chip select signal, that is, the operations of the plurality of first SDRAMs to execute the access instruction are synchronized. For example, when the access instruction is an MRS instruction and the first chip select signal is valid, the plurality of first SDRAMs execute the MRS instruction; for example, when the access instruction is the MRS instruction and the first chip selection signal is invalid, the plurality of None of the SDRAMs execute the MRS instruction. Similarly, when the plurality of second SDRAMs determine whether the access instruction needs to be executed according to the second chip select signal, the operations of the plurality of second SDRAMs to execute the access instruction are also synchronized, and details are not described herein again.

In the present application, since the SOC chip and the first SDRAM are fixed on the first side of the board, the second SDRAM is fixed on the second side of the board, the address signal pin of the first SDRAM and the address signal pin of the SOC chip. The first chip signal link communication pin, the chip select signal pin of the first SDRAM, and the first chip select signal pin of the SOC chip are communicatively connected through the first chip select signal link; the address signal pin of the second SDRAM and The address signal pin of the SOC chip is communicably connected through the first address signal link and the second address signal link, the chip select signal pin of the second SDRAM, and the second chip select signal pin of the SOC chip pass the second chip select signal The link is in communication with the third chip select signal link. Thus, when wiring the first SDRAM and the second SDRAM, the first SDRAM and the second SDRAM can share the first address signal link. In addition, the first address signal link and the second address signal link are only connected by at least one via communication on the board, and the second chip select signal link and the third chip select signal link are also passed through at least one of the boards. A via communication connection thus reduces the routing area and number of wiring layers in the device 400 in comparison to the single board routing scheme provided in the prior art shown in FIG. 2, thereby reducing wiring difficulty. At the same time, since the number of wirings on the single board, the wiring area, and the number of wiring layers are reduced during wiring, the apparatus 400 provided by the present application can reduce crosstalk and noise between signals due to single board wiring, and improve signal quality.

For example, when the MRS instruction needs to be executed, the SOC chip may perform the MRS instruction separately by the first SDRAM fixed on the first side of the board according to the mode parameter indication, and complete the configuration of the mode register; The second SDRAM of the second side separately executes the MRS instruction to complete the configuration of the mode register. Thus, when the first SDRAM and the second SDRAM are simultaneously executed, the second SDRAM receives the configuration value of the mode register through the wrong address signal pin, and the mode register is incorrectly configured. When the first SDRAM and the second SDRAM are required to simultaneously execute an access instruction that is not strictly required for the line sequence, such as a data read/write instruction, the SOC chip can indicate that the first chip selection signal and the second chip selection signal are valid by the mode parameter indication. To ensure the visit Ask the correct execution of the instruction.

It should be noted that, in the embodiment of the present application, the specifications and models of the SOC chip are not limited in China.

When the SOC chip in the device 400 supports only one chip select signal output, an additional pin may be added to the SOC chip as a pin for outputting the chip select signal. This is because the SOC chip itself supports only one chip select signal output. However, in the apparatus 400 provided by the present application, the SOC chip 402 needs to output two chip select signals of the first chip select signal and the second chip select signal. An additional pin can be added to the SOC chip as a pin for outputting a chip select signal, so that the SOC chip can output two chip select signals.

When the SOC chip in the device 400 supports multiple chip select signal outputs, it is not necessary to additionally add a pin in the pin of the SOC chip to output a chip select signal, but the SOC chip itself can be used to output multiple chip select signals. Pin to output two chip select signals.

Based on the above embodiment, the present application further provides a control method of a memory, and an execution body of the control method of the memory can be regarded as a SOC chip in the control device of the memory shown in FIG. 4. As shown in FIG. 6, the method includes the following steps:

S601: Generate an access instruction for two SDRAMs according to the instruction requirement.

The two SDRAMs are mirrored and fixed on both sides of the board.

S602: Generate two chip select signals according to the access instruction.

Wherein the first chip select signal of the two chip select signals is used to enable the first SDRAM of the two SDRAMs, and the second chip select signal of the two chip select signals is used to enable the second of the two SDRAMs SDRAM.

S603: Enable at least one of the two chip select signals to be valid according to the mode parameter.

The mode parameter is used to indicate the validity of each chip select signal of the two chip select signals.

S604: Output the access instruction and the first chip selection signal to the first SDRAM, and output the access instruction and the second chip selection signal to the second SDRAM.

Optionally, the access instruction may be an MRS instruction, and the access instruction may also be a data read/write instruction.

Optionally, in S603, at least one of the two chip select signals is valid according to the mode parameter, which may be implemented by: when the mode parameter is the first preset value, making the first chip select signal valid; When the mode parameter is the second preset value, the second chip selection signal is enabled; when the mode parameter is the third preset value or the fourth preset value, the first chip selection signal and the second chip selection signal are enabled.

The method illustrated in FIG. 6 can be viewed as a method performed by SOC chip 402 in device 400, and thus implementations not detailed and described in FIG. 6 can be referred to the related description in device 400.

In the method shown in FIG. 6, since the first SDRAM and the second SDRAM are mirror-fixed on both sides of the single board, the wiring manner is easier to implement when wiring the first SDRAM and the second SDRAM. This is because, since the first SDRAM and the second SDRAM are mirrored and fixed on both sides of the board, the first SDRAM and the second SDRAM can share the address signal link, which is different from the prior art on the board. Compared with the way in which the SDRAM is wired, the wiring area and the number of wiring layers are reduced, thereby reducing the wiring difficulty. At the same time, since the number of wirings on the board, the wiring area, and the number of wiring layers are reduced during wiring, the memory control method provided by the present application can reduce crosstalk and noise between signals caused by single board wiring, and improve signal quality. .

In addition, since at least one of the two chip select signals is valid according to the mode parameter in S603, and the access command and the first chip select signal are output to the first SDRAM in S604, the access command and the second chip select are performed. The signal is output to the second SDRAM. Therefore, when the first SDRAM is required to execute an access instruction that has strict requirements on the line order, the first chip select signal is valid and the second chip select signal is invalid by the indication of the mode parameter, thereby making the first SDRAM The access instruction may be executed separately, or when the second SDRAM is required to execute an access instruction that has strict requirements on the line sequence, the first chip selection signal is invalid and the second chip selection signal is valid by the indication of the mode parameter, thereby making the first The second SDRAM can separately execute the access instruction; when the first SDRAM and the second SDRAM are required to simultaneously execute an access instruction that is not strictly required for the line order, the first chip selection signal and the second chip selection signal can be made by the indication of the mode parameter. All are valid, so that the first SDRAM and the second SDRAM can simultaneously execute the access instruction.

In the following, taking the access command as an MRS command as an example, how to use the memory control method provided by the present application to control two SDRAMs to execute an access command is described in detail. The specific execution steps are as shown in FIG. 7. Among them, the method shown in FIG. 7 can be regarded as an example of the method shown in FIG. 6.

As shown in Figure 7, the method includes the following steps:

Step 1: The SOC chip is powered on.

Step 2: Initialize the dynamic storage controller.

The initialization dynamic storage controller includes a configuration working mode, a configuration timing parameter, and the like.

Step 3: Initialize the physical layer interface.

Initializing the physical layer interface mainly refers to the initialization and calibration of the Phase Locked Loop (PLL), and the initialization and calibration of the Delay Locked Loop (DLL), thereby generating the operating clock of the system and completing the physical layer interface. Its own calibration.

Step 4: Configure the registers in the dynamic memory controller to reset the two SDRAMs.

The registers of the dynamic memory controller for resetting the two SDRAMs are configured to implement resetting of the two SDRAMs: that is, both SDRAMs are in the IDLE state and the IDLE state is maintained for at least 200 us according to the JEDEC protocol requirements, and then the reset is cancelled.

Step 5: Configure the dynamic storage controller and two SDRAMs to exit the automatic refresh state.

According to the requirements of the JEDEC protocol, after performing step four for at least 500us, the dynamic memory controller and the two SDRAMs are configured to exit the automatic refresh state by pulling up the CEK signal.

Step 6: Configure the mode register of the first SDRAM by the indication of the mode parameter.

When step 6 is performed, the mode parameter may be 01, and the mode parameter indicates that the first chip select signal is valid, and then the SOC chip may send the MRS command to the first SDRAM through the dynamic memory controller, and the first SDRAM receives the MRS command. The configuration of the mode register can be done by executing the MRS instruction.

Step 7: Configure the mode register of the second SDRAM by the indication of the mode parameter.

When step 6 is performed, the mode parameter may be 10, and the mode parameter indicates that the second chip select signal is valid, and then the SOC chip may send the MRS command to the second SDRAM through the dynamic memory controller, and the second SDRAM after receiving the MRS command The configuration of the mode register can be done by executing the MRS instruction.

Step 8: The chip select signals for enabling both SDRAMs are valid by the indication of the mode parameters.

When step 8 is performed, the mode parameter may be 00 or 11, and the mode parameter indicates that both the first chip select signal and the second chip select signal are valid. That is to say, after configuring the mode registers of the first SDRAM and the second SDRAM in steps 6 and 7 respectively, the first chip selection signal and the second chip selection signal are both valid by the indication of the mode parameter, thereby making the two The SDRAM can simultaneously execute data read and write instructions after the configuration of the mode register is completed.

Step 9: Start data training on the physical layer interface.

Start data training on the physical layer interface to find the appropriate data sampling window.

Step 10: Start the system business.

After the execution of step ten, the two SDRAMs can simultaneously execute the data read and write instructions.

It should be noted that, after performing step 10, if it is necessary to perform a separate operation on one of the two SDRAMs, the dynamic storage controller can still be implemented by configuring corresponding mode parameters.

In summary, the memory control method and apparatus provided by the present application can reduce wiring difficulty and improve signal quality when controlling access commands of a plurality of SDRAMs belonging to the same RANK.

Those skilled in the art will appreciate that embodiments of the present application can be provided as a method, system, or computer program product. Thus, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware. Moreover, the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the present application. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

It will be apparent to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit and scope of the application. Thus, it is intended that the present invention cover the modifications and variations of the present invention.

Claims

A method for controlling a memory, comprising:

Generating access instructions to two synchronous dynamic random access memory SDRAMs according to the instruction requirements, the two SDRAMs being mirrored and fixed on both sides of the board;

Generating two chip select signals according to the access instruction, wherein a first chip select signal of the two chip select signals is used to enable a first SDRAM of the two SDRAMs, where the two chip select signals a second chip select signal for enabling a second SDRAM of the two SDRAMs;

And causing at least one chip select signal of the two chip select signals to be valid according to a mode parameter, where the mode parameter is used to indicate validity of each chip select signal of the two chip select signals;

Outputting the access instruction and the first chip select signal to the first SDRAM, and outputting the access instruction and the second chip select signal to the second SDRAM.
The method of claim 1 wherein said access instruction configures an MRS instruction for a mode register or said access instruction is a data read and write instruction.
The method according to claim 1 or 2, wherein the at least one of the two chip select signals is valid according to the mode parameter, including:

When the mode parameter is the first preset value, the first chip selection signal is valid;

When the mode parameter is the second preset value, enabling the second chip select signal to be valid;

When the mode parameter is a third preset value or a fourth preset value, the first chip select signal and the second chip select signal are enabled.
A control device for a memory, comprising: a single board, an on-chip system SOC chip, a first SDRAM and a second SDRAM, wherein the first SDRAM and the second SDRAM are mirrored and fixed on both sides of the board The SOC chip and the first SDRAM are fixed on the first side of the board, and the second SDRAM is fixed on the second side of the board, and the first side of the board is a first address signal link, a first chip select signal link, and a second chip select signal link, wherein the first address signal link is used to connect an address signal pin of the first SDRAM and the SOC chip The address signal signal pin, the first chip select signal pin is used to connect the chip select signal pin of the first SDRAM and the first chip select signal pin of the SOC chip, and the board is further configured Having at least one via, the first address signal link being communicatively coupled to a second address signal link on a second side of the board through the at least one via, the second chip select signal link Communicating with the third chip select signal link on the second side of the board through the at least one via, The first address signal link and the second address signal link together connect an address signal pin of the SOC chip and an address signal pin of the second SDRAM, the second chip select signal link and The third chip select signal link communicatively connects the second chip select signal pin of the SOC chip and the chip select signal pin of the second SDRAM;

The SOC chip includes:

a processor, configured to generate an access instruction to the first SDRAM and the second SDRAM according to an instruction requirement;

a dynamic storage controller, configured to generate two chip select signals according to the access instruction, and enable at least one chip select signal of the two chip select signals according to a mode parameter; wherein, among the two chip select signals a first chip select signal for enabling the first SDRAM, a second chip select signal of the two chip select signals for enabling the second SDRAM, the mode parameter is used to indicate the two The validity of each chip select signal in the chip select signal;

a driver for outputting the access instruction and the first chip select signal to the first SDRAM, The access instruction and the second chip select signal are output to the second SDRAM.
The apparatus according to claim 4, wherein said access instruction is an MRS instruction, or said access instruction is a data read/write instruction.
The device according to claim 4 or 5, wherein the dynamic storage controller, when validating at least one of the two chip select signals according to the mode parameter, comprises:

When the mode parameter is the first preset value, the dynamic storage controller makes the first chip select signal valid;

When the mode parameter is the second preset value, the dynamic storage controller makes the second chip select signal valid;

When the mode parameter is a third preset value or a fourth preset value, the dynamic storage controller makes the first chip select signal and the second chip select signal valid.