TWI488184B - Serial flash controller, serial flash memory, and method thereof - Google Patents

Description

Tandem flash controller, tandem flash memory and method for performing same

The disclosed embodiments relate to a serial flash memory, and more particularly to a tandem flash memory utilizing a latch line that assists in synchronization.

Compared with parallel flash, tandem flash generally has fewer pins, occupies less area on the printed circuit board (PCB), and consumes less power. Easy to control and reduce overall system cost. Therefore, in-line flash is widely used in various electronic devices, including portable electronic devices such as mobile phones, desktop personal computers, portable multimedia players, handheld game machines, or other devices.

Typically, a serial clock provided by a serial flash controller synchronizes communication between the controller and the serial flash memory. In theory, the commands, addresses, and data sent by the controller to the memory should be well-aligned with the serial clock to ensure that the memory can latch the command, address, and data at the correct timing. . Similarly, the data sent from the memory to the controller should also be well matched to the serial clock to ensure that the controller can latch the data at the correct timing.

However, when the tandem flash controller and the tandem flash memory are in the case of high speed or double data rate (DDR), the information bits transmitted between the above two components (information bits) Possible pair of strings The delay of the edge of the column clock. Sometimes the above delay is longer than one cycle of the serial clock. As long as there is a delay, the memory will not be able to latch commands, addresses, and/or data, which are correctly received from the controller based on the serial clock. Similarly, as long as there is a delay, the controller will not be able to latch the data correctly received from the memory based on the serial clock.

In view of this, the present invention provides a tandem flash controller, a tandem flash memory, and a method of performing the same.

A method performed by a tandem flash controller and a tandem flash memory, wherein the tandem flash controller and the tandem flash memory are provided by a serial clock line, a plurality of serials An input/output line and a latch line interconnect, and the serial clock line carries a serial clock from the serial flash controller to the tandem flash memory, the method comprising: transmitting the complex number The serial input/output line and the latch line respectively transmit the latch signal generated by the data bit and the memory from the serial flash memory to the serial flash controller; and allow the string The column flash controller replaces the serial clock with a latch signal generated by the memory to latch the data bit received through the plurality of serial input/output lines.

A method performed by a tandem flash controller and a tandem flash memory, wherein the tandem flash controller and the tandem flash memory are provided by a serial clock line, a plurality of serials An input/output line and a latch line interconnect, and the serial clock line carries a serial clock from the serial flash controller to the tandem flash memory, the tandem flash control And the method of performing tandem flash memory includes: translating the plurality of serials The input/output line and the latch line respectively send the information bit and the latch signal generated by the controller to the serial flash memory from the serial flash controller; and allow the serial flash to be flashed The memory replaces the serial clock with a latch signal generated by the controller to latch the information bit received through the plurality of serial input/output lines.

A tandem flash controller, wherein the serial flash controller and the tandem flash memory are interconnected by a serial clock line, a plurality of serial input/output lines, and a latch line, The tandem flash controller includes: a serial clock block configured to transmit a serial clock to the serial flash memory through the serial clock line; a serial input/output block, configured Transmitting information bits to the tandem flash memory through the plurality of serial input/output lines and receiving data bits from the tandem flash memory through the plurality of serial input/output lines And a latching block configured to transmit, by the latch line, a latch signal generated by the controller to the serial flash memory, thereby synchronizing with the serial flash memory to receive the information bit, or A latch signal generated by receiving the memory from the serial flash memory through the latch line is configured to be synchronized with the data bit received through the plurality of serial input/output lines.

A tandem flash memory, wherein the tandem flash memory and the serial flash controller are interconnected by a serial clock line, a plurality of serial input/output lines, and a latch line. The tandem flash memory includes: a memory array; and a command and control logic block connecting the serial clock line, the plurality of serial input/output lines, and the latch line, and configuring the command And the control logic block is as follows: receiving the serial clock from the serial flash controller through the serial clock line; according to the plurality of serial transmissions An input/output line accesses the memory array from an instruction received by the serial flash controller; and latches information bits received from the serial flash controller through the plurality of serial input/output lines And the information bit is synchronized with a latch signal generated by a controller received from the serial flash controller through the latch line, or through the plurality of serial input/output lines and the latch line The data bit and the latch signal generated by the memory are synchronously sent to the serial flash controller.

The invention provides a serial flash controller, a tandem flash memory and a method for performing the same, which can synchronously transmit information bits between a tandem flash memory and a tandem flash controller.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The words "including" and "including" as used throughout the specification and subsequent claims are an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Indirect electrical connections include connections through other devices.

The various embodiments of the invention are described in detail with reference to the embodiments of the invention.

1 is an illustration of an electronic device 100 according to an embodiment of the present invention. intention. The electronic device 100 can be a mobile phone, a desktop personal computer, a portable multimedia player, or a handheld game console. FIG. 1 depicts only one processor 110 of the electronic device 100, a tandem flash controller 120, and a tandem flash memory 140; the other components of the electronic device 100 are simplified. The serial flash controller 120 is interconnected with the processor 110 to provide the processor 110 with storage space for the in-line flash memory 140. The connection between the processor 110 and the in-line flash controller 120 may include a plurality of parallel lines, which are also omitted in FIG. 1 for the sake of simplicity.

The tandem flash controller 120 and the tandem flash memory 140 pass through a serial clock (SCK) line, a serial chip select (SCS) line, and a plurality of lines in other lines. Serial Input/Output (SIO) line. Specifically, in the present embodiment, there are four SIO lines including SIO[0], SIO[1], SIO[2], SIO[3]. The SCK line carries the SCK clock from the in-line flash controller 120 to the in-line flash memory 140 to synchronize the communication between the two components. The SCS line may also be referred to as a Serial Chip Enable (SCE) line that carries an SCS (or SCE) signal from the in-line flash controller 120 to the tandem flash memory 140. The SCS signal indicates when and when communication between the above two components is not possible. The SIO line carries the information bits from the in-line flash controller 120 to the tandem flash memory 140, and vice versa. For example, the information bit can include a command bit, an address bit, a data bit, or a combination thereof.

In addition to the above lines, the in-line flash controller 120 and the in-line flash memory 140 can be further interconnected through latch lines. As long as one of the two components is controlled, the latch line is a unidirectional line (unidirectional line); if both components are controlled, the latch line is a bidirectional line. The following paragraphs will assume that the latch line is a bidirectional line.

When the tandem flash memory 140 operates at a low speed or a single data rate (SDR) (ie, the rate of the SCK clock), the latch line can be inactive, for example, floating. . Specifically, when the tandem flash memory 140 operates at a low speed or SDR, the information bits transmitted through the SIO should match the SCK clock well. Thus, a separate SCK clock may be sufficient to synchronize the transmission of information bits between the in-line flash memory 140 and the in-line flash controller 120. Therefore, the above two components can avoid the additional use of latch lines to assist in synchronization.

Conversely, when the tandem flash memory 140 operates at high speed or DDR (ie, the rate is twice the SCK clock), the clock offset between the information bits transmitted over the SIO line and the SCK clock on the SCK line. (clock skew) can be very large. Due to the clock offset, the SCK clock cannot properly perform the synchronous operation. In other words, when the tandem flash memory 140 operates at high speed or DDR, the edge of the SCK clock does not correctly indicate the beginning and end of the information bits transmitted over the SIO line. In order to solve the above problem, when the tandem flash memory 140 operates at a high speed or DDR, the tandem flash memory 140 and the tandem flash controller 120 can further utilize the latch lines to assist in synchronization.

2 is a schematic diagram showing how the tandem flash controller 120 of FIG. 1 utilizes a latch line to ensure synchronization. In step 210, the serial flash controller 120 synchronously transmits the information bits to the serial flash memory 140 through the SIO line and generates the controller through the latch line. The latch signal of (controller-generated) is sent to the tandem flash memory 140. An information bit may constitute a complete instruction or part of an instruction, and thus it contains a command bit, an address bit, a data bit, or a combination thereof. For example, the instruction can be a read instruction that includes a read command or a read instruction that omits a read command.

At step 220, the in-line flash memory 140 utilizes the latch signal generated by the controller to latch the information bits received over the SIO line. Specifically, in this step, the serial flash memory 140 uses the latch signal generated by the controller as a basis for synchronization instead of using the SCK clock to latch the information bits received through the SIO line. Because there may be a clock offset between the SCK clock and the information bit, and the latch signal generated by the controller can better match the information bit, the tandem flash memory 140 uses the latch signal generated by the controller as The basis of synchronization can more accurately latch the information bits of the SIO line.

Prior to issuing the latch signal generated by the controller, the serial flash controller 120 needs to take over control of the latch line, such as by changing the latch line from a floating state to a high state/low state. After completing the latch signal generated by the transmit controller, the serial flash controller 120 needs to relinquish control of the latch line, such as by changing the latch line from a high state/low state to a floating state. If the information bit sent synchronously with the latch signal generated by the controller constitutes a read command or a partial read command, after the read command is sent, the serial flash controller 120 and the tandem flash memory 140 will Waiting for a period of a predetermined number of SCK clocks in the dummy phase. In this virtual phase, the serial flash controller 120 can abandon control of the latch lines.

If the information bit contains only a part of the instruction, ie the controller generates The latch signal overlaps only a portion of the command, and the serial flash memory 140 can utilize the latch signal generated by the controller to synchronously latch the information bits and use the SCK clock to synchronously latch the remainder of the command. For example, the instructions may include an SDR section and a DDR section, and the information bits may only include DDR sections that partially overlap the latch signals generated by the controller.

Fig. 3 is a diagram showing a method of how the tandem flash memory 140 in Fig. 1 utilizes a latch line to ensure synchronization. In step 310, the tandem flash memory 140 synchronously transmits the information bits to the serial flash controller 120 through the SIO line and transmits a memory-generated latch signal to the latch line. Tandem flash controller 120. For example, the information bit may include data bits extracted by the tandem flash memory 140 in response to a read command issued by the serial flash controller 120.

At step 320, the in-line flash controller 120 utilizes the latch signal generated by the memory to latch the information bits received through the SIO line. Specifically, in this step, the serial flash controller 120 uses the latch signal generated by the memory as a basis for synchronization instead of using the SCK clock to latch the information bits received through the SIO line. Because there may be a clock offset between the SCK clock and the information bit, and the latch signal generated by the memory can better match the information bit, the serial flash controller 120 uses the latch signal generated by the memory as the latch signal. The basis of synchronization can more accurately latch the information bits of the SIO line.

Prior to issuing the latch signal generated by the memory, the serial flash memory 140 needs to take over control of the latch line, such as by changing the latch line from a floating state to a high state/low state. After completing the latch signal generated by the transmit memory, the tandem flash memory 140 needs to give up the latch line. Control, for example by changing the latch line from a high state/low state to a floating state. If the signal bit transmitted in synchronization with the latch signal generated by the memory is obtained in response to the read command, the serial flash controller 120 and the tandem flash memory 140 will wait for a predetermined number of SCK clocks in the virtual phase. cycle. In the virtual phase, the serial flash memory 140 can abandon the control of the latch lines.

Although the schematic diagrams of the methods shown in Figures 2 and 3 are independent of one another, those skilled in the art can still operate the tandem flash block by combining the spirit of both, wherein the operation involves in-line flashing. Two communications (e.g., read operations) between the controller 120 and the in-line flash memory 140.

4 is a schematic diagram of a tandem flash controller 120 in accordance with an embodiment of the present invention. In the present embodiment, the serial flash controller 120 includes an SCK block 410, an SCS block 430, an SIO block 450, and a latch block 470.

The SCK block 410 is responsible for continuously transmitting the SCK clock to the SCK line, which includes a clock generator 412 and an output buffer 414, wherein the output buffer 414 serves as an intermediate portion between the clock generator 412 and the SCK line. The clock generator 412 generates an SCK clock based on the CLKin clock, which is provided by an oscillator. The SCS block 430 is responsible for transmitting the SCS signal to the SCS line, for example, whenever communication between the in-line flash controller 120 and the in-line flash memory 140 is allowed, by maintaining the SCS signal in a low state/high state. The situation is completed. The SCS block 430 includes a wafer selection processing unit 432 and an output buffer 434, wherein the output buffer 434 serves as an intermediate portion between the wafer selection processing unit 432 and the SCS line.

The SIO block 450 includes a data transmitter 451, an output buffer 459, a data receiver 461, and an input buffer 469, wherein the output buffer 459 serves as an intermediate portion between the data transmitter 451 and the SIO line. The buffer 469 serves as an intermediate portion between the data receiver 461 and the SIO line. Using the data transmitter 451 and the output buffer 459, the SIO block 450 transmits information bits to the serial flash memory 140 through the SIO line, wherein the information bits are generated by the SCK clock or the latch block 470. Latch clock synchronization is generated (the controller generates a latched clock that is indicated by a latch signal generated by the controller). Using the data receiver 461 and the input buffer 469, the SIO block 450 latches the information bits received from the in-line flash memory 140 through the SIO line, wherein the information bits are transmitted through the SCK clock or latch block 470. The memory received by the latch line generates a latch clock synchronization (the memory generates a latch clock that is indicated by a latch signal generated by the memory). Then, the data receiver 461 sends the latched information bit to the processor 110 by using the signal RDATA_IN, and the signal RDATA_IN can be a parallel signal.

The data transmitter 451 includes an SDR processing unit 452, a DDR processing unit 454, a multiplexer (MUX) 456, and an output control unit 458. When the data transmitter 451 is operating, the MUX 456 (which is the signal OUTPUT_DATA_EN control provided by the processor 110) and the output buffer 459 allow the information bits to be sent to the tandem flash memory 140 via SIO, where the information bits The synchronization is synchronized with the SCK clock or controller to generate a latched clock, wherein the information bits are generated by SDR processing unit 452 or DDR processing unit 454.

The latch block 470 includes a data latch generating unit 471 and an output. The control unit 473, an output buffer 475, a data latch receiving unit 477, and an input buffer 479. When the tandem flash memory 140 operates in the case of low speed or SDR, the latch block 470 is inactive; when the tandem flash memory 140 operates at high speed or DDR, the latch block is operated. 470 is active. Specifically, when the SIO block 450 is transmitting information bits to the serial flash memory 140 under high speed or DDR, the data latch generating unit 471 may additionally generate a latch signal generated by the controller. The output control unit 473 and the output buffer 475 ensure that the information bits transmitted through the SIO line are synchronized with the latch signals generated by the controller. When the SIO block 450 is receiving information bits from the serial flash memory 140 under high speed or DDR, the input buffer 479 can receive the memory from the serial flash memory 140 through the latch line. Latch signal. The data latch receiving unit 477 can control the data receiver 461 to latch the information bits received through the SIO line in synchronization with the latch signals generated by the memory. The data latch receiving unit 477 can be controlled by the signal RDATA_EN provided by the processor 110.

Figure 5 is a schematic illustration of a tandem flash memory 140 in accordance with an embodiment of the present invention. In the embodiment, the serial flash memory 140 includes a command and control logic block 510, a status register 520, an address record counter 530, a high voltage generator 540, and a data. A buffer 550, an X decoder 560, a Y decoder 570, and a memory array 580. Command and control logic block 510 receives instructions from serial flash controller 120 and controls the operation of tandem flash memory 140 accordingly. The status recorder 520 records the processing status of the serial flash memory 140. Data buffer 550 slave command and control logic area The data bits received by block 510 are written to memory array 580 or are retrieved from memory array 580 by command and control logic block 510. Using address record counter 530, high voltage generator 540, X decoder 560, and Y decoder 570, command and control logic block 510 can write data bits or retrieve data from the correct physical address of memory array 580. Bit.

When the command and control logic block 510 is receiving information bits from the serial flash controller 120 under high speed or DDR, it may additionally receive a latch signal generated by the controller. Command and control logic block 510 can then utilize the latch signals generated by the controller to synchronously latch the information bits received over the SIO line. When the command and control logic block 510 is transmitting data bits to the serial flash controller 120 under high speed or DDR, it may additionally send a latch signal generated by the memory to assist the serial flash controller. 120 obtains the data bit at the correct timing.

6 to 11 are signal timing diagrams sent between the serial flash controller 120 and the tandem flash memory 140 shown in FIG. 1, and the operation thereof is shown in FIG. 2 or FIG. Methods. In the examples shown in FIGS. 6 to 8, the serial flash controller 120 and the tandem flash memory 140 are performing a read operation in a Serial Peripheral Interface (SPI) mode. And the read operation includes an 8-bit command bit and a 24-bit address bit issued by the serial flash controller 120, an analog phase lasting 18 SCK clock cycles, and at least 8 bits returned by the tandem flash memory 140. Data bit. In the example shown in FIGS. 9 to 11, the tandem flash controller 120 and the tandem flash memory 140 are performing a read operation in a Quad Peripheral Interface (QPI) mode, and The read operation includes an 8-bit command bit issued by the serial flash controller 120. A 24-bit address bit, an analog phase lasting 18 SCK clock cycles, and at least one byte of data returned by the tandem flash memory 140. Note that Figures 6 through 11 only describe the delay between the data bit and the SCK clock, and do not describe the delay between the command (and/or address) bit and the SCK clock. The above-mentioned delay phases are indeterminate and more versatile, so the SCK clock is not an ideal basis for synchronization.

In the example shown in Figures 6 through 11, the in-line flash memory 140 further transmits a latch signal generated by the memory during the data phase to ensure that the serial flash controller 120 can lock at the correct timing. Store DDR data bits. In addition, in the examples shown in FIGS. 7 and 10, the in-line flash controller 120 further transmits a latch signal generated by the controller in the address stage to ensure that the tandem flash memory 140 is correct. The timing latches the DDR address bits. In the examples shown in Figures 8 and 11, the in-line flash controller 120 further transmits a latch signal generated by the controller in both the command phase and the address phase to ensure that the serial memory 140 is correct. The timing latches the DDR command bit and the DDR address bit.

If the in-line flash controller 120 and the tandem flash controller 140 are in continuous read mode (sometimes referred to as enhanced performance read mode), the command stages shown in FIGS. 6 through 11 may be omitted. . This is because the read command can be omitted from the read command in the above mode. In other words, the read instruction may only contain the address segment.

12 to 17 are signal timing diagrams transmitted between the in-line flash controller 120 and the tandem flash memory 140 shown in Fig. 1, which operate the method shown in Fig. 2. In the examples shown in FIGS. 12 to 14, the in-line flash controller 120 and the tandem flash memory 140 are The write operation is performed in the SPI mode, and the write operation includes the 8-bit command bit and the 24-bit address bit issued by the serial flash controller 120 and the at least 8-bit data bit provided by the serial flash controller 120. . In the example shown in FIGS. 15 to 17, the in-line flash controller 120 and the tandem flash memory 140 are performing a write operation in the QPI mode, and the write operation includes a tandem flash controller. 120 issued 8-bit command bit and 24-bit address bit and at least 1 data byte provided by the serial flash controller 120.

In the examples shown in Figures 12 and 15, the in-line flash controller 120 further transmits a latch signal generated by the controller during the data phase to ensure that the serial flash memory 140 can be locked at the correct timing. Store DDR data bits. In the examples shown in FIGS. 13 and 16, the in-line flash controller 120 further transmits a latch signal generated by the controller in the address phase and the data phase to ensure that the tandem flash memory 140 is available. The correct timing latches the DDR address bits and DDR data bits. In the examples shown in FIGS. 14 and 17, the serial flash controller 120 further transmits a latch signal generated by the controller in the command phase, the address phase, and the data phase to ensure that the serial memory 140 can be The DDR command bit, DDR address bit, and DDR data bit are latched at the correct timing.

If the in-line flash controller 120 and the serial flash controller 140 are in a continuous write mode (sometimes referred to as a boost performance write mode), the command stages shown in FIGS. 12 to 17 may be omitted. . This is because the write command can be omitted from the write command in the above mode. In other words, the write instruction can only include the address segment and the data segment.

In the above embodiments, the latch lines can be utilized to ensure synchronization. Even if the transmitted information bits do not match well with the SCK clock, the serial flash control The controller 120 or the in-line flash memory 140 can still utilize the latched signal as a basis for synchronization to latch the information bits at the correct timing. This allows the in-line flash controller 120 and the in-line flash memory 140 to operate reliably at high speeds or DDR.

The above is only the preferred embodiment of the present invention, and the present invention is not limited thereto, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Electronic devices

110‧‧‧ processor

120‧‧‧Inline flash controller

140‧‧‧ tandem flash memory

410‧‧‧SCK Block

430‧‧‧SCS Block

450‧‧‧SIO block

470‧‧‧Latch block

412‧‧‧clock generator

414, 434, 459, 475‧‧‧ output buffers

432‧‧‧ wafer selection processing unit

451‧‧‧ data transmitter

461‧‧‧ data receiver

469, 479‧‧‧ input buffer

452‧‧‧SDR processing unit

454‧‧‧DDR processing unit

456‧‧‧MUX

458‧‧‧Output control unit

471‧‧‧Data latch generation unit

473‧‧‧Output control unit

477‧‧‧Data latch receiving unit

510‧‧‧Command and Control Logic Blocks

520‧‧‧Status Recorder

530‧‧‧ address record counter

540‧‧‧High voltage generator

550‧‧‧ data buffer

560‧‧‧X decoder

570‧‧‧Y decoder

580‧‧‧Memory array

210, 220, 310, 320‧ ‧ steps

In the drawings, the same reference numerals are used to refer to the embodiments.

1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

Figure 2 is a schematic diagram showing how the tandem flash controller of Figure 1 utilizes a latch line to ensure synchronization.

Figure 3 is a schematic diagram showing how the tandem flash memory of Figure 1 utilizes a latch line to ensure synchronization.

Figure 4 is a schematic diagram of a tandem flash controller in accordance with an embodiment of the present invention.

Figure 5 is a schematic illustration of a tandem flash memory in accordance with an embodiment of the present invention.

Fig. 6 to Fig. 11 are signal timing diagrams sent between the serial flash controller and the tandem flash memory shown in Fig. 1.

Fig. 12 to Fig. 17 are signal timing diagrams transmitted between the in-line flash controller and the tandem flash memory shown in Fig. 1.

310, 320‧‧‧ steps

Claims (12)

A method performed by a tandem flash controller and a tandem flash memory, wherein the serial flash controller and the tandem flash memory comprise a serial clock line and a plurality of strings a columnar input/output line and a latch line interconnect, and the serial clock line carries a serial clock from the serial flash controller to the tandem flash memory, the serial The method of executing the flash controller and the tandem flash memory includes: transmitting the data bit synchronously from the serial flash memory through the plurality of serial input/output lines and the latch line respectively a latch signal generated by the memory to the serial flash controller; and allowing the serial flash controller to use the latch signal generated by the memory to replace the serial clock to latch through the plurality of The data bit received by the serial input/output line. The method of claim 1, wherein the tandem flash memory obtains the data bit from a memory array, as described in claim 1, wherein the tandem flash memory performs the method. In response to a read command issued by the serial flash controller, and the method performed by the serial flash controller and the tandem flash memory, the method further includes: staying in the data bit before transmitting A virtual phase is a predetermined number of cycles of the serial clock. The method of claim 1 , wherein the tandem flash memory obtains the data bit from a memory array, as described in claim 1 Responding to a read command issued by the serial flash controller, and the method performed by the tandem flash controller and the tandem flash memory further includes: Simultaneously transmitting at least a portion of the read command and a latch signal generated by a controller to the tandem by the plurality of serial input/output lines and the latch line respectively from the serial flash controller Flash memory; and allowing the serial flash memory to replace the serial clock with a latch signal generated by the controller to latch the at least one portion received through the plurality of serial input/output lines The read instruction. The method of performing the tandem flash controller and the tandem flash memory according to claim 3, further comprising: when the serial flash controller and the tandem flash memory The system allows the in-line flash controller to abandon and the in-line flash memory takes over control of the latch line in a virtual phase, wherein the virtual phase lasts for a predetermined number of cycles of the serial clock. A method performed by a tandem flash controller and a tandem flash memory, wherein the serial flash controller and the tandem flash memory comprise a serial clock line and a plurality of strings a columnar input/output line and a latch line interconnect, and the serial clock line carries a serial clock from the serial flash controller to the tandem flash memory, the serial The method of executing the flash controller and the tandem flash memory includes: synchronously transmitting the information bit from the serial flash controller through the plurality of serial input/output lines and the latch line respectively a latch signal generated by a controller to the serial flash memory; and allowing the serial flash memory to use the latch signal generated by the controller to replace the serial clock to latch through the plurality of The information bit received by the serial input/output line. Tandem flash controller as described in claim 5 And a method of performing tandem flash memory, wherein the information bit includes at least a portion of a read command issued by the serial flash controller, and the tandem flash controller and the tandem The method of flash memory execution further includes: after transmitting the read command, staying in a virtual phase for a predetermined number of cycles of the serial clock. The method of performing the tandem flash controller and the tandem flash memory as described in claim 6 further includes: after the virtual phase, transmitting the plurality of serial input/output lines Simultaneously transmitting, from the serial flash memory, a data bit and a latch signal generated by a memory to the serial flash controller, wherein the data bit is responsive to the read command; And allowing the serial flash controller to use the latch signal generated by the memory to replace the serial clock to latch the data bit received through the plurality of serial input/output lines. The method for performing the tandem flash controller and the tandem flash memory according to claim 7 of the patent application, further comprising: when the serial flash controller and the tandem flash memory The system allows the in-line flash controller to abandon and the in-line flash memory takes over control of the latch line during the virtual phase. A tandem flash controller, wherein the serial flash controller and a serial flash memory are mutually connected by a serial clock line, a plurality of serial input/output lines, and a latch line The serial flash controller includes: a serial clock block configured to pass the serial clock line to the The tandem flash memory transmits a serial clock; a serial input/output block configured to transmit information bits to the serial flash memory through the plurality of serial input/output lines And receiving, by the plurality of serial input/output lines, the data bit from the serial flash memory; and a latching block configured to transmit to the serial flash memory through the latch line a latch signal generated by a controller to synchronize with the serial flash memory to receive the information bit, or configured to receive a memory generated lock from the tandem flash memory through the latch line The signal is stored in synchronization with the data bit received by the latch through the plurality of serial input/output lines. The tandem flash controller of claim 9, wherein the string is configured before receiving the data bit from the serial flash memory through the plurality of serial input/output lines The column flash controller stays in a virtual phase for a predetermined number of cycles of the serial clock. A tandem flash memory, wherein the tandem flash memory and a tandem flash controller comprise a serial clock line, a plurality of serial input/output lines, and a latch line The serial flash memory includes: a memory array; and a command and control logic block connecting the serial clock line, the plurality of serial input/output lines, and the latch Line, configuring the command and control logic block as follows: receiving a serial clock from the serial flash controller through the serial clock line; Accessing the memory array by instructions received from the tandem flash controller through the plurality of serial input/output lines; and latching through the plurality of serial input/output lines from the serial An information bit received by the flash controller, the information bit being synchronized with a latch signal generated by a controller received through the latch line from the serial flash controller, or through the plurality of serials The input/output line and the latch line respectively send the data bit and the latch signal generated by a memory to the serial flash controller. The tandem flash memory of claim 11, wherein the string is configured after receiving a read command from the serial flash controller through the plurality of serial input/output lines The flash memory stays in a virtual phase for a predetermined number of cycles of the serial clock.