CN103123614B - The method of serial flash controller, serial flash and execution thereof - Google Patents
The method of serial flash controller, serial flash and execution thereof Download PDFInfo
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Abstract
A kind of method of serial flash controller, serial flash and execution thereof, wherein serial flash controller and serial flash are by serial time clock line, multiple serial input/output line and latch line and interconnect, and serial time clock line transports serial clock to serial flash from serial flash controller, and the method performed by serial flash controller and serial flash comprises: the latch signal produced from serial flash synchronized transmission data bit element and storer respectively by serial input/output line and latch line is to serial flash controller; And the latch signal allowing serial flash controller to utilize storer to produce replaces serial clock to latch the data bit element received by serial input/output line.The method of a kind of serial flash controller provided by the invention, serial flash and execution thereof can the transmission of information bit between synchronous serial flash memory and serial flash controller.
Description
Technical field
The present invention has about serial flash (serialflashmemory), and is particularly to utilize the serial flash of assisting synchronous latch line (latchline).
Background technology
Compared with paralleling flash memory (parallelflash), serial flash generally has less pin (pin), at circuit board (PrintedCircuitBoard, PCB) less area is taken on, consume less energy, be easier to control, and the cost of whole system can be reduced.Therefore, serial flash is widely used in various electronic installation, comprises portable electron device, such as mobile phone, desktop PC, portable media player, handheld game device or other devices.
Normally, serial clock (serialclock) communication between isochronous controller and serial flash that provides of serial flash controller (serialflashcontroller).In theory, controller is sent to the order of storer, address and data and should mates well with serial clock (well-aligned), thus guarantees that storer can latch this order, address and data in correct sequential.Similarly, the data being sent to controller by storer should be mated with serial clock equally well, to guarantee that controller can latch this data in correct sequential.
But, when serial flash controller and serial flash are at high speed or double data rate (DoubleDataRate, DDR), in situation, may there is the delay to serial clock edge in the information bit (informationbit) sent between above-mentioned two assemblies.Sometimes the one-period of above-mentioned retardation ratio serial clock also will be grown.Postpone as long as exist, storer can not latches command, address and/or data, it correctly receives from controller based on serial clock.Similarly, postpone as long as exist, controller can not latch the data correctly received from storer based on serial clock.
Summary of the invention
In view of this, the invention provides a kind of method of serial flash controller, serial flash and execution thereof.
A kind of method performed by serial flash controller and serial flash, wherein this serial flash controller and this serial flash are by serial time clock line, multiple serial input/output line and latch line and interconnect, and this serial time clock line transports serial clock to this serial flash from this serial flash controller, and the method comprises: the latch signal produced from this serial flash synchronized transmission data bit element and storer respectively by this serial input/output line and this latch line is to this serial flash controller; And the latch signal allowing this serial flash controller to utilize this storer to produce replaces this serial clock to latch this data bit element received by this serial input/output line.
A kind of method performed by serial flash controller and serial flash, wherein this serial flash controller and this serial flash are by serial time clock line, multiple serial input/output line and latch line and interconnect, and this serial time clock line transports serial clock to this serial flash from this serial flash controller, and the method that this serial flash controller and serial flash perform comprises: the latch signal produced from this serial flash controller synchronized transmission information bit and controller respectively by this serial input/output line and this latch line is to this serial flash; And the latch signal allowing this serial flash to utilize this controller to produce replaces this serial clock to latch this information bit received by this serial input/output line.
A kind of serial flash controller, wherein this serial flash controller and serial flash are by serial time clock line, multiple serial input/output line and latch line and interconnect, this serial flash controller comprises: serial clock module, is configured to send serial clock by this this serial flash of serial clock alignment; Serial input/output module, be configured to by this serial input/output line to this serial flash send information bit and by this serial input/output line from this serial flash receive data bit element; And latch module, be configured to the latch signal produced by this serial flash transmit control device of this latch alignment, thus with this serial flash, to receive this information bit synchronous, or be configured to the latch signal produced from this serial flash reception memorizer by this latch line, thus synchronous with latching this data bit element received by this serial input/output line.
A kind of serial flash, wherein this serial flash and serial flash controller are by serial time clock line, multiple serial input/output line and latch line and interconnect, and this serial flash comprises: memory array; And order and steering logic module, it connects this serial time clock line, the plurality of serial input/output line and this latch line, configures this order and steering logic module is as follows: receive serial clock by this serial time clock line from this serial flash controller; According to this memory array of instruction accessing received from this serial flash controller by this serial flash input/output line; And latch the information bit received from this serial flash controller by this serial input/output line, this information bit is synchronous with the latch signal produced from the controller that this serial flash controller receives by this latch line, or by latch signal that this serial input/output line and this latch line produce respectively to this serial flash controller synchronized transmission data bit element and storer.
The method of a kind of serial flash controller provided by the invention, serial flash and execution thereof can the transmission of information bit between synchronous serial flash memory and serial flash controller.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the electronic installation according to embodiment of the present invention description.
Fig. 2 is how the serial flash controller described in Fig. 1 utilizes latch line to guarantee synchronous method schematic diagram.
Fig. 3 is how the serial flash described in Fig. 1 utilizes latch line to guarantee synchronous method schematic diagram.
Fig. 4 is the schematic diagram of the serial flash controller according to embodiment of the present invention description.
Fig. 5 is the schematic diagram of the serial flash according to embodiment of the present invention description.
The signal timing diagram that Fig. 6 to Figure 11 is the serial flash controller shown in Fig. 1 and sends between serial flash.
The signal timing diagram that Figure 12 to Figure 17 is the serial flash controller shown in Fig. 1 and sends between serial flash.
Embodiment
Some vocabulary is employed to censure specific element in the middle of instructions and claims.Person of ordinary skill in the field should understand, and hardware manufacturer may call same element with different nouns.This specification and claims book not using the difference of title as the mode of distinguish one element from another, but using element difference functionally as the criterion distinguished." comprising " mentioned in instructions and claim is in the whole text an open term, therefore should be construed to " comprise but be not limited to ".In addition, " couple " word comprise directly any at this and be indirectly electrically connected means.Therefore, if describe first device in literary composition to be coupled to the second device, then represent first device and can directly be electrically connected in the second device, or be indirectly electrically connected to the second device through other device or connection means.
Ensuing description is about embodiments of the invention, and it is in order to describe ultimate principle of the present invention, not as limitation of the present invention.Protection scope of the present invention is made by claims and being defined.
Fig. 1 is the schematic diagram of the electronic installation 100 according to embodiment of the present invention description.Electronic installation 100 can be mobile phone, desktop PC, portable media player or handheld game device.Fig. 1 only describes the processor 110 of electronic installation 100, serial flash controller 120 and serial flash 140, simplifies other assemblies eliminating electronic installation 100.The storage space that serial flash controller 120 and processor 110 interconnect to provide serial flash 140 to processor 110.Being connected between processor 110 with serial flash controller 120 can comprise many parallel lines (parallelline), and in order to the object simplified, Fig. 1 is also omitted.
Serial flash controller 120 and serial flash 140 are by the serial clock (SerialClock in other lines, SCK) line, serial chip select (SerialChipSelect, SCS) line and many serial input/output (SerialInput/Output, SIO) lines.Particularly, there are 4 SIO lines in the present embodiment, it comprises SIO [0], SIO [1], SIO [2], SIO [3].SCK line transports SCK clock to serial flash 140 the communication between two assemblies to be carried out synchronously from serial flash controller 120.SCS line also can be described as serial chip enable (SerialChipEnable, SCE) line, and it transports SCS(or SCE from serial flash controller 120) signal is to serial flash 140.When can and when cannot communicate between above-mentioned two assemblies of SCS signal designation.SIO line transports information bit to serial flash 140 from serial flash controller 120, and vice versa.Such as, information bit can comprise order bit, address bit, data bit element or its combination.
Except above-mentioned line, serial flash controller 120 and serial flash 140 can interconnect further by latching line.As long as an assembly in two assemblies controls, then latching line is unidirectional line (unidirectionalline); If two assemblies all carry out controlling, latching line is bidirectional lines (bidirectionalline).This latch line of hypothesis is bidirectional lines by paragraph below.
When serial flash 140 operates at low speed or single data transfer rate (SingleDataRate, SDR) (speed of SCK clock), latch line and can be inactive, such as, (floating) that float.Particularly, when serial flash 140 operates at low speed or SDR, the information bit sent by SIO should well with SCK clock matches.Therefore, independent SCK clock can be enough to the transmission of information bit between synchronous serial flash memory 140 and serial flash controller 120.Therefore, above-mentioned two assemblies can be avoided utilizing in addition and latch line to assist synchronously.
On the contrary, when serial flash 140 operate when at a high speed or DDR (namely speed doubles SCK clock), the clock skew (clockskew) between the information bit sent by SIO line and the online SCK clock of SCK may be very large.Due to clock skew, SCK clock can not complete synchronous operation preferably.In other words, when serial flash 140 operates in high speed or DDR, the edge of SCK clock correctly can not indicate beginning and the end of the information bit sent by SIO line.In order to solve the problem, when serial flash 140 operate when at a high speed or DDR, serial flash 140 and serial flash controller 120 can utilize further and latch line and assist synchronous.
Fig. 2 is how the serial flash controller 120 described in Fig. 1 utilizes latch line to guarantee synchronous method schematic diagram.In step 210, information bit is synchronously sent to serial flash 140 by SIO line and by latching line, the latch signal that controller produces (controller-generated) is sent to serial flash 140 by serial flash controller 120.Information bit can form complete instruction (instruction) or part instructs, and therefore it comprises order bit, address bit, data bit element or its combination.Such as, instruction can be comprise read command read instruction, or omit read command read instruction.
In step 220, the latch signal that serial flash 140 utilizes controller to produce is to latch the information bit received by SIO line.Particularly, in this step serial flash 140 utilize controller to produce latch signal as synchronous basis, to replace utilizing SCK clock to latch the information bit received by SIO line.Because may clock skew be there is between SCK clock and information bit, and the latch signal that controller produces can match information bit preferably, so the latch signal that serial flash 140 utilizes controller to produce can latch the information bit of SIO line more accurately as synchronous basis.
Before the latch signal sending controller generation, serial flash controller 120 needs adapter to the control of latching line, such as, by latch line is changed into high state/low state from quick condition.After the latch signal completing transmit control device generation, serial flash controller 120 needs to abandon the control to latching line, such as, by latch line is changed into quick condition from high state/low state.Read instruction if the information bit of the latch signal synchronized transmission produced with controller is formed or partly read instruction, then after sending and reading instruction, serial flash controller 120 and serial flash 140 will treat the cycle waiting for the SCK clock of predetermined quantity in simulation stage (dummyphase).The control to latching line can be abandoned at this simulation stage serial flash controller 120.
If information bit only comprises a part for instruction, namely a part for the latch signal that produces of controller only and instruction is overlapping, then serial flash 140 latch signal that controller can be utilized to produce is first and utilize the remainder of SCK clock synchronous latch instruction synchronously to latch information bit.Such as, instruction can comprise SDR section and DDR section, and information bit only can comprise the partly overlapping DDR section of the latch signal produced with controller.
Fig. 3 is how the serial flash 140 described in Fig. 1 utilizes latch line to guarantee synchronous method schematic diagram.In step 310, information bit is synchronously sent to serial flash controller 120 by SIO line and by latching line, the latch signal that storer produces (memory-generated) is sent to serial flash controller 120 by serial flash 140.Such as, information bit can comprise the data bit element extracted from serial flash 140, reads instruction with what respond that serial flash controller 120 sends.
In step 320, the latch signal that serial flash controller 120 utilizes storer to produce is to latch the information bit received by SIO line.Particularly, in this step serial flash controller 120 utilize storer to produce latch signal as synchronous basis, to replace utilizing SCK clock to latch the information bit received by SIO line.Because may clock skew be there is between SCK clock and information bit, and the latch signal that storer produces can match information bit preferably, so the latch signal that serial flash controller 120 utilizes storer to produce can latch the information bit of SIO line more accurately as synchronous basis.
Before the latch signal sending storer generation, serial flash 140 needs adapter to the control of latching line, such as, by latch line is changed into high state/low state from quick condition.After completing the latch signal sending storer generation, serial flash 140 needs to abandon the control to latching line, such as, by latch line is changed into quick condition from high state/low state.If the signal bits obtaining the latch signal synchronized transmission produced with storer reads instruction to respond, serial flash controller 120 and serial flash 140 will treat the cycle waiting for the SCK clock of predetermined quantity in simulation stage.The control to latching line can be abandoned at this simulation stage serial flash 140.
Although the method schematic diagram shown in Fig. 2 and Fig. 3 is independent of each other, those skilled in the art still operate the executable operations of serial flash module by both combinations, wherein this operation two kinds of relating between serial flash controller 120 with serial flash 140 communicate (such as read operation).
Fig. 4 is the schematic diagram describing serial flash controller 120 according to the embodiment of the present invention.In the present embodiment, serial flash controller 120 comprises SCK module 410, SCS module 430, SIO module 450 and latch module 470.
SCK module 410 is responsible for sending SCK clock continuously to SCK line, and it comprises clock generator 412 and output buffer 414, and wherein output buffer 414 is as the center section between clock generator 412 and SCK line.Clock generator 412 is based on CLKin clock generating SCK clock, and wherein this CLKin is provided by oscillator (oscillator).SCS module 430 is responsible for sending SCS signal to SCS line, such as, no matter when allows the communication between serial flash controller 120 and serial flash 140, completes by maintaining SCS signal when low state/high state.SCS module 430 comprises chip selection processing unit 432 and output buffer 434, and wherein output buffer 434 is as the center section between chip selection processing unit 432 and SCS line.
SIO module 450 comprises data transmitter 451, output buffer 459, data receiver 461 and input buffer 469, wherein output buffer 459 is as the center section between data transmitter 451 and SIO line, and input buffer 469 is as the center section between data receiver 461 and SIO line.Utilize data transmitter 451 and output buffer 459, SIO module 450 sends information bit by SIO alignment serial flash 140, and wherein information bit and the controller that SCK clock or latch module 470 produce produce latch clock synchronous (controller produces the latch signal that latch clock produced by controller and indicates).Utilize data receiver 461 and input buffer 469, SIO module 450 latches the information bit received from serial flash 140 by SIO line, wherein information bit and SCK clock or latch module 470 produce latch clock synchronous (storer produces the latch signal that latch clock produced by storer and indicates) by the storer latching line and receive.Then, data receiver 461 utilizes signal RDATA_IN to send the information bit latched to processor 110, and signal RDATA_IN can be parallel signal.
Data transmitter 451 comprises SDR processing unit 452, DDR processing unit 454, multiplexer (Multiplexer, MUX) 456 and output control unit 458.When data transmitter 451 operates, its signal OUTPUT_DATA_EN provided for processor 110 of MUX456(controls) allow information bit to be sent to serial flash 140 by SIO with output buffer 459, wherein to produce latch clock synchronous for information bit and SCK clock or controller, and wherein information bit is produced by SDR processing unit 452 or DDR processing unit 454.
Latch module 470 comprises latches data generation unit 471, output control unit 473, output buffer 475, latches data receiving element 477 and input buffer 479.When serial flash 140 at low speed or SDR operate, latch module 470 is inactive; When serial flash 140 when at a high speed or DDR operate, latch module 470 be activity.Particularly, when SIO module 450 at a high speed or DDR when serially flash memory 140 sends information bit time, latches data generation unit 471 can produce the latch signal that controller produces in addition.Output control unit 473 and output buffer 475 guarantee that the latch signal that the information bit that sent by SIO line and controller are produced is synchronous.When SIO module 450 at a high speed or DDR when receive information bit from serial flash 140 time, the latch signal that input buffer 479 produces from serial flash 140 reception memorizer by latching line.Latches data receiving element 477 can control data receiver 461 to latch the information bit that by SIO line received synchronous with the latch signal that storer produces.The signal RDATA_EN that latches data receiving element 477 can be provided by processor 110 controls.
Fig. 5 is the schematic diagram of the serial flash 140 according to embodiment of the present invention description.In the present embodiment, serial flash 140 comprises order and steering logic module 510, state recording device (statusregister) 520, address recording counter 530, high voltage generator 540, data buffer 550, X code translator 560, Y code translator 570 and memory array 580.Order and steering logic module 510 receive instruction from serial flash controller 120 and correspondingly control the running of serial flash 140.State recording device 520 records the treatment state of serial flash 140.The data bit element received from order and steering logic module 510 is write memory array 580 by data buffer 550, or obtains data with steering logic module 510 from memory array 580 for ordering.Utilize address recording counter 530, high voltage generator 540, X code translator 560 and Y code translator 570, order and steering logic module 510 can write data bit element or obtain data bit element from the correct physical address of memory array 580.
When order with steering logic module 510 at a high speed or DDR when receive information bit from serial flash controller 120 time, it can receive the latch signal that controller produces in addition.Then, order and steering logic module 510 latch signal that controller can be utilized to produce are synchronously to latch the information bit received by SIO line.When order with steering logic module 510 at a high speed or DDR when serially flash controller 120 sends data bit element time, it can send latch signal that storer produces in addition and obtain data bit element to help serial flash controller 120 in correct sequential.
The signal timing diagram that Fig. 6 to Figure 11 is the serial flash controller 120 shown in Fig. 1 and sends between serial flash 140, it operates the method shown in Fig. 2 or Fig. 3.In example shown in Fig. 6 to Fig. 8, serial flash controller 120 and serial flash 140 are just at Serial Peripheral Interface (SPI) (SerialPeripheralInterface, SPI) perform read operation under pattern, and read operation comprises at least 8 bit data bits that 8 order of the bit bits and 24 bit address bits that serial flash controller 120 issues, the simulation stage of lasting 18 SCK clock period and serial flash 140 return.In example shown in Fig. 9 to Figure 11, serial flash controller 120 and serial flash 140 are just at quaternary Peripheral Interface (QuadPeripheralInterface, QPI) perform read operation under pattern, and read operation comprises at least 1 data byte (byteofdata) that 8 order of the bit bits and 24 bit address bits that serial flash controller 120 issues, the simulation stage of lasting 18 SCK clock period and serial flash 140 return.Note that Fig. 6 to Figure 11 only describes the delay between data bit element and SCK clock, do not describe the delay between order (and/or address) bit and SCK clock.The stage of above-mentioned delay be uncertain and pattern more, therefore, SCK clock is not synchronous ideal basic.
In example shown in Fig. 6 to Figure 11, serial flash 140 sends the latch signal of storer generation further to guarantee that serial flash controller 120 can latch DDR data bit element in correct sequential at data phase.In addition, in the example shown in Fig. 7 and Figure 10, the latch signal that serial flash controller 120 produces at address phase transmit control device is further to guarantee that serial flash 140 can latch DDR address bit in correct sequential.In example shown in Fig. 8 and Figure 11, serial flash controller 120 further command phase and address phase all the latch signal that produces of transmit control device to guarantee that serial storage 140 can latch DDR order bit and DDR address bit in correct sequential.
If serial flash controller 120 and serial flash controller 140 are under continuous reading mode (being sometimes referred to as enhancement mode reading mode), then the command phase shown in Fig. 6 to Figure 11 can omit.So because read command can from reading to omit instruction under above-mentioned pattern.In other words, read instruction and can only comprise address section.
The signal timing diagram that Figure 12 to Figure 17 is the serial flash controller 120 shown in Fig. 1 and sends between serial flash 140, it operates the method shown in Fig. 2.In example shown in Figure 12 to Figure 14, serial flash controller 120 and serial flash 140 perform write operation just in the spi mode, and write operation comprises 8 order of the bit bits and 24 bit address bits that serial flash controller 120 issues and at least 8 bit data bits that serial flash controller 120 provides.In example shown in Figure 15 to Figure 17, serial flash controller 120 and serial flash 140 just perform write operation under QPI pattern, and write operation comprises 8 order of the bit bits and 24 bit address bits that serial flash controller 120 issues and at least 1 data byte that serial flash controller 120 provides.
In example shown in Figure 12 and Figure 15, the latch signal that serial flash controller 120 produces at data phase transmit control device is further to guarantee that serial flash 140 can latch DDR data bit element in correct sequential.In example shown in Figure 13 and Figure 16, the latch signal that serial flash controller 120 produces at address phase and data phase transmit control device is further to guarantee that serial flash 140 can latch DDR address bit and DDR data bit element in correct sequential.In example shown in Figure 14 and Figure 17, the latch signal that serial flash controller 120 produces at command phase, address phase and data phase transmit control device is further to guarantee that serial storage 140 can latch DDR order bit, DDR address bit and DDR data bit element in correct sequential.
If serial flash controller 120 and serial flash controller 140 are under continuous WriteMode (being sometimes referred to as enhanced write pattern), then the command phase shown in Figure 12 to Figure 17 can omit.So because write order can omit from write command under above-mentioned pattern.In other words, write command can only comprise address section and data segments.
In above embodiment, latch line all can be utilized to guarantee synchronously.Even if the information bit sent can not mate well with SCK clock, serial flash controller 120 or serial flash 140 still can utilize latch signal as synchronous foundation with at correct sequential latch information bit.Serial flash controller 120 and serial flash 140 can be allowed so reliably to operate when high speed or DDR.
Though the present invention discloses as above with preferred embodiment, but itself and be not used to limit scope of the present invention, any person that is familiar with technique, without departing from the spirit and scope of the present invention, do impartial change and modification, all belong to covering scope of the present invention.
Claims (12)
1. the method performed by serial flash controller and serial flash, wherein this serial flash controller and this serial flash latch line by serial time clock line, multiple serial input/output line and one and interconnect, and this serial time clock line transports serial clock to this serial flash from this serial flash controller, and the method that should be performed by serial flash controller and serial flash comprises:
Send data bit element by the plurality of serial input/output line from this serial flash, and synchronously send the latch signal of storer generation to this serial flash controller by this latch line; And
The latch signal allowing this serial flash controller to utilize this storer to produce replaces this serial clock to latch this data bit element received by the plurality of serial input/output line.
2. the method performed by serial flash controller and serial flash as claimed in claim 1, it is characterized in that, this serial flash from memory array obtain this data bit element with response issued by this serial flash controller read instruction, and the method that this serial flash controller and serial flash perform comprises further: before sending this data bit element, rest on the cycle of this serial clock of simulation stage predetermined quantity.
3. the method performed by serial flash controller and serial flash as claimed in claim 1, it is characterized in that, this serial flash from memory array obtain this data bit element with response issued by this serial flash controller read instruction, and the method that this serial flash controller and serial flash perform comprises further: by the plurality of serial input/output line from this serial flash controller send at least partially this read instruction, and the latch signal synchronously produced by this latch line transmit control device is to this serial flash; And the latch signal allowing this serial flash to utilize this controller to produce replaces this serial clock to read instruction to latch this at least partially this received by the plurality of serial input/output line.
4. the method performed by serial flash controller and serial flash as claimed in claim 3, comprise further: when this serial flash controller and this serial flash are in simulation stage, allow this serial flash controller to abandon and this latch line of this serial flash adapter control, wherein this simulation stage continues the prearranged multiple in the cycle of this serial clock.
5. the method performed by serial flash controller and serial flash, wherein this serial flash controller and this serial flash latch line by serial time clock line, multiple serial input/output line and one and interconnect, and this serial time clock line transports serial clock to this serial flash from this serial flash controller, and the method that should be performed by serial flash controller and serial flash comprises:
Send information bit by the plurality of serial input/output line from this serial flash controller, and the latch signal synchronously produced by this latch line transmit control device is to this serial flash; And
The latch signal allowing this serial flash to utilize this controller to produce replaces this serial clock to latch this information bit received by the plurality of serial input/output line.
6. the method performed by serial flash controller and serial flash as claimed in claim 5, it is characterized in that, this information bit comprise this serial flash controller issue read instruction at least partially, and the method that this serial flash controller and serial flash perform comprises further: sending after this reads instruction, rest on the cycle of this serial clock of simulation stage predetermined quantity.
7. the method performed by serial flash controller and serial flash as claimed in claim 6, comprise further: after this simulation stage, data bit element is sent from this serial flash by the plurality of serial input/output line, and synchronously send the latch signal of storer generation to this serial flash controller by this latch line, wherein this data bit element responds this and reads instruction; And the latch signal allowing this serial flash controller to utilize this storer to produce replaces this serial clock to latch this data bit element received by the plurality of serial input/output line.
8. the method performed by serial flash controller and serial flash as claimed in claim 7, comprise further: when this serial flash controller and this serial flash are in this simulation stage, allow this serial flash controller to abandon and this latch line of this serial flash adapter control.
9. a serial flash controller, wherein this serial flash controller and serial flash latch line by serial time clock line, multiple serial input/output line and one and interconnect, and this serial flash controller comprises:
Serial clock module, is configured to send serial clock by this this serial flash of serial clock alignment;
Serial input/output module, be configured to by the plurality of serial input/output line to this serial flash send information bit and by the plurality of serial input/output line from this serial flash receive data bit element; And
Latch module, be configured to the latch signal produced by this serial flash transmit control device of this latch alignment, thus with this serial flash, to receive this information bit synchronous, or be configured to the latch signal produced from this serial flash reception memorizer by this latch line, thus synchronous with latching this data bit element received by the plurality of serial input/output line.
10. serial flash controller as claimed in claim 9, it is characterized in that, before receiving this data bit element by the plurality of serial input/output line from this serial flash, configure the cycle that this serial flash controller rests on this serial clock of simulation stage predetermined quantity.
11. 1 kinds of serial flash, wherein this serial flash and serial flash controller latch line by serial time clock line, multiple serial input/output line and one and interconnect, and this serial flash comprises:
Memory array; And
Order and steering logic module, connect this serial time clock line, the plurality of serial input/output line and this latch line, configure this order and steering logic module is as follows:
Serial clock is received from this serial flash controller by this serial time clock line;
According to this memory array of instruction accessing received from this serial flash controller by this serial flash input/output line; And
Latch the information bit received from this serial flash controller by the plurality of serial input/output line, this information bit is synchronous with the latch signal produced from the controller that this serial flash controller receives by this latch line, or send data bit element by the plurality of serial input/output line to this serial flash controller, and synchronously sent the latch signal of storer generation by this latch line.
12. serial flash as claimed in claim 11, is characterized in that, after reading instruction by the plurality of serial input/output line from the reception of this serial flash controller, configure the cycle that this serial flash rests on this serial clock of simulation stage predetermined quantity.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| US201161535477P | 2011-09-16 | 2011-09-16 | |
| US61/535,477 | 2011-09-16 | ||
| BR102012008776A BR102012008776A8 (en) | 2012-04-13 | 2012-04-13 | SERIAL FLASH CONTROLLER, SERIAL FLASH MEMORY, AND METHOD THEREOF |
| BR1020120087766 | 2012-04-13 |
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| CN103123614A CN103123614A (en) | 2013-05-29 |
| CN103123614B true CN103123614B (en) | 2016-01-20 |
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| CN201210332366.XA Expired - Fee Related CN103123614B (en) | 2011-09-16 | 2012-09-10 | The method of serial flash controller, serial flash and execution thereof |
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| CN (1) | CN103123614B (en) |
| BR (1) | BR102012008776A8 (en) |
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| US9514088B2 (en) * | 2014-09-24 | 2016-12-06 | Macronix International Co., Ltd. | Method and device for processing serial binary input by comparing binary digits at even and odd locations of the input |
| CN111008171B (en) * | 2019-11-25 | 2020-12-22 | 中国兵器工业集团第二一四研究所苏州研发中心 | Communication IP circuit with serial FLASH interface control |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010094068A (en) * | 2000-04-03 | 2001-10-31 | 강재철 | Hardware device for the data protection of personal computer which includes control driver program for data encryption, decryption and I/O devices(USB, printer port, serial port, FDD, etc.) |
| US6816420B1 (en) * | 2003-07-29 | 2004-11-09 | Xilinx, Inc. | Column redundancy scheme for serially programmable integrated circuits |
| CN1790548A (en) * | 2004-12-17 | 2006-06-21 | 三星电子株式会社 | Flash memory data storage apparatus |
| CN101677019A (en) * | 2008-09-18 | 2010-03-24 | 深圳市朗科科技股份有限公司 | Production line reading method and system of flash memory |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7475174B2 (en) * | 2004-03-17 | 2009-01-06 | Super Talent Electronics, Inc. | Flash / phase-change memory in multi-ring topology using serial-link packet interface |
| US8996784B2 (en) * | 2006-03-09 | 2015-03-31 | Mediatek Inc. | Command controller, prefetch buffer and methods for accessing a serial flash in an embedded system |
| US20070260778A1 (en) * | 2006-04-04 | 2007-11-08 | Ming-Shiang Lai | Memory controller with bi-directional buffer for achieving high speed capability and related method thereof |
| TWI351606B (en) * | 2007-10-26 | 2011-11-01 | Sunplus Technology Co Ltd | Memory module and control method of serial periphe |
-
2012
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010094068A (en) * | 2000-04-03 | 2001-10-31 | 강재철 | Hardware device for the data protection of personal computer which includes control driver program for data encryption, decryption and I/O devices(USB, printer port, serial port, FDD, etc.) |
| US6816420B1 (en) * | 2003-07-29 | 2004-11-09 | Xilinx, Inc. | Column redundancy scheme for serially programmable integrated circuits |
| CN1790548A (en) * | 2004-12-17 | 2006-06-21 | 三星电子株式会社 | Flash memory data storage apparatus |
| CN101677019A (en) * | 2008-09-18 | 2010-03-24 | 深圳市朗科科技股份有限公司 | Production line reading method and system of flash memory |
Non-Patent Citations (1)
| Title |
|---|
| 基于固态硬盘的闪存阵列并行结构设计;李佳琦;《微电子学与计算机》;20100430;第27卷(第4期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103123614A (en) | 2013-05-29 |
| BR102012008776A8 (en) | 2016-12-13 |
| TW201342379A (en) | 2013-10-16 |
| BR102012008776A2 (en) | 2013-11-26 |
| TWI488184B (en) | 2015-06-11 |
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