CN103123614A - Serial flash memory controller, serial flash memory and execution method thereof - Google Patents
Serial flash memory controller, serial flash memory and execution method thereof Download PDFInfo
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Abstract
The invention relates to a serial flash memory controller, a serial flash memory and an execution method thereof. The serial flash memory controller and the serial flash memory are connected via a serial clock line, a plurality of serial input/output lines and a latching line, and the serial clock line conveys a serial clock from the serial flash memory controller to the serial flash memory. The execution method of the serial flash memory controller and the serial flash memory comprises the steps of synchronously sending data bits and a latching signal generated by a memorizer to the serial flash memory controller from the serial flash memory via the serial input/output lines, and permitting the serial flash memory controller to utilize the latching signal generated by the memorizer to substitute the serial clock to thereby latch the data bits received by the serial input/output lines. The invention provides the serial flash memory controller, the serial flash memory and the execution method thereof, so that the sending of information bits between the serial flash memory controller and the serial flash memory can be synchronized.
Description
Technical field
The present invention is relevant for serial flash (serial flash memory), and is particularly to utilize and assists the synchronous serial flash that latchs line (latch line).
Background technology
(parallel flash) compares with paralleling flash memory, and serial flash generally has less pin (pin), at circuit board (Printed Circuit Board, PCB) take less area on, consume less energy, be easier to control, and the cost that can reduce whole system.Therefore, serial flash is widely used in various electronic installations, comprises portable electron device, for example mobile phone, desktop PC, portable media player, handheld game device or other devices.
Normally, communicating by letter between serial clock (serial clock) isochronous controller that provides of serial flash controller (serial flash controller) and serial flash.In theory, order, address and data that controller is sent to storer should be mated well with serial clock (well-aligned), thereby guarantee that storer can latch in correct sequential this order, address and data.Similarly, the data that are sent to controller by storer should be mated well with serial clock equally, can latch in correct sequential this data to guarantee controller.
Yet, when serial flash controller and serial flash at a high speed or double data rate (Double Data Rate, DDR) in situation, the delay to the serial clock edge may appear in the information bit (information bit) that sends between above-mentioned two assemblies.Sometimes the one-period of above-mentioned retardation ratio serial clock also will be grown.As long as exist to postpone, storer can not latches command, address and/or data, and it correctly receives from controller based on serial clock.Similarly, postpone as long as exist, controller can not latch based on serial clock from the correct data that receive of storer.
Summary of the invention
In view of this, the invention provides a kind of method of serial flash controller, serial flash and execution thereof.
A kind of method of being carried out by serial flash controller and serial flash, wherein this serial flash controller and this serial flash are by serial time clock line, a plurality of serial input/output line and latch line interconnection, and this serial time clock line transports serial clock to this serial flash from this serial flash controller, and the method comprises: latch latch signal that line produces from this serial flash synchronized transmission data bit element and storer respectively to this serial flash controller by this serial input/output line and this; And the latch signal that allows this serial flash controller to utilize this storer to produce replaces this serial clock to latch this data bit element that receives by this serial input/output line.
A kind of method of being carried out by serial flash controller and serial flash, wherein this serial flash controller and this serial flash are by serial time clock line, a plurality of serial input/output line and latch line interconnection, and this serial time clock line transports serial clock to this serial flash from this serial flash controller, and the method that this serial flash controller and serial flash are carried out comprises: latch line respectively from the latch signal of this serial flash controller synchronized transmission information bit and controller generation to this serial flash by this serial input/output line and this; And the latch signal that allows this serial flash to utilize this controller to produce replaces this serial clock to latch this information bit that receives by this serial input/output line.
A kind of serial flash controller, wherein this serial flash controller and serial flash are by serial time clock line, a plurality of serial input/output line and latch line interconnection, this serial flash controller comprises: the serial clock module is configured to send serial clock by this serial flash of this serial clock alignment; Serial input/output module is configured to send the information bit and pass through this serial input/output line from this serial flash receive data bit to this serial flash by this serial input/output line; And latch module, be configured to latch by this latch signal that this serial flash transmit control device of alignment produces, thereby receiving this information bit with this serial flash synchronizes, perhaps be configured to latch by this latch signal that line produces from this serial flash reception memorizer, thereby synchronize with this data bit element that latchs by this serial input/output line reception.
A kind of serial flash, wherein this serial flash and serial flash controller are by serial time clock line, a plurality of serial input/output line and latch line interconnection, and this serial flash comprises: memory array; And order and steering logic module, it connects this serial time clock line, these a plurality of serial input/output lines and this latchs line, configures this order and the steering logic module is as follows: receive serial clock by this serial time clock line from this serial flash controller; According to this memory array of instruction accessing that receives from this serial flash controller by this serial flash input/output line; And latch by the information bit of this serial input/output line from this serial flash controller reception, this information bit with latch the latch signal that controller that line receives from this serial flash controller produces by this and synchronize, perhaps latch line respectively to the latch signal of this serial flash controller synchronized transmission data bit element and storer generation by this serial input/output line and this.
But the transmission of information bit between the method synchronous serial flash memory of a kind of serial flash controller provided by the invention, serial flash and execution thereof and serial flash controller.
Description of drawings
Fig. 1 is the schematic diagram according to the electronic installation of embodiment of the present invention description.
Fig. 2 describes serial flash controller in Fig. 1 how to utilize and latch line and guarantee synchronous method schematic diagram.
Fig. 3 describes serial flash in Fig. 1 how to utilize and latch line and guarantee synchronous method schematic diagram.
Fig. 4 is the schematic diagram according to the serial flash controller of embodiment of the present invention description.
Fig. 5 is the schematic diagram according to the serial flash of embodiment of the present invention description.
Fig. 6 to Figure 11 is the signal timing diagram that sends between serial flash controller shown in Figure 1 and serial flash.
Figure 12 to Figure 17 is the signal timing diagram that sends between serial flash controller shown in Figure 1 and serial flash.
Embodiment
Used some vocabulary to censure specific element in the middle of instructions and claims.The person of ordinary skill in the field should understand, and hardware manufacturer may be called same element with different nouns.This specification and claims book not with the difference of title as the mode of distinguishing element, but with element the difference on function as the criterion of distinguishing.In instructions and claim, be an open term mentioned " comprising " in the whole text, therefore should be construed to " comprise but be not limited to ".In addition, " couple " word and comprise any means that indirectly are electrically connected that directly reach at this.Therefore, be coupled to the second device if describe first device in literary composition, represent that first device can directly be electrically connected in the second device, or indirectly be electrically connected to the second device through other device or connection means.
Ensuing description is about embodiments of the invention, and it is in order to describe ultimate principle of the present invention, not as limitation of the present invention.Protection scope of the present invention is made by claims and being defined.
Fig. 1 is the schematic diagram according to the electronic installation 100 of embodiment of the present invention description.Electronic installation 100 can be mobile phone, desktop PC, portable media player or handheld game device.Fig. 1 has only described processor 110, serial flash controller 120 and the serial flash 140 of electronic installation 100, simplifies other assemblies that omitted electronic installation 100.Serial flash controller 120 interconnects so that the storage space of serial flash 140 to be provided to processor 110 with processor 110.Being connected between processor 110 and serial flash controller 120 can comprise many parallel lines (parallel line), and for the purpose of simplifying, Fig. 1 is also with its omission.
Except above-mentioned line, serial flash controller 120 can further interconnect by latching line with serial flash 140.An assembly that needs only in two assemblies is controlled, and latching line is unidirectional line (unidirectional line); If two assemblies are all controlled latched line is bidirectional lines (bidirectional line).Paragraph below will suppose that this latchs line is bidirectional lines.
When serial flash 140 running in the situation that low speed or single data transfer rate (Single Data Rate, SDR) (being the speed of SCK clock), latch line can be inactive, for example, (floating) that floats.Particularly, in the situation that low speed or SDR, the information bit that sends by SIO should mate with the SCK clock well when serial flash 140 running.Therefore, independent SCK clock can be enough to the transmission of information bit between synchronous serial flash memory 140 and serial flash controller 120.Therefore, above-mentioned two assemblies can be avoided utilizing in addition and latch line to assist synchronously.
On the contrary, in the situation that at a high speed or DDR (being that speed doubles the SCK clock), the clock skew (clock skew) between the online SCK clock of the information bit that sends by the SIO line and SCK may be very large when serial flash 140 running.Due to clock skew, the SCK clock can not be completed synchronous operation preferably.In other words, in the situation that at a high speed or DDR, beginning and the end of the information bit that sends by the SIO line can not be correctly indicated at the edge of SCK clock when serial flash 140 running.In order to address the above problem, in the situation that at a high speed or DDR, serial flash 140 and serial flash controller 120 can further utilize and latch line assistance and synchronize when serial flash 140 runnings.
Fig. 2 describes serial flash controller 120 in Fig. 1 how to utilize and latch line and guarantee synchronous method schematic diagram.In step 210, serial flash controller 120 synchronously is sent to the information bit serial flash 140 and by latching line, the latch signal that controller produces (controller-generated) is sent to serial flash 140 by the SIO line.But instruction (instruction) or the part instruction of information bit complete, so it comprises order bit, address bit, data bit element or its combination.For example, instruction can be the instruction of reading that comprises read command, perhaps omits the instruction of reading of read command.
In step 220, serial flash 140 utilizes the latch signal of controller generation to latch the information bit that receives by the SIO line.Particularly, serial flash 140 utilizes latch signal that controller produces as synchronous basis, to replace the utilizing SCK clock to latch the information bit that receives by the SIO line in this step.Because may have clock skew between SCK clock and information bit, and the latch signal that controller produces is the match information bit preferably, so the latch signal that serial flash 140 utilizes controller to produce can latch the information bit of SIO line more accurately as synchronous basis.
Before the latch signal that sends the controller generation, serial flash controller 120 needs to take over latching the control of line, for example changes into high state/low state by latching line from quick condition.After the latch signal of completing the transmit control device generation, serial flash controller 120 need to be abandoned latching the control of line, for example changes into quick condition by latching line from high state/low state.If the information bit of the latch signal synchronized transmission that produces with controller consists of and reads instruction or part is read instruction, send read instruction after, the cycle that serial flash controller 120 and serial flash 140 will treat to wait in simulation stage (dummy phase) the SCK clock of predetermined quantity.Can abandon latching the control of line at this simulation stage serial flash controller 120.
If the information bit is the part of include instruction only, be the latch signal that produces of controller only the part of and instruction is overlapping, serial flash 140 can utilize latch signal that controller produces synchronously to latch information bit unit and to utilize the remainder of SCK clock synchronous latch instruction.For example, instruction can comprise SDR section and DDR section, and the information bit can only comprise the partly overlapping DDR section of latch signal that produces with controller.
Fig. 3 describes serial flash 140 in Fig. 1 how to utilize and latch line and guarantee synchronous method schematic diagram.In step 310, serial flash 140 synchronously is sent to the information bit serial flash controller 120 and by latching line, the latch signal that storer produces (memory-generated) is sent to serial flash controller 120 by the SIO line.For example, the information bit can comprise the data bit element that extracts from serial flash 140, reads instruction with what response serial flash controller 120 sent.
In step 320, serial flash controller 120 utilizes the latch signal of storer generation to latch the information bit that receives by the SIO line.Particularly, serial flash controller 120 utilizes latch signal that storer produces as synchronous basis, to replace the utilizing SCK clock to latch the information bit that receives by the SIO line in this step.Because may have clock skew between SCK clock and information bit, and the latch signal that storer produces is the match information bit preferably, so the latch signal that serial flash controller 120 utilizes storer to produce can latch the information bit of SIO line more accurately as synchronous basis.
Before the latch signal that sends the storer generation, serial flash 140 needs to take over latching the control of line, for example changes into high state/low state by latching line from quick condition.After completing the latch signal that sends the storer generation, serial flash 140 need to be abandoned latching the control of line, for example changes into quick condition by latching line from high state/low state.Read instruction if obtain the signal bits of the latch signal synchronized transmission that produces with storer with response, serial flash controller 120 and serial flash 140 will treat to wait in simulation stage the cycle of the SCK clock of predetermined quantity.Can abandon latching the control of line at this simulation stage serial flash 140.
Although Fig. 2 and method schematic diagram shown in Figure 3 are independent of each other, those skilled in the art still can be by operating the executable operations of serial flash module in conjunction with both, wherein this operation relates to two kinds communicate by letter (for example read operations) between serial flash controller 120 and serial flash 140.
Fig. 4 describes the schematic diagram of serial flash controller 120 according to the embodiment of the present invention.In the present embodiment, serial flash controller 120 comprises SCK module 410, SCS module 430, SIO module 450 and latch module 470.
SCK module 410 is responsible for sending continuously the SCK clock to the SCK line, and it comprises clock generator 412 and output buffer 414, and wherein output buffer 414 is as the center section between clock generator 412 and SCK line.Clock generator 412 is based on CLKin clock generating SCK clock, and wherein this CLKin is provided by oscillator (oscillator).SCS module 430 is responsible for sending the SCS signal to the SCS line, for example, no matter when allows communicating by letter between serial flash controller 120 and serial flash 140, by keeping the SCS signal in the situation that hang down state/high state and complete.SCS module 430 comprises chip selection processing unit 432 and output buffer 434, and wherein output buffer 434 is as the center section between chip selection processing unit 432 and SCS line.
SIO module 450 comprises data transmitter 451, output buffer 459, data receiver 461 and input buffer 469, wherein output buffer 459 is as the center section between data transmitter 451 and SIO line, and input buffer 469 is as the center section between data receiver 461 and SIO line.Utilize data transmitter 451 and output buffer 459, SIO module 450 sends the information bits by SIO alignment serial flash 140, and wherein information bit and controller that SCK clock or latch module 470 produce produce latch clock and synchronize (controller generation latch clock is indicated by the latch signal that controller produces).Utilize data receiver 461 and input buffer 469, SIO module 450 latchs the information bit that receives from serial flash 140 by the SIO line, wherein information bit and SCK clock or latch module 470 produce latch clock by the storer that latchs line and receive and synchronize (storer generation latch clock is indicated by the latch signal that storer produces).Then, data receiver 461 utilizes signal RDATA_IN to send to processor 110 the information bit that has latched, and signal RDATA_IN can be parallel signal.
Data transmitter 451 comprises SDR processing unit 452, DDR processing unit 454, multiplexer (Multiplexer, MUX) 456 and output control unit 458.When data transmitter 451 is operating, its signal OUTPUT_DATA_EN control that provides for processor 110 of MUX 456() allow the information bit is sent to serial flash 140 by SIO with output buffer 459, wherein the information bit is synchronizeed with SCK clock or controller generation latch clock, and wherein the information bit is produced by SDR processing unit 452 or DDR processing unit 454.
Latch module 470 comprises data and latchs generation unit 471, output control unit 473, output buffer 475, data and latch receiving element 477 and input buffer 479.In the situation that low speed or SDR operate, latch module 470 is inactive when serial flash 140; In the situation that high speed or DDR operate, latch module 470 is movable when serial flash 140.Particularly, when SIO module 450 at a high speed or when sending the information bit to serial flash 140 in the situation of DDR, data latch generation unit 471 can produce the latch signal that controller produces in addition.Output control unit 473 is guaranteed to synchronize by the information bit of SIO line transmission and the latch signal of controller generation with output buffer 475.When SIO module 450 at a high speed or when receiving the information bit from serial flash 140 in the situation of DDR, the latch signal that input buffer 479 can produce from serial flash 140 reception memorizers by latching line.Data latch receiving element 477 can control data receiver 461 to latch the information bit that the SIO line receives that passes through of synchronizeing with the latch signal of storer generation.Data latch receiving element 477 and can be controlled by the signal RDATA_EN that processor 110 provides.
Fig. 5 is the schematic diagram according to the serial flash 140 of embodiment of the present invention description.In the present embodiment, serial flash 140 comprises order and steering logic module 510, state recording device (status register) 520, address recording counter 530, high voltage generator 540, data buffer 550, X code translator 560, Y code translator 570 and memory array 580.Order and steering logic module 510 receive instructions and correspondingly control the running of serial flash 140 from serial flash controller 120.State recording device 520 records the treatment state of serial flash 140.Data buffer 550 will from the data bit element write store array 580 of order with 510 receptions of steering logic module, perhaps be obtained data for order and steering logic module 510 from memory array 580.Utilize address recording counter 530, high voltage generator 540, X code translator 560 and Y code translator 570, but order with steering logic module 510 data writing bits or obtain data bit element from the correct physical address of memory array 580.
When order and steering logic module 510 at a high speed or when receiving the information bit from serial flash controller 120 in the situation of DDR, it can receive the latch signal that controller produces in addition.Then, order can utilize the latch signal that controller produces to latch to synchronize the information bit that receives by the SIO line with steering logic module 510.When order and steering logic module 510 at a high speed or when sending data bit element to serial flash controller 120 in the situation of DDR, it can send in addition latch signal that storer produces and obtain data bit element with assistance serial flash controller 120 in correct sequential.
Fig. 6 to Figure 11 is the signal timing diagram that sends between serial flash controller 120 shown in Figure 1 and serial flash 140, its running Fig. 2 or method shown in Figure 3.At Fig. 6 to the example shown in Figure 8, serial flash controller 120 and serial flash 140 are just at Serial Peripheral Interface (SPI) (Serial Peripheral Interface, SPI) carry out read operation under pattern, and read operation comprises 8 order of the bit bits and 24 bit address bits, the simulation stage that continues 18 SCK clock period and at least 8 bit data bits that serial flash 140 returns of 120 issues of serial flash controller.At Fig. 9 to the example shown in Figure 11, serial flash controller 120 and serial flash 140 are just at quaternary Peripheral Interface (Quad Peripheral Interface, QPI) carry out read operation under pattern, and read operation comprises 8 order of the bit bits and 24 bit address bits, the simulation stage that continues 18 SCK clock period and at least 1 data byte (byte of data) that serial flash 140 returns of 120 issues of serial flash controller.Note that Fig. 6 to Figure 11 has only described the delay between data bit element and SCK clock, do not describe the delay between order (and/or address) bit and SCK clock.The stage of above-mentioned delay be uncertain and pattern more, therefore, the SCK clock is not synchronous ideal basic.
To example shown in Figure 11, serial flash 140 further can latch in correct sequential the DDR data bit element at the latch signal that data phase transmission storer produces to guarantee serial flash controller 120 at Fig. 6.In addition, in Fig. 7 and example shown in Figure 10, the latch signal that serial flash controller 120 further produces at the address phase transmit control device can latch in correct sequential DDR address bit to guarantee serial flash 140.In Fig. 8 and example shown in Figure 11, serial flash controller 120 further command phase and address phase all the latch signal that produces of transmit control device can latch in correct sequential DDR order bit and DDR address bit to guarantee serial storage 140.
If under continuous reading mode (being sometimes referred to as the enhancement mode reading mode), extremely Fig. 6 can omit by the command phase shown in Figure 11 with serial flash controller 140 for serial flash controller 120.So because read command can be omitted from read instruction under above-mentioned pattern.In other words, read instruction and can only comprise the address section.
Figure 12 to Figure 17 is the signal timing diagram that sends between serial flash controller 120 shown in Figure 1 and serial flash 140, the method that its running is shown in Figure 2.At Figure 12 to the example shown in Figure 14, serial flash controller 120 is just carried out write operation with serial flash 140 under the SPI pattern, and write operation comprises at least 8 bit data bits that 8 order of the bit bits of serial flash controller 120 issues and 24 bit address bits and serial flash controller 120 provide.At Figure 15 to the example shown in Figure 17, serial flash controller 120 is just carried out write operation with serial flash 140 under the QPI pattern, and write operation comprises at least 1 data byte that 8 order of the bit bits of serial flash controller 120 issues and 24 bit address bits and serial flash controller 120 provide.
In Figure 12 and example shown in Figure 15, serial flash controller 120 further can latch in correct sequential the DDR data bit element at the latch signal that the data phase transmit control device produces to guarantee serial flash 140.In Figure 13 and example shown in Figure 16, serial flash controller 120 further can latch in correct sequential DDR address bit and DDR data bit element at the latch signal that address phase and data phase transmit control device produce to guarantee serial flash 140.In Figure 14 and example shown in Figure 17, serial flash controller 120 further can latch in correct sequential DDR order bit, DDR address bit and DDR data bit element at the latch signal that command phase, address phase and data phase transmit control device produce to guarantee serial storage 140.
If under continuous WriteMode (being sometimes referred to as the enhanced write pattern), extremely Figure 12 can omit by the command phase shown in Figure 17 with serial flash controller 140 for serial flash controller 120.So because write order can omit from write command under above-mentioned pattern.In other words, write command can only comprise address section and data segments.
All can utilize in above embodiment and latch line and guarantee synchronously.Even the information bit and the SCK clock that send can not mate well, serial flash controller 120 or serial flash 140 still can utilize latch signal as synchronous foundation with at correct sequential latch information bit.Can allow like this serial flash controller 120 with serial flash 140 in the situation that high speed or DDR operate reliably.
Though the present invention discloses as above with preferred embodiment, but it is not to limit scope of the present invention, any person that is familiar with the technique without departing from the spirit and scope of the present invention, does impartial variation and modification, all belongs to covering scope of the present invention.
Claims (12)
1. method of being carried out by serial flash controller and serial flash, wherein this serial flash controller and this serial flash are by serial time clock line, a plurality of serial input/output line and latch line interconnection, and this serial time clock line transports serial clock to this serial flash from this serial flash controller, should be comprised by the method that serial flash controller and serial flash are carried out:
Latch latch signal that line produces from this serial flash synchronized transmission data bit element and storer respectively to this serial flash controller by this serial input/output line and this; And
The latch signal that allows this serial flash controller to utilize this storer to produce replaces this serial clock to latch this data bit element that receives by this serial input/output line.
2. the method for being carried out by serial flash controller and serial flash as claimed in claim 1, it is characterized in that, this serial flash is obtained this data bit element with the read instruction of response by this serial flash controller issue from memory array, and the method for this serial flash controller and serial flash execution further comprises: before sending this data bit element, rest on the cycle of this serial clock of simulation stage predetermined quantity.
3. the method for being carried out by serial flash controller and serial flash as claimed in claim 1, it is characterized in that, this serial flash is obtained this data bit element with the read instruction of response by the issue of this serial flash controller from memory array, and the method that this serial flash controller and serial flash are carried out further comprises: latch line respectively from this latch signal of reading instruction and controller generation of this serial flash controller synchronized transmission at least a portion to this serial flash by this serial input/output line and this; And the latch signal that allows this serial flash to utilize this controller to produce replaces this serial clock to read instruction with this that latchs this at least a portion of receiving by this serial input/output line.
4. the method for being carried out by serial flash controller and serial flash as claimed in claim 3, further comprise: when this serial flash controller and this serial flash during in simulation stage, allow this serial flash controller to abandon and this serial flash is taken over and controlled this and latch line, wherein this simulation stage continues the cycle of this serial clock of predetermined quantity.
5. method of being carried out by serial flash controller and serial flash, wherein this serial flash controller and this serial flash are by serial time clock line, a plurality of serial input/output line and latch line interconnection, and this serial time clock line transports serial clock to this serial flash from this serial flash controller, should be comprised by the method that serial flash controller and serial flash are carried out:
Latch latch signal that line produces from this serial flash controller synchronized transmission information bit and controller respectively to this serial flash by this serial input/output line and this; And
The latch signal that allows this serial flash to utilize this controller to produce replaces this serial clock to latch this information bit that receives by this serial input/output line.
6. the method for being carried out by serial flash controller and serial flash as claimed in claim 5, it is characterized in that, this information bit comprises at least a portion of reading instruction of this serial flash controller issue, and the method for this serial flash controller and serial flash execution further comprises: after this reads instruction in transmission, rest on the cycle of this serial clock of simulation stage predetermined quantity.
7. the method for being carried out by serial flash controller and serial flash as claimed in claim 6, further comprise: after this simulation stage, latch latch signal that line produces from this serial flash synchronized transmission data bit element and storer respectively to this serial flash controller by this serial input/output line and this, wherein this data bit element responds this and reads instruction; And the latch signal that allows this serial flash controller to utilize this storer to produce replaces this serial clock to latch this data bit element that receives by this serial input/output line.
8. the method for being carried out by serial flash controller and serial flash as claimed in claim 7, further comprise: when this serial flash controller and this serial flash during in this simulation stage, allow this serial flash controller to abandon and this serial flash is taken over and controlled this and latch line.
9. serial flash controller, wherein this serial flash controller and serial flash are by serial time clock line, a plurality of serial input/output line and latch the line interconnection, and this serial flash controller comprises:
The serial clock module is configured to send serial clock by this serial flash of this serial clock alignment;
Serial input/output module is configured to send the information bit and pass through this serial input/output line from this serial flash receive data bit to this serial flash by this serial input/output line; And
Latch module, be configured to latch by this latch signal that this serial flash transmit control device of alignment produces, thereby receiving this information bit with this serial flash synchronizes, perhaps be configured to latch by this latch signal that line produces from this serial flash reception memorizer, thereby synchronize with this data bit element that latchs by this serial input/output line reception.
10. serial flash controller as claimed in claim 9, it is characterized in that, before receiving this data bit element by this serial input/output line from this serial flash, configure the cycle that this serial flash controller rests on this serial clock of simulation stage predetermined quantity.
11. a serial flash, wherein this serial flash and serial flash controller are by serial time clock line, a plurality of serial input/output line and latch line interconnection, and this serial flash comprises:
Memory array; And
Order and steering logic module connect this serial time clock line, these a plurality of serial input/output lines and this latchs line, configure this order and the steering logic module is as follows:
Receive serial clock by this serial time clock line from this serial flash controller;
According to this memory array of instruction accessing that receives from this serial flash controller by this serial flash input/output line; And
Latch the information bit that receives from this serial flash controller by this serial input/output line, this information bit with latch the latch signal that controller that line receives from this serial flash controller produces by this and synchronize, perhaps latch line respectively to the latch signal of this serial flash controller synchronized transmission data bit element and storer generation by this serial input/output line and this.
12. serial flash as claimed in claim 11 is characterized in that, after reading instruction by this serial input/output line from this serial flash controller reception, configures the cycle that this serial flash rests on this serial clock of simulation stage predetermined quantity.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161535477P | 2011-09-16 | 2011-09-16 | |
| US61/535,477 | 2011-09-16 | ||
| BR1020120087766 | 2012-04-13 | ||
| BR102012008776A BR102012008776A8 (en) | 2012-04-13 | 2012-04-13 | SERIAL FLASH CONTROLLER, SERIAL FLASH MEMORY, AND METHOD THEREOF |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103123614A true CN103123614A (en) | 2013-05-29 |
| CN103123614B CN103123614B (en) | 2016-01-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210332366.XA Expired - Fee Related CN103123614B (en) | 2011-09-16 | 2012-09-10 | The method of serial flash controller, serial flash and execution thereof |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN103123614B (en) |
| BR (1) | BR102012008776A8 (en) |
| TW (1) | TWI488184B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105446731A (en) * | 2014-09-24 | 2016-03-30 | 旺宏电子股份有限公司 | Method and device for command processing |
| CN111008171A (en) * | 2019-11-25 | 2020-04-14 | 中国兵器工业集团第二一四研究所苏州研发中心 | Communication IP circuit with serial FLASH interface control |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010094068A (en) * | 2000-04-03 | 2001-10-31 | 강재철 | Hardware device for the data protection of personal computer which includes control driver program for data encryption, decryption and I/O devices(USB, printer port, serial port, FDD, etc.) |
| US6816420B1 (en) * | 2003-07-29 | 2004-11-09 | Xilinx, Inc. | Column redundancy scheme for serially programmable integrated circuits |
| CN1790548A (en) * | 2004-12-17 | 2006-06-21 | 三星电子株式会社 | Flash memory data storage apparatus |
| CN101677019A (en) * | 2008-09-18 | 2010-03-24 | 深圳市朗科科技股份有限公司 | Production line reading method and system of flash memory |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7475174B2 (en) * | 2004-03-17 | 2009-01-06 | Super Talent Electronics, Inc. | Flash / phase-change memory in multi-ring topology using serial-link packet interface |
| US8996784B2 (en) * | 2006-03-09 | 2015-03-31 | Mediatek Inc. | Command controller, prefetch buffer and methods for accessing a serial flash in an embedded system |
| US20070260778A1 (en) * | 2006-04-04 | 2007-11-08 | Ming-Shiang Lai | Memory controller with bi-directional buffer for achieving high speed capability and related method thereof |
| TWI351606B (en) * | 2007-10-26 | 2011-11-01 | Sunplus Technology Co Ltd | Memory module and control method of serial periphe |
-
2012
- 2012-04-13 BR BR102012008776A patent/BR102012008776A8/en not_active Application Discontinuation
- 2012-09-10 CN CN201210332366.XA patent/CN103123614B/en not_active Expired - Fee Related
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010094068A (en) * | 2000-04-03 | 2001-10-31 | 강재철 | Hardware device for the data protection of personal computer which includes control driver program for data encryption, decryption and I/O devices(USB, printer port, serial port, FDD, etc.) |
| US6816420B1 (en) * | 2003-07-29 | 2004-11-09 | Xilinx, Inc. | Column redundancy scheme for serially programmable integrated circuits |
| CN1790548A (en) * | 2004-12-17 | 2006-06-21 | 三星电子株式会社 | Flash memory data storage apparatus |
| CN101677019A (en) * | 2008-09-18 | 2010-03-24 | 深圳市朗科科技股份有限公司 | Production line reading method and system of flash memory |
Non-Patent Citations (1)
| Title |
|---|
| 李佳琦: "基于固态硬盘的闪存阵列并行结构设计", 《微电子学与计算机》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105446731A (en) * | 2014-09-24 | 2016-03-30 | 旺宏电子股份有限公司 | Method and device for command processing |
| CN105446731B (en) * | 2014-09-24 | 2020-04-14 | 旺宏电子股份有限公司 | Method and device for processing instruction |
| CN111008171A (en) * | 2019-11-25 | 2020-04-14 | 中国兵器工业集团第二一四研究所苏州研发中心 | Communication IP circuit with serial FLASH interface control |
| CN111008171B (en) * | 2019-11-25 | 2020-12-22 | 中国兵器工业集团第二一四研究所苏州研发中心 | Communication IP circuit with serial FLASH interface control |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103123614B (en) | 2016-01-20 |
| BR102012008776A8 (en) | 2017-07-25 |
| TWI488184B (en) | 2015-06-11 |
| BR102012008776A2 (en) | 2013-11-26 |
| TW201342379A (en) | 2013-10-16 |
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