CN101677019B - Production line reading method and system of flash memory - Google Patents
Production line reading method and system of flash memory Download PDFInfo
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- CN101677019B CN101677019B CN200810211885.4A CN200810211885A CN101677019B CN 101677019 B CN101677019 B CN 101677019B CN 200810211885 A CN200810211885 A CN 200810211885A CN 101677019 B CN101677019 B CN 101677019B
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Abstract
The invention relates to a flash memory and provides a production line reading method of a flash memory. The system comprises a flash memory and a controller, wherein the flash memory supports the expanded data output mode, memorizes data and outputs data to an input-output bus; the controller is connected with the flash memory through the input-output bus and carries out the data interaction; the controller transmits read pulses to the flash memory and latches data output to the input-output bus by the flash memory; while the flash memory outputs the data to the input-output bus according to the current mth read pulse, the controller continuously transmits the (m+1)th, (m+2)th, ..., (m+n)th read pulses to the flash memory and latches the corresponding data at a proper time point; and n is equal to or greater than 1. The invention also provides a production line reading method of a flash memory. In the invention, the controller continuously transmits a plurality of read pulses to the flash memory and latches the data output by the flash memory at a proper time point so as to increase the reading speed of the flash memory.
Description
Technical field
The present invention relates to flash memory (Flash Memory is called for short " flash memory ") technical field, more particularly, relate to a kind of production line reading method and system of flash memory.
Background technology
The time of flash memory reading out data exports data to time composition in input and output (Input/Output is called for short " I/O ") bus by inner reading out data time of flash memory and flash memory.
Support growth data output (Extended Data Out, be called for short " EDO ") flash memory of pattern, the transmission time of data equals data of flash drive is multiplied by the number of data to the time in bus, because bus bit wide is limited, it is longer that data are transferred to time in controller from the buffer zone of flash memory.Read the time certain in the situation that in flash memory inside, the transmission time that reduces data can greatly shorten the time of reading flash data.As shown in Figure 1, read technology according to existing streamline, before data transmission, the reading order that flash memory sends according to controller reads buffer unit by data from storage array.At data transfer phase, controller reads flash memory by following step: in step S101, controller sends m read pulse to flash memory; In step S102, according to the cycle of read pulse (tRC), through time of tREA, flash memory is postponed m data to rush device and be driven in I/O bus; In step S103, on the time point in a read pulse cycle (tRC) data in the middle of bus I/O is latched into first in first out unit (FirstInput First Output, be called for short " FIFO ").In step S104, controller sends next read pulse to flash memory on the time point of tRC.Repeat this step, until that needed data all read is complete.In this scheme, if read correct data, necessary tRC>tREA, be transmission cycle of read pulse must be greater than data to be driven to the time in I/O bus, in other words, must, after the data of previous read pulse are driven in I/O bus, could send next read pulse.This condition restriction the reading speed of flash memory.
Therefore propose a kind of new flash memory read method, improve the reading speed of flash memory.
Summary of the invention
One of object of the present invention is to provide a kind of production line reading method of flash memory, is intended to solve the slow problem of flash memory reading speed in prior art.
In order to realize goal of the invention, described system comprises:
Support edo mode, storage data and data exported to the flash memory of input/output bus, and the controller that is connected and carries out data interaction by input/output bus with described flash memory, described controller sends read pulse to flash memory, and latch flash memory exports the data of input/output bus to.Described controller exports data in the time of input/output bus according to current m read pulse at flash memory, sends continuously m+1, m+2 ..., m+n read pulse is to flash memory, and the data latch of naming a person for a particular job corresponding at reasonable time is come in;
Described n >=1.
Described controller comprises:
Register cell, for the waveform of the read pulse that outputs to flash memory is set, and the time point of latch data that flash memory is exported;
Steering logic unit, the waveform of the read pulse signal that register cell is produced is sent to flash memory, and controls the data of first in first out unit latches flash memory output;
First in first out unit, the data for latch from flash memory output.
Described register cell comprises:
Register A, setting outputs to the waveform width of the read pulse signal of flash memory;
Register B, arranges cycle of read pulse;
Register C, arranges the time point of latch data that flash memory is exported.
In order to realize better goal of the invention,
The value of described register B is greater than the value of register A, and is less than the value of register C.
Described flash memory comprises:
Cells of memory arrays, storage data and according to the reading order reading out data of controller to buffer unit;
Buffer unit, the data that cells of memory arrays is read are temporary, and according to the read pulse of controller, data are delivered in input/output bus.
In order to realize better goal of the invention, described method comprises:
Steps A. controller sends current m read pulse to flash memory;
Current m the read pulse that described in step B., controller sends according to controller at flash memory also exported in the time of corresponding data, m+1 after sending continuously, and m+2 ..., m+n read pulse is to flash memory;
The data that described in step C., controller is exported according to described each read pulse at suitable time point latch flash memory;
Described n >=1.
Before described steps A, also comprise:
The width of read pulse signal waveform is set;
The cycle of read pulse is set;
The time point of latch flash memory output data is set.
Described step C comprises:
Step C1. controller latch flash memory is according to current m the data that read pulse is exported;
Step C2. controller latch flash memory is according to m+1, m+2 ..., m+n the data that read pulse is exported.
The cycle of the read pulse that further, described controller sends is less than the time of flash memory output data.
As from the foregoing, the present invention reads in process flash memory, difference with the prior art is that controller sends continuously multiple read pulses to flash memory in flash memory is read time of current data, and the data of exporting at reasonable time point latch flash memory, has therefore improved the reading speed of flash memory.
Brief description of the drawings
Fig. 1 is the production line reading method process flow diagram of prior art flash memory;
Fig. 2 is the reading system structural representation of flash memory in one of them embodiment of the present invention;
Fig. 3 is the inner structure schematic diagram of one of them embodiment middle controller of the present invention and flash memory;
Fig. 4 is the syndeton schematic diagram of register in one of them embodiment of the present invention;
Fig. 5 is the read method process flow diagram of flash memory when n=1 in one of them embodiment of the present invention;
Fig. 6 is the working timing figure that in one of them embodiment of the present invention, n=1 Time Controller sends read pulse;
Fig. 7 is the method flow diagram of flash memory output data in one of them embodiment of the present invention;
Fig. 8 is the schematic flow sheet of n=1 Time Controller latch data that flash memory is exported in one of them embodiment of the present invention.
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.
Embodiment
In the present invention, controller sends continuously multiple read pulses to flash memory in flash memory is read time of current data, and in the data of suitable time point latch flash memory output, has improved the reading speed of flash memory.
Fig. 2 shows the structure of the reading system of flash memory in one embodiment of the present of invention, this system comprises controller 10, is connected with controller 10 and carries out the flash memory 20 of data interaction and for being connected controller 10 and flash memory 20 and carrying out input and output (Input/Output, be called for short " the I/O ") bus 30 of data transmission.It should be noted that in all diagrams of the present invention, the annexation between each equipment is for the needs of clear its information interaction of explaination and control procedure, therefore should be considered as annexation in logic, and should not only limit to physical connection.It should be noted that in addition, the communication mode between each functional module can be taked multiple, and protection scope of the present invention should not be defined as the communication mode of certain particular type.Wherein:
Controller 10, is connected and is carried out data interaction by input and output (Input/Output is called for short " I/O ") bus 30 with flash memory 20, send read pulse to flash memory 20, and latch flash memory 20 outputs to the data of I/O bus 30 according to read pulse.
Flash memory 20, supports EDO pattern, is connected by I/O bus 30 with controller 10, for storing data, and exports data to I/O bus 30 according to the read pulse of controller transmission, reads and latch for controller 10.
I/O bus 30, connects controller 10 and flash memory 20 and carries out data transmission, the data that temporary flash memory 20 is exported.
In a preferred embodiment, controller 10 sends read pulse and meets to the frequency of operation of flash memory 20 requirement of flash memory 20 reading out datas.For example: in one embodiment, in flash memory 20, receive the time tREA that read pulse is driven in I/O bus 30 to data and have a maximal value, then n the read pulse time tRLOH that step-down is cancelled to a front m data again has a minimum value, more than the frequency of operation of controller 10 reaches 1/tRLOH, can within the tRLOH time, send out one or n read pulse.
In another preferred embodiment, controller 10 reads in current m data procedures at flash memory 20, continuously by m+1, and m+2 ..., m+n read pulse is sent to flash memory 20, wherein, and n >=1.
Fig. 3 shows the structure of one embodiment of the present of invention middle controller 10 and flash memory 20, and controller 10 comprises:
Register cell 101, for width and the cycle of the read pulse that outputs to flash memory 20 are set, and the time point of latch flash memory 20 data of exporting;
Steering logic unit 102, is connected with register cell 101 and first in first out unit 103 and carries out data interaction, is sent to flash memory 20 for the signal waveform that register cell is produced;
First in first out unit 103, is connected with controller logic unit 102 and carries out data interaction, the data of exporting from flash memory 20 for latch.
Flash memory 20 comprises:
Cells of memory arrays 201, exports data to buffer unit 202 for the read pulse of storing data and send according to controller 10;
Buffer unit 202, is connected with cells of memory arrays and carries out data interaction, for the read pulse sending according to controller 10, data is transported to I/O bus 30.
Fig. 4 shows the structure of register cell 101 in one embodiment of the present of invention, and this register cell 101 comprises:
(1) register A, is connected with steering logic unit 102 and carries out data interaction, and its value is for arranging the waveform width of the read pulse signal that outputs to flash memory 20;
(2) register B, is connected with steering logic unit 102 and carries out data interaction, and its value is for arranging the wave period of read pulse signal;
(3) register C, is connected and carries out data interaction with first in first out unit (First Input First Output is called for short " FIFO ") 103, and its value is for controlling the time point of data in FIFO latch I/O bus 30.
In a preferred embodiment, the value of register B is greater than the value of register A, and is less than the value of register C, i.e. read pulse cycle tRC is less than the time point of latch data, and system works is at pipeline state.In one embodiment, suppose that the time (tREA) that current m data are urged to I/O bus 30 by flash memory 20 is 25ns to the maximum, the individual read pulse of rear n (n >=1) time (tRLOH) that step-down is cancelled to a front m data is again minimum is 10ns, the minimum pulse width (tRP) of read pulse is 10ns, can be set for 20ns the read pulse cycle (tRC), the time point that latch data is set is 28ns, and the course of work of controller 10 is as follows:
Steering logic unit 102 is in tRC (20ns) moment, the read pulse of rear one-period data is sent to flash memory 20 in advance, and the value control FIFO of register C at tREA (25ns) afterwards, and it in the scope of tRC+tRLOH (20ns+10ns), is the time point latch data of 28ns.Between the time range of the valid data maximal value 25ns to tRC+tRLOH (30ns) that is tREA, the data of now latch are valid data.
Fig. 5 shows the production line reading method flow process of flash memory in an embodiment in the present invention, the system architecture of the method flow process based on shown in Fig. 2, carry out institute in steps before, the read command that flash memory 20 sends according to controller 10, reads buffer unit 202 by corresponding data from cells of memory arrays 201.Detailed process is as follows:
In step S501, controller 10 sends m read pulse to flash memory 20;
In step S502, flash memory 20 is exported the data of corresponding m read pulse to I/O bus 30, and controller sends m+n read pulse to flash memory 20;
In step S503, the data that controller 10 is exported according to each read pulse at suitable time point latch flash memory 20.
Wherein, n >=1.
In a preferred embodiment, controller 10 is exported according to m read pulse at suitable time point successively latch flash memory 20 data and flash memory 20 data that individual read pulse is exported according to m+n (1).
In another preferred embodiment, controller 10 sends first reading order (such as " 00H ") to flash memory 20, flash memory 20 reads data buffer unit 202 from cells of memory arrays 201, after pending buffer device unit 202 is ready, controller 10 sends second reading order (such as " 30H ") again to flash memory 20.Meanwhile, controller sends m read pulse, and flash memory 20 is by the data-driven in buffer unit 202 to I/O bus 30, and when data are not driven into I/O bus 30, controller sends m+1 read pulse.In the time that data are driven into I/O bus 30, controller 10 m data in latch I/O bus 30 and the individual data of m+n (1) continuously successively.Repeat this flow process, until that all data read is complete.
N=2 in another preferred embodiment, in the present invention, the detailed process of the production line reading method of flash memory is, controller sends m read pulse, flash memory 20 starts the data-driven in buffer unit 202 to I/O bus 30, when flash memory 20 is not also driven into I/O bus 30 by data, controller sends m+2 read pulse.In the time that flash memory 20 is driven into data I/O bus 30, controller 10 m data and m+2 data in latch I/O bus 30 continuously successively.Repeat this flow process, until that all data read is complete.
Fig. 6 shows n=1 Time Controller 10 in one embodiment of the present of invention and sends the work schedule of read pulse, and detailed process is as follows:
Controller 10 sends m read pulse to flash memory 20 through the time of tRC, flash memory 20 by data by buffer unit 202, time through tREA transfers data to I/O bus 30, and within the tRC moment, controller 10 sends m+1 read pulse to flash memory 20, and m+1 data occur, by the scope of the time (be greater than tREA, be less than tROH+tRC) before cancelling, data being latching to FIFO in I/O bus 30.The rest may be inferred, and in the time of n=2, in the moment of tRC, controller 10 sends m+2 read pulse to flash memory 20.
Fig. 7 shows flash memory 20 in one embodiment of the present of invention and exports the flow process of data, the system architecture of this flow process based on shown in Fig. 2, and detailed process is as follows:
In step S701, the read pulse that flash memory 20 sends according to controller 10 reads buffer unit 202 by data from cells of memory arrays 201;
In step S702, buffer unit 202 according to the read pulse cycle by data-driven to I/O bus 30.
In a preferred embodiment, flash memory 20 is within the time in current read pulse cycle, and next the cycle read pulse sending according to controller reads buffer unit 202 by data from reading cells of memory arrays 201.
In another preferred embodiment, buffer unit 202 is greater than data-driven the cycle of read pulse to the time of I/O bus 30.
Fig. 8 shows in one embodiment of the present of invention in the time of n=1, the course of work of controller 10 latch datas, the system architecture of the course of work of this controller 10 based on Fig. 2, first in first out unit 103 is connected with register cell 101 and steering logic unit 102, and by the input and output of data in counter controls flash memory 20.Wherein:
First in first out unit 103 is connected with the register C in register cell 101 and carries out data interaction, and is connected with flash memory 20 by I/O bus 30.In a preferred embodiment, the value of the register C being connected with first in first out unit 103 is for the time point of latch data is set, and its value is greater than and is respectively used to the value of the register A that read pulse width is set and for the value of register B of data read cycle of flash memory 20 is set.For example, if the value of register C is " 4 ", the value of register B is " 2 ", and the value of register A is " 1 ".In one embodiment, register A and register B use same counter 30, and arranging of this counter 30 is as follows: when the count value meter of counter 30 is to time " 0 ", steering logic unit 102 sends read pulse; When the count value meter of counter 30 is to time register A settings " 1 " (read pulse width), read pulse is drawn high, and then this high level remains to the end of read cycle always; And in the time that the next count value of counter 30 is register B settings " 2 " (read pulse cycle), the count value of counter 30 clear " 0 ".Register C uses another one counter 40, and when the count value of counter 40 is the settings " 4 " (time point of latch data) of register C, the value that counter 40 is set becomes the next count value " 2 " of counter 30.Like this, even the value of the value > register B of register C, the count cycle of the count cycle sum counter 30 of counter 40 still can be consistent.In the time that the next count value of counter 40 is the settings " 4 " of register C, lock valid data to deposit into from I/O bus 30 in first in first out unit 103.This process constantly circulates, until that needed data read is complete.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. the streamline reading system of a flash memory, comprise the flash memory of supporting edo mode, storage data and data being exported to input/output bus, and the controller that is connected and carries out data interaction by input/output bus with described flash memory, described controller sends read pulse to flash memory, and latch flash memory exports the data of input/output bus to, it is characterized in that
Described controller exports data in the time of input/output bus according to current m read pulse at flash memory, send continuously m+1, m+2 ..., m+n read pulse be to flash memory, and come in the reasonable time data latch that flash memory exports according to read pulse described in each of naming a person for a particular job; Described n >=1,
The cycle that described controller sends read pulse is less than flash memory by the time of data output.
2. the streamline reading system of flash memory according to claim 1, is characterized in that, described controller comprises:
Register cell, for the waveform of the read pulse that outputs to flash memory is set, and the time point of the data exported of latch flash memory;
Steering logic unit, the waveform of the read pulse signal that register cell is produced is sent to flash memory, and controls the data of first in first out unit latches flash memory output;
First in first out unit, the data for latch from flash memory output.
3. the streamline reading system of flash memory according to claim 2, is characterized in that, described register cell comprises:
Register A, setting outputs to the waveform width of the read pulse signal of flash memory;
Register B, arranges cycle of read pulse;
Register C, arranges the time point of latch data that flash memory is exported.
4. the streamline reading system of flash memory according to claim 3, is characterized in that, the value of described register B is greater than the value of register A, and the value of register B is less than the value of register C.
5. the streamline reading system of flash memory according to claim 1 and 2, is characterized in that, described flash memory comprises:
Cells of memory arrays, storage data and according to the reading order reading out data of controller to buffer unit;
Buffer unit, the data that cells of memory arrays is read are temporary, and according to the read pulse of controller, data are delivered in input/output bus.
6. a production line reading method for flash memory, based on comprising the reading system of controller with the flash memory of support edo mode, is characterized in that, comprises the following steps:
Steps A. controller sends current m read pulse to flash memory;
In the time of current m the corresponding data that read pulse is exported that described in step B., controller sends according to controller at flash memory, m+1 after sending continuously, m+2 ..., m+n read pulse is to flash memory;
The data that described in step C., controller is exported according to read pulse described in each at suitable time point latch flash memory; Described n >=1,
The cycle of described controller transmission read pulse is less than the time of flash memory output data.
7. the production line reading method of flash memory according to claim 6, is characterized in that, before described steps A, also comprises:
The width of read pulse signal waveform is set;
The cycle of read pulse is set;
The time point of latch flash memory output data is set.
8. the production line reading method of flash memory according to claim 6, is characterized in that, described step C comprises:
Step C1. controller latch flash memory is according to current m the data that read pulse is exported;
Step C2. controller latch flash memory is according to m+1, m+2 ..., m+n the data that read pulse is exported.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810211885.4A CN101677019B (en) | 2008-09-18 | 2008-09-18 | Production line reading method and system of flash memory |
| HK10109037.4A HK1142714A1 (en) | 2008-09-18 | 2010-09-21 | Production line reading method and system of flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810211885.4A CN101677019B (en) | 2008-09-18 | 2008-09-18 | Production line reading method and system of flash memory |
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| CN101677019A CN101677019A (en) | 2010-03-24 |
| CN101677019B true CN101677019B (en) | 2014-07-16 |
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| CN200810211885.4A Active CN101677019B (en) | 2008-09-18 | 2008-09-18 | Production line reading method and system of flash memory |
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| HK (1) | HK1142714A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US8495330B2 (en) * | 2010-04-02 | 2013-07-23 | Intel Corporation | Method and apparatus for interfacing with heterogeneous dual in-line memory modules |
| BR102012008776A8 (en) * | 2012-04-13 | 2016-12-13 | Mediatek Inc | SERIAL FLASH CONTROLLER, SERIAL FLASH MEMORY, AND METHOD THEREOF |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1571951A (en) * | 2001-08-23 | 2005-01-26 | 集成装置技术公司 | FIFO memory devices having single data rate (sdr) and dual data rate (ddr) capability |
| CN1790548A (en) * | 2004-12-17 | 2006-06-21 | 三星电子株式会社 | Flash memory data storage apparatus |
| CN101233575A (en) * | 2005-07-29 | 2008-07-30 | 国际商业机器公司 | Memory control method and memory system |
-
2008
- 2008-09-18 CN CN200810211885.4A patent/CN101677019B/en active Active
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- 2010-09-21 HK HK10109037.4A patent/HK1142714A1/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1571951A (en) * | 2001-08-23 | 2005-01-26 | 集成装置技术公司 | FIFO memory devices having single data rate (sdr) and dual data rate (ddr) capability |
| CN1790548A (en) * | 2004-12-17 | 2006-06-21 | 三星电子株式会社 | Flash memory data storage apparatus |
| CN101233575A (en) * | 2005-07-29 | 2008-07-30 | 国际商业机器公司 | Memory control method and memory system |
Non-Patent Citations (2)
| Title |
|---|
| 王宏强等.面向闪存类存储设备嵌入式文件系统研究与实现.《计算机应用研究》.2008,第25卷(第3期),814-815，819. |
| 面向闪存类存储设备嵌入式文件系统研究与实现;王宏强等;《计算机应用研究》;20080330;第25卷(第3期);814-815，819 * |
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| CN101677019A (en) | 2010-03-24 |
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